V4L/DVB (9658): em28xx: use em28xx_write_reg() for i2c clock setup
Convert the calls that write the i2c clock register over to the new em28xx_write_reg() function that allows for or'ing bits Signed-off-by: Devin Heitmueller <devin.heitmueller@gmail.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Devin Heitmueller
Mauro Carvalho Chehab
parent
b697248994
commit
23159a0bfc
@ -1400,7 +1400,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2883_BOARD_KWORLD_HYBRID_A316:
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case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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msleep(50);
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/* Sets GPO/GPIO sequences for this device */
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@ -1412,7 +1414,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2882_BOARD_TERRATEC_HYBRID_XS:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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msleep(50);
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/* should be added ir_codes here */
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@ -1432,7 +1436,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2870_BOARD_KWORLD_350U:
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case EM2881_BOARD_DNT_DA2_HYBRID:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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msleep(50);
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/* NOTE: EM2881_DNT_DA2_HYBRID spend 140 msleep for digital
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@ -1449,7 +1455,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2880_BOARD_MSI_DIGIVOX_AD:
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case EM2880_BOARD_MSI_DIGIVOX_AD_II:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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msleep(50);
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/* Sets GPO/GPIO sequences for this device */
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@ -1466,7 +1474,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2861_BOARD_PLEXTOR_PX_TV100U:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* FIXME guess */
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/* Turn on analog audio output */
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em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1);
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@ -1475,7 +1485,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2861_BOARD_KWORLD_PVRTV_300U:
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case EM2880_BOARD_KWORLD_DVB_305U:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x4c", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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msleep(10);
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em28xx_write_regs(dev, 0x08, "\x6d", 1);
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msleep(10);
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@ -1485,7 +1497,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2870_BOARD_KWORLD_355U:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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msleep(50);
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/* Sets GPO/GPIO sequences for this device */
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@ -1494,7 +1508,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2870_BOARD_COMPRO_VIDEOMATE:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* TODO: someone can do some cleanup here...
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not everything's needed */
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em28xx_write_regs(dev, 0x04, "\x00", 1);
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@ -1513,7 +1529,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2870_BOARD_TERRATEC_XS_MT2060:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* this device needs some gpio writes to get the DVB-T
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demod work */
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em28xx_write_regs(dev, 0x08, "\xfe", 1);
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@ -1525,7 +1543,10 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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break;
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case EM2870_BOARD_PINNACLE_PCTV_DVB:
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* this device needs some gpio writes to get the
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DVB-T demod work */
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em28xx_write_regs(dev, 0x08, "\xfe", 1);
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@ -1541,7 +1562,9 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2820_BOARD_GADMEI_UTV310:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* Turn on analog audio output */
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em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1);
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break;
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@ -1549,20 +1572,27 @@ void em28xx_pre_card_setup(struct em28xx *dev)
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case EM2860_BOARD_GADMEI_UTV330:
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/* Turn on IR */
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x07", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* should be added ir_codes here */
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break;
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case EM2820_BOARD_MSI_VOX_USB_2:
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em28xx_write_regs(dev, EM28XX_R0F_XCLK, "\x27", 1);
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x40", 1);
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM28XX_I2C_FREQ_100_KHZ);
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/* enables audio for that device */
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em28xx_write_regs_req(dev, 0x00, 0x08, "\xfd", 1);
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break;
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case EM2874_BOARD_PINNACLE_PCTV_80E:
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/* Set 400 KHz clock */
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em28xx_write_regs(dev, EM28XX_R06_I2C_CLK, "\x45", 1);
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/* Set 400 KHz clock and select secondary i2c bus */
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em28xx_write_reg(dev, EM28XX_R06_I2C_CLK,
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EM28XX_I2C_CLK_WAIT_ENABLE |
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EM2874_I2C_SECONDARY_BUS_SELECT |
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EM28XX_I2C_FREQ_400_KHZ);
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dev->digital_gpio = em2874_pinnacle_80e_digital;
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break;
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@ -32,6 +32,19 @@
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#define EM28XX_R08_GPIO 0x08 /* em2820 or upper */
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#define EM28XX_R06_I2C_CLK 0x06
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/* em28xx I2C Clock Register (0x06) */
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#define EM28XX_I2C_CLK_ACK_LAST_READ 0x80
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#define EM28XX_I2C_CLK_WAIT_ENABLE 0x40
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#define EM28XX_I2C_EEPROM_ON_BOARD 0x08
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#define EM28XX_I2C_EEPROM_KEY_VALID 0x04
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#define EM2874_I2C_SECONDARY_BUS_SELECT 0x04 /* em2874 has two i2c busses */
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#define EM28XX_I2C_FREQ_1_5_MHZ 0x03 /* bus frequency (bits [1-0]) */
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#define EM28XX_I2C_FREQ_25_KHZ 0x02
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#define EM28XX_I2C_FREQ_400_KHZ 0x01
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#define EM28XX_I2C_FREQ_100_KHZ 0x00
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#define EM28XX_R0A_CHIPID 0x0a
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#define EM28XX_R0C_USBSUSP 0x0c /* */
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