i7core_edac: Add a memory check routine, based on device 3 function 4
This function appears only on Xeon 5500 datasheet. Yet, testing with a Xeon 3503 showed that this is also implemented on other Nehalem processors. At the first read, MC_TEST_ERR_RCV1 and MC_TEST_ERR_RCV0 can contain any value. Modify CE error logic to update the error count only after the second read. An alternative approach would be to do a write at rcv0 and rcv1 registers, but it seemed better to keep they untouched, since BIOS might eventually assume that they are exclusive for their usage. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Mauro Carvalho Chehab
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87d1d272ba
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442305b152
@ -62,6 +62,18 @@
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#define MC_STATUS 0x4c
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#define MC_MAX_DOD 0x64
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/*
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* OFFSETS for Device 3 Function 4, as inicated on Xeon 5500 datasheet:
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* http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
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*/
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#define MC_TEST_ERR_RCV1 0x60
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#define DIMM2_COR_ERR(r) ((r) & 0x7fff)
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#define MC_TEST_ERR_RCV0 0x64
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#define DIMM1_COR_ERR(r) (((r) >> 16) & 0x7fff)
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#define DIMM0_COR_ERR(r) ((r) & 0x7fff)
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/* OFFSETS for Devices 4,5 and 6 Function 0 */
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#define MC_CHANNEL_DIMM_INIT_PARAMS 0x58
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@ -136,8 +148,9 @@
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*/
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#define NUM_CHANS 3
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#define NUM_MCR_FUNCS 4
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#define NUM_CHAN_FUNCS 3
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#define MAX_DIMMS 3 /* Max DIMMS per channel */
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#define MAX_MCR_FUNC 4
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#define MAX_CHAN_FUNC 3
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struct i7core_info {
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u32 mc_control;
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@ -159,8 +172,8 @@ struct i7core_inject {
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};
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struct i7core_channel {
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u32 ranks;
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u32 dimms;
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u32 ranks;
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u32 dimms;
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};
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struct pci_id_descr {
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@ -171,11 +184,16 @@ struct pci_id_descr {
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};
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struct i7core_pvt {
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struct pci_dev *pci_mcr[NUM_MCR_FUNCS];
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struct pci_dev *pci_ch[NUM_CHANS][NUM_CHAN_FUNCS];
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struct pci_dev *pci_mcr[MAX_MCR_FUNC + 1];
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struct pci_dev *pci_ch[NUM_CHANS][MAX_CHAN_FUNC + 1];
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struct i7core_info info;
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struct i7core_inject inject;
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struct i7core_channel channel[NUM_CHANS];
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int ce_count_available;
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unsigned long ce_count[MAX_DIMMS]; /* ECC corrected errors counts per dimm */
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int last_ce_count[MAX_DIMMS];
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};
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/* Device name and register DID (Device ID) */
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@ -749,6 +767,19 @@ static ssize_t i7core_inject_enable_show(struct mem_ctl_info *mci,
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return sprintf(data, "%d\n", pvt->inject.enable);
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}
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static ssize_t i7core_ce_regs_show(struct mem_ctl_info *mci, char *data)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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if (!pvt->ce_count_available)
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return sprintf(data, "unavailable\n");
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return sprintf(data, "dimm0: %lu\ndimm1: %lu\ndimm2: %lu\n",
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pvt->ce_count[0],
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pvt->ce_count[1],
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pvt->ce_count[2]);
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}
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/*
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* Sysfs struct
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*/
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@ -789,6 +820,13 @@ static struct mcidev_sysfs_attribute i7core_inj_attrs[] = {
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},
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.show = i7core_inject_enable_show,
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.store = i7core_inject_enable_store,
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}, {
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.attr = {
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.name = "corrected_error_counts",
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.mode = (S_IRUGO | S_IWUSR)
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},
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.show = i7core_ce_regs_show,
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.store = NULL,
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},
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};
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@ -879,13 +917,76 @@ static int i7core_get_devices(struct mem_ctl_info *mci, struct pci_dev *mcidev)
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return 0;
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}
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/****************************************************************************
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Error check routines
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****************************************************************************/
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/* This function is based on the device 3 function 4 registers as described on:
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* Intel Xeon Processor 5500 Series Datasheet Volume 2
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* http://www.intel.com/Assets/PDF/datasheet/321322.pdf
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* also available at:
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* http://www.arrownac.com/manufacturers/intel/s/nehalem/5500-datasheet-v2.pdf
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*/
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static void check_mc_test_err(struct mem_ctl_info *mci)
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{
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struct i7core_pvt *pvt = mci->pvt_info;
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u32 rcv1, rcv0;
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int new0, new1, new2;
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if (!pvt->pci_mcr[4]) {
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debugf0("%s MCR registers not found\n",__func__);
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return;
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}
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/* Corrected error reads */
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pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
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pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
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/* Store the new values */
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new2 = DIMM2_COR_ERR(rcv1);
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new1 = DIMM1_COR_ERR(rcv0);
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new0 = DIMM0_COR_ERR(rcv0);
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debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
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(pvt->ce_count_available ? "UPDATE" : "READ"),
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rcv1, rcv0, new0, new1, new2);
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/* Updates CE counters if it is not the first time here */
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if (pvt->ce_count_available) {
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/* Updates CE counters */
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int add0, add1, add2;
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add2 = new2 - pvt->last_ce_count[2];
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add1 = new1 - pvt->last_ce_count[1];
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add0 = new0 - pvt->last_ce_count[0];
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if (add2 < 0)
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add2 += 0x7fff;
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pvt->ce_count[2] += add2;
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if (add1 < 0)
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add1 += 0x7fff;
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pvt->ce_count[1] += add1;
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if (add0 < 0)
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add0 += 0x7fff;
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pvt->ce_count[0] += add0;
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} else
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pvt->ce_count_available = 1;
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/* Store the new values */
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pvt->last_ce_count[2] = new2;
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pvt->last_ce_count[1] = new1;
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pvt->last_ce_count[0] = new0;
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}
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/*
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* i7core_check_error Retrieve and process errors reported by the
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* hardware. Called by the Core module.
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*/
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static void i7core_check_error(struct mem_ctl_info *mci)
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{
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/* FIXME: need a real code here */
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check_mc_test_err(mci);
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}
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/*
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