PWN-Hunter/android_kernel_xiaomi_sdm845
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ARM: Merge fixes-s3c64xx

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Merge branch 'fixes-s3c64xx' into fixes-s3c-2632-rc5
This commit is contained in:
Ben Dooks 2009-10-28 18:34:23 +00:00
commit 8e8821e5bb
2 changed files with 5 additions and 2 deletions
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4
arch/arm/plat-s3c64xx/include/plat/regs-clock.h
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@ -51,8 +51,8 @@
#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
#define S3C6400_CLKDIV0_ARM_MASK (0x3 << 0)
#define S3C6410_CLKDIV0_ARM_MASK (0x7 << 0)
#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
#define S3C6400_CLKDIV0_ARM_SHIFT (0)
/* CLKDIV1 */

3
arch/arm/plat-s3c64xx/s3c6400-clock.c
View File

@ -677,6 +677,9 @@ void __init_or_cpufreq s3c6400_setup_clocks(void)
printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
/* For now assume the mux always selects the crystal */
clk_ext_xtal_mux.parent = xtal_clk;
epll = s3c6400_get_epll(xtal);
mpll = s3c6400_get_pll(xtal, __raw_readl(S3C_MPLL_CON));
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));