PWN-Hunter/android_kernel_xiaomi_sdm845
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V4L/DVB (11804): xc5000: poll at 5ms interval for register write command completion

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Instead of polling at 100ms intervals for register writes, poll at 5ms
intervals.  This is consistent with the xc5000 specification, and improves
tuning time by up to 500 ms on devices that such as the au0828 which do not
properly implement i2c clock stretching (since the five register writes that
occur for a tuning request often do not complete immediately but do complete
far before 100ms has gone by).

The net amount of time we wait before timing out is unchanged (500ms).

Signed-off-by: Devin Heitmueller <dheitmueller@kernellabs.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Devin Heitmueller 2009-05-04 23:29:17 -03:00 committed by Mauro Carvalho Chehab
parent 6c99080d8e
commit a37791c540
1 changed files with 2 additions and 2 deletions
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4
drivers/media/common/tuners/xc5000.c
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@ -262,7 +262,7 @@ static int xc5000_TunerReset(struct dvb_frontend *fe)
static int xc_write_reg(struct xc5000_priv *priv, u16 regAddr, u16 i2cData)
{
u8 buf[4];
int WatchDogTimer = 5;
int WatchDogTimer = 100;
int result;
buf[0] = (regAddr >> 8) & 0xFF;
@ -284,7 +284,7 @@ static int xc_write_reg(struct xc5000_priv *priv, u16 regAddr, u16 i2cData)
/* busy flag cleared */
break;
} else {
xc_wait(100); /* wait 5 ms */
xc_wait(5); /* wait 5 ms */
WatchDogTimer--;
}
}