drm/radeon: Fix setting of bits
Duplicate bits set Signed-off-by: Roel Kluin <roel.kluin@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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df748b025d
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@ -411,7 +411,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb);
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R300_P2G2CLK_DAC_ALWAYS_ONb);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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} else if (rdev->family >= CHIP_RV350) {
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} else if (rdev->family >= CHIP_RV350) {
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tmp = RREG32_PLL(R300_SCLK_CNTL2);
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tmp = RREG32_PLL(R300_SCLK_CNTL2);
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@ -464,7 +464,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb);
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R300_P2G2CLK_DAC_ALWAYS_ONb);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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tmp = RREG32_PLL(RADEON_MCLK_MISC);
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tmp = RREG32_PLL(RADEON_MCLK_MISC);
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@ -654,7 +654,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_DAC_ALWAYS_ONb |
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R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
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R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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} else if (rdev->family >= CHIP_RV350) {
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} else if (rdev->family >= CHIP_RV350) {
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@ -705,7 +705,7 @@ void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable)
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TRANS_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_PIXCLK_TVO_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_ALWAYS_ONb |
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R300_P2G2CLK_DAC_ALWAYS_ONb |
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R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
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R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
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} else {
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} else {
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@ -881,7 +881,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
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R420_TV_DAC_DACADJ_MASK |
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R420_TV_DAC_DACADJ_MASK |
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R420_TV_DAC_RDACPD |
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R420_TV_DAC_RDACPD |
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R420_TV_DAC_GDACPD |
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R420_TV_DAC_GDACPD |
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R420_TV_DAC_GDACPD |
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R420_TV_DAC_BDACPD |
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R420_TV_DAC_TVENABLE);
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R420_TV_DAC_TVENABLE);
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} else {
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} else {
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tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
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tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
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@ -889,7 +889,7 @@ static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
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RADEON_TV_DAC_DACADJ_MASK |
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RADEON_TV_DAC_DACADJ_MASK |
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RADEON_TV_DAC_RDACPD |
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RADEON_TV_DAC_RDACPD |
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RADEON_TV_DAC_GDACPD |
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RADEON_TV_DAC_GDACPD |
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RADEON_TV_DAC_GDACPD);
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RADEON_TV_DAC_BDACPD);
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}
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}
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/* FIXME TV */
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/* FIXME TV */
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