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V4L/DVB (12222): gspca - stv06xx-hdcs: Fix sensor sequence bug

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All hdcs registers use bit 0 as a read/write flag and needs to be shifted one bit to the left. This wasn't accounted for when doing a sequence of writes.

Signed-off-by: Erik Andrén <erik.andren@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
This commit is contained in:
Erik Andrén 2009-06-24 04:30:56 -03:00 committed by Mauro Carvalho Chehab
parent 36a516d953
commit ac51295ccc
1 changed files with 5 additions and 3 deletions
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8
drivers/media/video/gspca/stv06xx/stv06xx_hdcs.c
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@ -131,9 +131,11 @@ static int hdcs_reg_write_seq(struct sd *sd, u8 reg, u8 *vals, u8 len)
(reg + len > 0xff)))
return -EINVAL;
for (i = 0; i < len; i++, reg++) {
regs[2*i] = reg;
regs[2*i+1] = vals[i];
for (i = 0; i < len; i++) {
regs[2 * i] = reg;
regs[2 * i + 1] = vals[i];
/* All addresses are shifted left one bit as bit 0 toggles r/w */
reg += 2;
}
return stv06xx_write_sensor_bytes(sd, regs, len);