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@ -111,7 +111,7 @@ MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold");
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#define FALCON_RX_FLUSH_COUNT 4
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#define FALCON_IS_DUAL_FUNC(efx) \
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(falcon_rev(efx) < FALCON_REV_B0)
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(efx_nic_rev(efx) < EFX_REV_FALCON_B0)
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/**************************************************************************
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*
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@ -447,7 +447,7 @@ void falcon_init_tx(struct efx_tx_queue *tx_queue)
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FRF_AZ_TX_DESCQ_TYPE, 0,
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FRF_BZ_TX_NON_IP_DROP_DIS, 1);
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if (falcon_rev(efx) >= FALCON_REV_B0) {
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM;
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EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum);
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EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS,
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@ -457,7 +457,7 @@ void falcon_init_tx(struct efx_tx_queue *tx_queue)
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efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base,
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tx_queue->queue);
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if (falcon_rev(efx) < FALCON_REV_B0) {
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if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
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efx_oword_t reg;
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/* Only 128 bits in this register */
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@ -574,7 +574,7 @@ void falcon_init_rx(struct efx_rx_queue *rx_queue)
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{
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efx_oword_t rx_desc_ptr;
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struct efx_nic *efx = rx_queue->efx;
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bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0;
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bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0;
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bool iscsi_digest_en = is_b0;
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EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n",
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@ -752,7 +752,7 @@ static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue,
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FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR);
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rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR);
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rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC);
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rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ?
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rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ?
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0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB));
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rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR);
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@ -897,13 +897,13 @@ static void falcon_handle_global_event(struct efx_channel *channel,
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handled = true;
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}
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if ((falcon_rev(efx) >= FALCON_REV_B0) &&
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if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) &&
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EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) {
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efx->xmac_poll_required = true;
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handled = true;
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}
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if (falcon_rev(efx) <= FALCON_REV_A1 ?
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if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ?
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EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) :
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EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) {
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EFX_ERR(efx, "channel %d seen global RX_RESET "
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@ -1531,7 +1531,7 @@ static void falcon_setup_rss_indir_table(struct efx_nic *efx)
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unsigned long offset;
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efx_dword_t dword;
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if (falcon_rev(efx) < FALCON_REV_B0)
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if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
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return;
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for (offset = FR_BZ_RX_INDIRECTION_TBL;
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@ -1554,7 +1554,7 @@ int falcon_init_interrupt(struct efx_nic *efx)
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if (!EFX_INT_MODE_USE_MSI(efx)) {
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irq_handler_t handler;
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if (falcon_rev(efx) >= FALCON_REV_B0)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
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handler = falcon_legacy_interrupt_b0;
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else
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handler = falcon_legacy_interrupt_a1;
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@ -1601,7 +1601,7 @@ void falcon_fini_interrupt(struct efx_nic *efx)
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}
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/* ACK legacy interrupt */
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if (falcon_rev(efx) >= FALCON_REV_B0)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
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efx_reado(efx, ®, FR_BZ_INT_ISR0);
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else
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falcon_irq_ack_a1(efx);
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@ -1841,7 +1841,7 @@ static int falcon_reset_macs(struct efx_nic *efx)
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efx_oword_t reg;
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int count;
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if (falcon_rev(efx) < FALCON_REV_B0) {
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if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
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/* It's not safe to use GLB_CTL_REG to reset the
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* macs, so instead use the internal MAC resets
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*/
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@ -1917,7 +1917,7 @@ void falcon_drain_tx_fifo(struct efx_nic *efx)
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{
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efx_oword_t reg;
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if ((falcon_rev(efx) < FALCON_REV_B0) ||
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if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
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(efx->loopback_mode != LOOPBACK_NONE))
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return;
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@ -1933,7 +1933,7 @@ void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
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{
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efx_oword_t reg;
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if (falcon_rev(efx) < FALCON_REV_B0)
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if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
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return;
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/* Isolate the MAC -> RX */
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@ -1970,7 +1970,7 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
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FRF_AB_MAC_SPEED, link_speed);
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/* On B0, MAC backpressure can be disabled and packets get
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* discarded. */
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if (falcon_rev(efx) >= FALCON_REV_B0) {
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
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!link_state->up);
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}
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@ -1988,7 +1988,7 @@ void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
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EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc);
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/* Unisolate the MAC -> RX */
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if (falcon_rev(efx) >= FALCON_REV_B0)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
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EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
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efx_writeo(efx, ®, FR_AZ_RX_CFG);
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}
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@ -2207,7 +2207,7 @@ static void falcon_clock_mac(struct efx_nic *efx)
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/* Configure the NIC generated MAC clock correctly */
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efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
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strap_val = EFX_IS10G(efx) ? 5 : 3;
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if (falcon_rev(efx) >= FALCON_REV_B0) {
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1);
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EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val);
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efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT);
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@ -2296,7 +2296,7 @@ int falcon_probe_port(struct efx_nic *efx)
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efx->link_state.fd = true;
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/* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
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if (falcon_rev(efx) >= FALCON_REV_B0)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
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efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
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else
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efx->wanted_fc = EFX_FC_RX;
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@ -2806,13 +2806,13 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
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efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
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switch (falcon_rev(efx)) {
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case FALCON_REV_A0:
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case 0xff:
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EFX_ERR(efx, "Falcon rev A0 not supported\n");
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return -ENODEV;
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if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
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u8 pci_rev = efx->pci_dev->revision;
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case FALCON_REV_A1:
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if ((pci_rev == 0xff) || (pci_rev == 0)) {
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EFX_ERR(efx, "Falcon rev A0 not supported\n");
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return -ENODEV;
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}
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if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
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EFX_ERR(efx, "Falcon rev A1 1G not supported\n");
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return -ENODEV;
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@ -2821,14 +2821,6 @@ static int falcon_probe_nic_variant(struct efx_nic *efx)
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EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n");
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return -ENODEV;
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}
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break;
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case FALCON_REV_B0:
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break;
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default:
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EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx));
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return -ENODEV;
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}
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return 0;
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@ -2991,7 +2983,7 @@ static void falcon_init_rx_cfg(struct efx_nic *efx)
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efx_oword_t reg;
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efx_reado(efx, ®, FR_AZ_RX_CFG);
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if (falcon_rev(efx) <= FALCON_REV_A1) {
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if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
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/* Data FIFO size is 5.5K */
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if (data_xon_thr < 0)
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data_xon_thr = 512 >> 8;
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@ -3037,7 +3029,7 @@ int falcon_init_nic(struct efx_nic *efx)
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efx_writeo(efx, &temp, FR_AB_NIC_STAT);
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/* Set the source of the GMAC clock */
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if (falcon_rev(efx) == FALCON_REV_B0) {
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if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) {
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efx_reado(efx, &temp, FR_AB_GPIO_CTL);
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EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true);
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efx_writeo(efx, &temp, FR_AB_GPIO_CTL);
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@ -3128,7 +3120,7 @@ int falcon_init_nic(struct efx_nic *efx)
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/* Prefetch threshold 2 => fetch when descriptor cache half empty */
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EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2);
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/* Squash TX of packets of 16 bytes or less */
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if (falcon_rev(efx) >= FALCON_REV_B0)
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
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EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1);
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efx_writeo(efx, &temp, FR_AZ_TX_RESERVED);
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@ -3142,7 +3134,7 @@ int falcon_init_nic(struct efx_nic *efx)
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falcon_init_rx_cfg(efx);
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/* Set destination of both TX and RX Flush events */
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if (falcon_rev(efx) >= FALCON_REV_B0) {
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if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
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EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
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efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
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}
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@ -3242,9 +3234,10 @@ void falcon_stop_nic_stats(struct efx_nic *efx)
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**************************************************************************
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*/
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struct efx_nic_type falcon_a_nic_type = {
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struct efx_nic_type falcon_a1_nic_type = {
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.default_mac_ops = &falcon_xmac_operations,
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.revision = EFX_REV_FALCON_A1,
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.mem_map_size = 0x20000,
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.txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
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.rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
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@ -3257,9 +3250,10 @@ struct efx_nic_type falcon_a_nic_type = {
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.phys_addr_channels = 4,
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};
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struct efx_nic_type falcon_b_nic_type = {
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struct efx_nic_type falcon_b0_nic_type = {
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.default_mac_ops = &falcon_xmac_operations,
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.revision = EFX_REV_FALCON_B0,
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/* Map everything up to and including the RSS indirection
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* table. Don't map MSI-X table, MSI-X PBA since Linux
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* requires that they not be mapped. */
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