PWN-Hunter/android_kernel_xiaomi_sdm845
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ath9k: Fix bug in checking HT flag

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The operating HT mode is stored in chanmode and
not channelFlags.

Cc: stable@kernel.org
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Sujith 2009-04-13 21:56:41 +05:30 committed by John W. Linville
parent 822b0dfc13
commit db2f63f60a
1 changed files with 1 additions and 1 deletions
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2
drivers/net/wireless/ath/ath9k/calib.c
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@ -883,7 +883,7 @@ bool ath9k_hw_calibrate(struct ath_hw *ah, struct ath9k_channel *chan,
static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan) static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
{ {
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
if (chan->channelFlags & CHANNEL_HT20) { if (IS_CHAN_HT20(chan)) {
REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,