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usb: phy: mxs: add delay before set phyctrl.clkgate

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There is a request from IC engineer that if we doesn't
set phypwd as 0xffffffff, we need to delay about five
32Khz cycles before set phy's pwd register, otherwise,
the wakeup signal may can't wake up controller.

Signed-off-by: Peter Chen <peter.chen@freescale.com>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Peter Chen 2015-01-16 18:29:01 +08:00 committed by Felipe Balbi
parent efdbd3a5d6
commit e235f7b86f
1 changed files with 9 additions and 3 deletions
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12
drivers/usb/phy/phy-mxs-usb.c
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@ -371,10 +371,16 @@ static int mxs_phy_suspend(struct usb_phy *x, int suspend)
* connect. The low speed connection will have problem at
* very rare cases during usb suspend and resume process.
*/
if (low_speed_connection & vbus_is_on)
writel(0xfffbffff, x->io_priv + HW_USBPHY_PWD);
else
if (low_speed_connection & vbus_is_on) {
/*
* If value to be set as pwd value is not 0xffffffff,
* several 32Khz cycles are needed.
*/
mxs_phy_clock_switch_delay();
writel(0xffbfffff, x->io_priv + HW_USBPHY_PWD);
} else {
writel(0xffffffff, x->io_priv + HW_USBPHY_PWD);
}
writel(BM_USBPHY_CTRL_CLKGATE,
x->io_priv + HW_USBPHY_CTRL_SET);
clk_disable_unprepare(mxs_phy->clk);