sh: Add support for SH7706/SH7710/SH7343 CPUs.
This adds support for the aforementioned CPU subtypes, and cleans up some build issues encountered as a result. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
parent
ecd9561687
commit
e5723e0eeb
@ -324,12 +324,11 @@ config SH_FPU_EMU
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config SH_DSP
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bool "DSP support"
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depends on !CPU_SH4
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default y
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default y if SH4AL_DSP || !CPU_SH4
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default n
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help
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Selecting this option will enable support for SH processors that
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have DSP units (ie, SH2-DSP and SH3-DSP). It is safe to say Y here
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by default, as the existance of the DSP will be probed at runtime.
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have DSP units (ie, SH2-DSP, SH3-DSP, and SH4AL-DSP).
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This option must be set in order to enable the DSP.
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@ -393,8 +392,9 @@ config SH_PCLK_FREQ
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int "Peripheral clock frequency (in Hz)"
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default "50000000" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7780
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default "60000000" if CPU_SUBTYPE_SH7751
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default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || CPU_SUBTYPE_SH7760
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default "27000000" if CPU_SUBTYPE_SH73180
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default "33333333" if CPU_SUBTYPE_SH7300 || CPU_SUBTYPE_SH7770 || \
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CPU_SUBTYPE_SH7760
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default "27000000" if CPU_SUBTYPE_SH73180 || CPU_SUBTYPE_SH7343
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default "66000000" if CPU_SUBTYPE_SH4_202
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help
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This option is used to specify the peripheral clock frequency.
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@ -18,11 +18,13 @@ cflags-y := -mb
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cflags-$(CONFIG_CPU_LITTLE_ENDIAN) := -ml
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isa-y := any
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isa-$(CONFIG_SH_DSP) := sh
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isa-$(CONFIG_CPU_SH2) := sh2
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isa-$(CONFIG_CPU_SH2A) := sh2a
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isa-$(CONFIG_CPU_SH3) := sh3
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isa-$(CONFIG_CPU_SH4) := sh4
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isa-$(CONFIG_CPU_SH4A) := sh4a
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isa-$(CONFIG_CPU_SH2A) := sh2a
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isa-$(CONFIG_CPU_SH4AL_DSP) := sh4al
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isa-$(CONFIG_SH_DSP) := $(isa-y)-dsp
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@ -30,9 +32,11 @@ ifndef CONFIG_MMU
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isa-y := $(isa-y)-nommu
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endif
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ifndef CONFIG_SH_DSP
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ifndef CONFIG_SH_FPU
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isa-y := $(isa-y)-nofpu
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endif
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endif
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cflags-y += $(call as-option,-Wa$(comma)-isa=$(isa-y),)
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@ -188,4 +192,3 @@ CLEAN_FILES += include/asm-sh/machtypes.h
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define archhelp
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@echo ' zImage - Compressed kernel image (arch/sh/boot/zImage)'
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endef
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@ -8,10 +8,11 @@
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*
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* Setup code for an HP680 (internal peripherials only)
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*/
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#include <linux/types.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#include <asm/hd64461.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/hp6xx/hp6xx.h>
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#include <asm/cpu/dac.h>
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@ -10,10 +10,10 @@
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* placeholder code from io_hs7751rvoip.c left in with the
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* expectation of later SuperIO and PCMCIA access.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <asm/hs7751rvoip/hs7751rvoip.h>
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#include <asm/addrspace.h>
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@ -89,6 +89,7 @@ static void mask_and_ack_ipr(unsigned int irq)
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disable_ipr_irq(irq);
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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/* This is needed when we use edge triggered setting */
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/* XXX: Is it really needed? */
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@ -162,6 +163,7 @@ void __init init_IRQ(void)
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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/*
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* Initialize the Interrupt Controller (INTC)
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@ -6,16 +6,19 @@ obj-y := ex.o probe.o
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# CPU subtype setup
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obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh7709.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh7709.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh7708.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh7709.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7300) += setup-sh7300.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
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# Primary on-chip clocks (common)
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clock-$(CONFIG_CPU_SH3) := clock-sh3.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7300) := clock-sh7300.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7705) := clock-sh7705.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7706) := clock-sh7706.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7709) := clock-sh7709.o
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clock-$(CONFIG_CPU_SUBTYPE_SH7710) := clock-sh7300.o
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obj-y += $(clock-y)
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84
arch/sh/kernel/cpu/sh3/clock-sh7706.c
Normal file
84
arch/sh/kernel/cpu/sh3/clock-sh7706.c
Normal file
@ -0,0 +1,84 @@
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/*
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* arch/sh/kernel/cpu/sh3/clock-sh7706.c
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*
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* SH7706 support for the clock framework
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*
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* Copyright (C) 2006 Takashi YOSHII
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*
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* Based on arch/sh/kernel/cpu/sh3/clock-sh7709.c
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* Copyright (C) 2005 Andriy Skulysh
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/freq.h>
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#include <asm/io.h>
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static int stc_multipliers[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
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static int ifc_divisors[] = { 1, 2, 4, 1, 3, 1, 1, 1 };
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static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
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static void master_clk_init(struct clk *clk)
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{
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int frqcr = ctrl_inw(FRQCR);
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int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
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clk->rate *= pfc_divisors[idx];
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}
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static struct clk_ops sh7706_master_clk_ops = {
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.init = master_clk_init,
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};
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static void module_clk_recalc(struct clk *clk)
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{
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int frqcr = ctrl_inw(FRQCR);
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int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
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clk->rate = clk->parent->rate / pfc_divisors[idx];
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}
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static struct clk_ops sh7706_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static void bus_clk_recalc(struct clk *clk)
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{
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int frqcr = ctrl_inw(FRQCR);
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int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
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clk->rate = clk->parent->rate / stc_multipliers[idx];
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}
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static struct clk_ops sh7706_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static void cpu_clk_recalc(struct clk *clk)
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{
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int frqcr = ctrl_inw(FRQCR);
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int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
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clk->rate = clk->parent->rate / ifc_divisors[idx];
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}
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static struct clk_ops sh7706_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct clk_ops *sh7706_clk_ops[] = {
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&sh7706_master_clk_ops,
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&sh7706_module_clk_ops,
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&sh7706_bus_clk_ops,
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&sh7706_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
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{
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if (idx < ARRAY_SIZE(sh7706_clk_ops))
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*ops = sh7706_clk_ops[idx];
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}
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@ -84,8 +84,12 @@ ENTRY(interrupt_table)
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.long do_IRQ ! rovi
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.long do_IRQ
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.long do_IRQ /* 5E0 */
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
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#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
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defined(CONFIG_CPU_SUBTYPE_SH7709) || \
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defined(CONFIG_CPU_SUBTYPE_SH7706) || \
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defined(CONFIG_CPU_SUBTYPE_SH7300) || \
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defined(CONFIG_CPU_SUBTYPE_SH7705) || \
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defined(CONFIG_CPU_SUBTYPE_SH7710)
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.long do_IRQ ! 32 IRQ irq0 /* 600 */
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.long do_IRQ ! 33 irq1
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.long do_IRQ ! 34 irq2
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@ -147,6 +151,51 @@ ENTRY(interrupt_table)
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.long do_IRQ ! 62 PCC pcc0i
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.long do_IRQ ! 63 pcc1i /* 9E0 */
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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.long exception_none ! 61 /* 9A0 */
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.long exception_none ! 62
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.long exception_none ! 63
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.long exception_none ! 64 /* A00 */
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.long exception_none ! 65
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.long exception_none ! 66
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.long exception_none ! 67
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.long exception_none ! 68
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.long exception_none ! 69
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.long exception_none ! 70
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.long exception_none ! 71
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.long exception_none ! 72 /* B00 */
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.long exception_none ! 73
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.long exception_none ! 74
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.long exception_none ! 75
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.long do_IRQ ! 76 DMAC2 dei4 /* B80 */
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.long do_IRQ ! 77 DMAC2 dei5
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.long exception_none ! 78
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.long do_IRQ ! 79 IPSEC ipseci /* BE0 */
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.long do_IRQ ! 80 EDMAC eint0 /* C00 */
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.long do_IRQ ! 81 EDMAC eint1
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.long do_IRQ ! 82 EDMAC eint2
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.long exception_none ! 83 /* C60 */
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.long exception_none ! 84
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.long exception_none ! 85
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.long exception_none ! 86
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.long exception_none ! 87
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.long exception_none ! 88 /* D00 */
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.long exception_none ! 89
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.long exception_none ! 90
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.long exception_none ! 91
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.long exception_none ! 92
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.long exception_none ! 93
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.long exception_none ! 94
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.long exception_none ! 95
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.long do_IRQ ! 96 SIOF eri0 /* E00 */
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.long do_IRQ ! 97 txi0
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.long do_IRQ ! 98 rxi0
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.long do_IRQ ! 99 cci0
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.long do_IRQ ! 100 eri1 /* E80 */
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.long do_IRQ ! 101 txi1
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.long do_IRQ ! 102 rxi2
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.long do_IRQ ! 103 cci3
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7300)
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.long do_IRQ ! 64
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.long do_IRQ ! 65
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@ -195,4 +244,3 @@ ENTRY(interrupt_table)
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.long do_IRQ ! 108
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#endif
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#endif
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@ -72,6 +72,12 @@ int __init detect_cpu_and_cache_system(void)
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cpu_data->dcache.sets = 256;
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cpu_data->type = CPU_SH7729;
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#if defined(CONFIG_CPU_SUBTYPE_SH7706)
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cpu_data->type = CPU_SH7706;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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cpu_data->type = CPU_SH7710;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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cpu_data->type = CPU_SH7705;
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43
arch/sh/kernel/cpu/sh3/setup-sh7710.c
Normal file
43
arch/sh/kernel/cpu/sh3/setup-sh7710.c
Normal file
@ -0,0 +1,43 @@
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/*
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* SH7710 Setup
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*
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* Copyright (C) 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xa4400000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55, 54 },
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}, {
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.flags = 0,
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}
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};
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static struct platform_device sci_device = {
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.name = "sh-sci",
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.id = -1,
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.dev = {
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.platform_data = sci_platform_data,
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},
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};
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static struct platform_device *sh7710_devices[] __initdata = {
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&sci_device,
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};
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static int __init sh7710_devices_setup(void)
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{
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return platform_add_devices(sh7710_devices,
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ARRAY_SIZE(sh7710_devices));
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}
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__initcall(sh7710_devices_setup);
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@ -14,6 +14,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7760) += setup-sh7760.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
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obj-$(CONFIG_CPU_SUBTYPE_SH73180) += setup-sh73180.o
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obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
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obj-$(CONFIG_CPU_SUBTYPE_SH4_202) += setup-sh4-202.o
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# Primary on-chip clocks (common)
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@ -123,6 +123,13 @@ ENTRY(interrupt_table)
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.long do_IRQ ! 45 dmte5
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.long do_IRQ ! 46 dmte6
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.long do_IRQ ! 47 dmte7 /* 7E0 */
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
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.long do_IRQ ! 44 IIC1 ali /* 780 */
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.long do_IRQ ! 45 tacki
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.long do_IRQ ! 46 waiti
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.long do_IRQ ! 47 dtei /* 7E0 */
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.long do_IRQ ! 48 DMAC dei0 /* 800 */
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.long do_IRQ ! 49 dei1 /* 820 */
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#else
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.long exception_error ! 44 /* 780 */
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.long exception_error ! 45
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@ -132,7 +139,8 @@ ENTRY(interrupt_table)
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#if defined(CONFIG_SH_FPU)
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.long do_fpu_state_restore ! 48 /* 800 */
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.long do_fpu_state_restore ! 49 /* 820 */
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#else
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#elif !defined(CONFIG_CPU_SUBTYPE_SH7343) && \
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!defined(CONFIG_CPU_SUBTYPE_SH73180)
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.long exception_error
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.long exception_error
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#endif
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@ -225,7 +233,7 @@ ENTRY(interrupt_table)
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.long exception_error
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.long do_IRQ ! ADC adi
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.long do_IRQ ! CMT cmti /* FA0 */
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#elif defined(CONFIG_CPU_SUBTYPE_SH73180)
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#elif defined(CONFIG_CPU_SUBTYPE_SH73180) || defined(CONFIG_CPU_SUBTYPE_SH7343)
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.long do_IRQ ! 50 0x840
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.long do_IRQ ! 51 0x860
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.long do_IRQ ! 52 0x880
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@ -3,7 +3,7 @@
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*
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* CPU Subtype Probing for SH-4.
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*
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* Copyright (C) 2001 - 2005 Paul Mundt
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* Copyright (C) 2001 - 2006 Paul Mundt
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* Copyright (C) 2003 Richard Curnow
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*
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* This file is subject to the terms and conditions of the GNU General Public
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@ -76,12 +76,6 @@ int __init detect_cpu_and_cache_system(void)
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cpu_data->type = CPU_SH73180;
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cpu_data->icache.ways = 4;
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cpu_data->dcache.ways = 4;
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/*
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* XXX: Double check this, none of the SH-4A/SH-4AL processors
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* should have this, as it's essentially a legacy thing.
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*/
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cpu_data->flags |= CPU_HAS_PTEA;
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break;
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case 0x2001:
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case 0x2004:
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@ -89,8 +83,7 @@ int __init detect_cpu_and_cache_system(void)
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cpu_data->icache.ways = 4;
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cpu_data->dcache.ways = 4;
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/* Same note as above applies here for PTEA */
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cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
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cpu_data->flags |= CPU_HAS_FPU;
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break;
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case 0x2006:
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case 0x200A:
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@ -104,6 +97,12 @@ int __init detect_cpu_and_cache_system(void)
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cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER;
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break;
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case 0x3000:
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case 0x3003:
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cpu_data->type = CPU_SH7343;
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cpu_data->icache.ways = 4;
|
||||
cpu_data->dcache.ways = 4;
|
||||
break;
|
||||
case 0x8000:
|
||||
cpu_data->type = CPU_ST40RA;
|
||||
cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PTEA;
|
||||
|
43
arch/sh/kernel/cpu/sh4/setup-sh7343.c
Normal file
43
arch/sh/kernel/cpu/sh4/setup-sh7343.c
Normal file
@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SH7343 Setup
|
||||
*
|
||||
* Copyright (C) 2006 Paul Mundt
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file "COPYING" in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/serial.h>
|
||||
#include <asm/sci.h>
|
||||
|
||||
static struct plat_sci_port sci_platform_data[] = {
|
||||
{
|
||||
.mapbase = 0xffe00000,
|
||||
.flags = UPF_BOOT_AUTOCONF,
|
||||
.type = PORT_SCIF,
|
||||
.irqs = { 80, 81, 83, 82 },
|
||||
}, {
|
||||
.flags = 0,
|
||||
}
|
||||
};
|
||||
|
||||
static struct platform_device sci_device = {
|
||||
.name = "sh-sci",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = sci_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *sh7343_devices[] __initdata = {
|
||||
&sci_device,
|
||||
};
|
||||
|
||||
static int __init sh7343_devices_setup(void)
|
||||
{
|
||||
return platform_add_devices(sh7343_devices,
|
||||
ARRAY_SIZE(sh7343_devices));
|
||||
}
|
||||
__initcall(sh7343_devices_setup);
|
@ -310,7 +310,7 @@ ubc_set_tracing(int asid, unsigned long pc)
|
||||
|
||||
ctrl_outl(0, UBC_BAMRA);
|
||||
|
||||
if (cpu_data->type == CPU_SH7729) {
|
||||
if (cpu_data->type == CPU_SH7729 || cpu_data->type == CPU_SH7710) {
|
||||
ctrl_outw(BBR_INST | BBR_READ | BBR_CPU, UBC_BBRA);
|
||||
ctrl_outl(BRCR_PCBA | BRCR_PCTE, UBC_BRCR);
|
||||
} else {
|
||||
|
@ -424,25 +424,18 @@ static int __init topology_init(void)
|
||||
subsys_initcall(topology_init);
|
||||
|
||||
static const char *cpu_name[] = {
|
||||
[CPU_SH7604] = "SH7604",
|
||||
[CPU_SH7705] = "SH7705",
|
||||
[CPU_SH7708] = "SH7708",
|
||||
[CPU_SH7729] = "SH7729",
|
||||
[CPU_SH7300] = "SH7300",
|
||||
[CPU_SH7750] = "SH7750",
|
||||
[CPU_SH7750S] = "SH7750S",
|
||||
[CPU_SH7750R] = "SH7750R",
|
||||
[CPU_SH7751] = "SH7751",
|
||||
[CPU_SH7751R] = "SH7751R",
|
||||
[CPU_SH7760] = "SH7760",
|
||||
[CPU_SH73180] = "SH73180",
|
||||
[CPU_ST40RA] = "ST40RA",
|
||||
[CPU_ST40GX1] = "ST40GX1",
|
||||
[CPU_SH4_202] = "SH4-202",
|
||||
[CPU_SH4_501] = "SH4-501",
|
||||
[CPU_SH7770] = "SH7770",
|
||||
[CPU_SH7780] = "SH7780",
|
||||
[CPU_SH7781] = "SH7781",
|
||||
[CPU_SH7604] = "SH7604", [CPU_SH7300] = "SH7300",
|
||||
[CPU_SH7705] = "SH7705", [CPU_SH7706] = "SH7706",
|
||||
[CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
|
||||
[CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
|
||||
[CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
|
||||
[CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
|
||||
[CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
|
||||
[CPU_SH7760] = "SH7760", [CPU_SH73180] = "SH73180",
|
||||
[CPU_ST40RA] = "ST40RA", [CPU_ST40GX1] = "ST40GX1",
|
||||
[CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
|
||||
[CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
|
||||
[CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
|
||||
[CPU_SH_NONE] = "Unknown"
|
||||
};
|
||||
|
||||
|
@ -89,7 +89,8 @@ EXPORT_SYMBOL(flush_dcache_page);
|
||||
EXPORT_SYMBOL(__flush_purge_region);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMU
|
||||
#if defined(CONFIG_MMU) && (defined(CONFIG_CPU_SH4) || \
|
||||
defined(CONFIG_SH7705_CACHE_32KB))
|
||||
EXPORT_SYMBOL(clear_user_page);
|
||||
#endif
|
||||
|
||||
|
@ -21,6 +21,10 @@ config CPU_SH4A
|
||||
bool
|
||||
select CPU_SH4
|
||||
|
||||
config CPU_SH4AL_DSP
|
||||
bool
|
||||
select CPU_SH4A
|
||||
|
||||
config CPU_SUBTYPE_ST40
|
||||
bool
|
||||
select CPU_SH4
|
||||
@ -47,6 +51,12 @@ config CPU_SUBTYPE_SH7705
|
||||
select CPU_SH3
|
||||
select CPU_HAS_PINT_IRQ
|
||||
|
||||
config CPU_SUBTYPE_SH7706
|
||||
bool "Support SH7706 processor"
|
||||
select CPU_SH3
|
||||
help
|
||||
Select SH7706 if you have a 133 Mhz SH-3 HD6417706 CPU.
|
||||
|
||||
config CPU_SUBTYPE_SH7707
|
||||
bool "Support SH7707 processor"
|
||||
select CPU_SH3
|
||||
@ -68,6 +78,12 @@ config CPU_SUBTYPE_SH7709
|
||||
help
|
||||
Select SH7709 if you have a 80 Mhz SH-3 HD6417709 CPU.
|
||||
|
||||
config CPU_SUBTYPE_SH7710
|
||||
bool "Support SH7710 processor"
|
||||
select CPU_SH3
|
||||
help
|
||||
Select SH7710 if you have a SH3-DSP SH7710 CPU.
|
||||
|
||||
comment "SH-4 Processor Support"
|
||||
|
||||
config CPU_SUBTYPE_SH7750
|
||||
@ -132,10 +148,6 @@ config CPU_SUBTYPE_ST40GX1
|
||||
|
||||
comment "SH-4A Processor Support"
|
||||
|
||||
config CPU_SUBTYPE_SH73180
|
||||
bool "Support SH73180 processor"
|
||||
select CPU_SH4A
|
||||
|
||||
config CPU_SUBTYPE_SH7770
|
||||
bool "Support SH7770 processor"
|
||||
select CPU_SH4A
|
||||
@ -145,6 +157,16 @@ config CPU_SUBTYPE_SH7780
|
||||
select CPU_SH4A
|
||||
select CPU_HAS_INTC2_IRQ
|
||||
|
||||
comment "SH4AL-DSP Processor Support"
|
||||
|
||||
config CPU_SUBTYPE_SH73180
|
||||
bool "Support SH73180 processor"
|
||||
select CPU_SH4AL_DSP
|
||||
|
||||
config CPU_SUBTYPE_SH7343
|
||||
bool "Support SH7343 processor"
|
||||
select CPU_SH4AL_DSP
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Memory management options"
|
||||
|
@ -26,12 +26,10 @@
|
||||
#define CCR_CACHE_ENABLE CCR_CACHE_CE
|
||||
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define CCR3 0xa40000b4
|
||||
#define CCR_CACHE_16KB 0x00010000
|
||||
#define CCR_CACHE_32KB 0x00020000
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __ASM_CPU_SH3_CACHE_H */
|
||||
|
||||
|
@ -27,8 +27,12 @@
|
||||
#define TRA 0xffffffd0
|
||||
#define EXPEVT 0xffffffd4
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
|
||||
#else
|
||||
#define INTEVT 0xffffffd8
|
||||
|
@ -20,6 +20,7 @@
|
||||
* SH7710
|
||||
* SH7720
|
||||
* SH7300
|
||||
* SH7710
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
@ -11,6 +11,19 @@
|
||||
#ifndef __ASM_CPU_SH3_UBC_H
|
||||
#define __ASM_CPU_SH3_UBC_H
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define UBC_BARA 0xa4ffffb0
|
||||
#define UBC_BAMRA 0xa4ffffb4
|
||||
#define UBC_BBRA 0xa4ffffb8
|
||||
#define UBC_BASRA 0xffffffe4
|
||||
#define UBC_BARB 0xa4ffffa0
|
||||
#define UBC_BAMRB 0xa4ffffa4
|
||||
#define UBC_BBRB 0xa4ffffa8
|
||||
#define UBC_BASRB 0xffffffe8
|
||||
#define UBC_BDRB 0xa4ffff90
|
||||
#define UBC_BDMRB 0xa4ffff94
|
||||
#define UBC_BRCR 0xa4ffff98
|
||||
#else
|
||||
#define UBC_BARA 0xffffffb0
|
||||
#define UBC_BAMRA 0xffffffb4
|
||||
#define UBC_BBRA 0xffffffb8
|
||||
@ -22,6 +35,6 @@
|
||||
#define UBC_BDRB 0xffffff90
|
||||
#define UBC_BDMRB 0xffffff94
|
||||
#define UBC_BRCR 0xffffff98
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_CPU_SH3_UBC_H */
|
||||
|
||||
|
@ -311,6 +311,4 @@
|
||||
#define IRQ6_PRIORITY 1
|
||||
#define IRQ7_PRIORITY 1
|
||||
|
||||
int shmse_irq_demux(int irq);
|
||||
|
||||
#endif /* __ASM_SH_IRQ_SH73180_H */
|
||||
|
317
include/asm-sh/irq-sh7343.h
Normal file
317
include/asm-sh/irq-sh7343.h
Normal file
@ -0,0 +1,317 @@
|
||||
#ifndef __ASM_SH_IRQ_SH7343_H
|
||||
#define __ASM_SH_IRQ_SH7343_H
|
||||
|
||||
/*
|
||||
* linux/include/asm-sh/irq-sh7343.h
|
||||
*
|
||||
* Copyright (C) 2006 Kenati Technologies Inc.
|
||||
* Andre Mccurdy <andre@kenati.com>
|
||||
* Ranjit Deshpande <ranjit@kenati.com>
|
||||
*/
|
||||
|
||||
#undef INTC_IPRA
|
||||
#undef INTC_IPRB
|
||||
#undef INTC_IPRC
|
||||
#undef INTC_IPRD
|
||||
|
||||
#undef DMTE0_IRQ
|
||||
#undef DMTE1_IRQ
|
||||
#undef DMTE2_IRQ
|
||||
#undef DMTE3_IRQ
|
||||
#undef DMTE4_IRQ
|
||||
#undef DMTE5_IRQ
|
||||
#undef DMTE6_IRQ
|
||||
#undef DMTE7_IRQ
|
||||
#undef DMAE_IRQ
|
||||
#undef DMA_IPR_ADDR
|
||||
#undef DMA_IPR_POS
|
||||
#undef DMA_PRIORITY
|
||||
|
||||
#undef INTC_IMCR0
|
||||
#undef INTC_IMCR1
|
||||
#undef INTC_IMCR2
|
||||
#undef INTC_IMCR3
|
||||
#undef INTC_IMCR4
|
||||
#undef INTC_IMCR5
|
||||
#undef INTC_IMCR6
|
||||
#undef INTC_IMCR7
|
||||
#undef INTC_IMCR8
|
||||
#undef INTC_IMCR9
|
||||
#undef INTC_IMCR10
|
||||
|
||||
|
||||
#define INTC_IPRA 0xA4080000UL
|
||||
#define INTC_IPRB 0xA4080004UL
|
||||
#define INTC_IPRC 0xA4080008UL
|
||||
#define INTC_IPRD 0xA408000CUL
|
||||
#define INTC_IPRE 0xA4080010UL
|
||||
#define INTC_IPRF 0xA4080014UL
|
||||
#define INTC_IPRG 0xA4080018UL
|
||||
#define INTC_IPRH 0xA408001CUL
|
||||
#define INTC_IPRI 0xA4080020UL
|
||||
#define INTC_IPRJ 0xA4080024UL
|
||||
#define INTC_IPRK 0xA4080028UL
|
||||
#define INTC_IPRL 0xA408002CUL
|
||||
|
||||
#define INTC_IMR0 0xA4080080UL
|
||||
#define INTC_IMR1 0xA4080084UL
|
||||
#define INTC_IMR2 0xA4080088UL
|
||||
#define INTC_IMR3 0xA408008CUL
|
||||
#define INTC_IMR4 0xA4080090UL
|
||||
#define INTC_IMR5 0xA4080094UL
|
||||
#define INTC_IMR6 0xA4080098UL
|
||||
#define INTC_IMR7 0xA408009CUL
|
||||
#define INTC_IMR8 0xA40800A0UL
|
||||
#define INTC_IMR9 0xA40800A4UL
|
||||
#define INTC_IMR10 0xA40800A8UL
|
||||
#define INTC_IMR11 0xA40800ACUL
|
||||
|
||||
#define INTC_IMCR0 0xA40800C0UL
|
||||
#define INTC_IMCR1 0xA40800C4UL
|
||||
#define INTC_IMCR2 0xA40800C8UL
|
||||
#define INTC_IMCR3 0xA40800CCUL
|
||||
#define INTC_IMCR4 0xA40800D0UL
|
||||
#define INTC_IMCR5 0xA40800D4UL
|
||||
#define INTC_IMCR6 0xA40800D8UL
|
||||
#define INTC_IMCR7 0xA40800DCUL
|
||||
#define INTC_IMCR8 0xA40800E0UL
|
||||
#define INTC_IMCR9 0xA40800E4UL
|
||||
#define INTC_IMCR10 0xA40800E8UL
|
||||
#define INTC_IMCR11 0xA40800ECUL
|
||||
|
||||
#define INTC_ICR0 0xA4140000UL
|
||||
#define INTC_ICR1 0xA414001CUL
|
||||
|
||||
#define INTMSK0 0xa4140044
|
||||
#define INTMSKCLR0 0xa4140064
|
||||
#define INTC_INTPRI0 0xa4140010
|
||||
|
||||
/*
|
||||
NOTE:
|
||||
|
||||
*_IRQ = (INTEVT2 - 0x200)/0x20
|
||||
*/
|
||||
|
||||
/* TMU0 */
|
||||
#define TMU0_IRQ 16
|
||||
#define TMU0_IPR_ADDR INTC_IPRA
|
||||
#define TMU0_IPR_POS 3
|
||||
#define TMU0_PRIORITY 2
|
||||
|
||||
#define TIMER_IRQ 16
|
||||
#define TIMER_IPR_ADDR INTC_IPRA
|
||||
#define TIMER_IPR_POS 3
|
||||
#define TIMER_PRIORITY 2
|
||||
|
||||
/* TMU1 */
|
||||
#define TMU1_IRQ 17
|
||||
#define TMU1_IPR_ADDR INTC_IPRA
|
||||
#define TMU1_IPR_POS 2
|
||||
#define TMU1_PRIORITY 2
|
||||
|
||||
/* TMU2 */
|
||||
#define TMU2_IRQ 18
|
||||
#define TMU2_IPR_ADDR INTC_IPRA
|
||||
#define TMU2_IPR_POS 1
|
||||
#define TMU2_PRIORITY 2
|
||||
|
||||
/* LCDC */
|
||||
#define LCDC_IRQ 28
|
||||
#define LCDC_IPR_ADDR INTC_IPRB
|
||||
#define LCDC_IPR_POS 2
|
||||
#define LCDC_PRIORITY 2
|
||||
|
||||
/* VIO (Video I/O) */
|
||||
#define CEU_IRQ 52
|
||||
#define BEU_IRQ 53
|
||||
#define VEU_IRQ 54
|
||||
#define VOU_IRQ 55
|
||||
#define VIO_IPR_ADDR INTC_IPRE
|
||||
#define VIO_IPR_POS 2
|
||||
#define VIO_PRIORITY 2
|
||||
|
||||
/* MFI (Multi Functional Interface) */
|
||||
#define MFI_IRQ 56
|
||||
#define MFI_IPR_ADDR INTC_IPRE
|
||||
#define MFI_IPR_POS 1
|
||||
#define MFI_PRIORITY 2
|
||||
|
||||
/* VPU (Video Processing Unit) */
|
||||
#define VPU_IRQ 60
|
||||
#define VPU_IPR_ADDR INTC_IPRE
|
||||
#define VPU_IPR_POS 0
|
||||
#define VPU_PRIORITY 2
|
||||
|
||||
/* 3DG */
|
||||
#define TDG_IRQ 63
|
||||
#define TDG_IPR_ADDR INTC_IPRJ
|
||||
#define TDG_IPR_POS 2
|
||||
#define TDG_PRIORITY 2
|
||||
|
||||
/* DMAC(1) */
|
||||
#define DMTE0_IRQ 48
|
||||
#define DMTE1_IRQ 49
|
||||
#define DMTE2_IRQ 50
|
||||
#define DMTE3_IRQ 51
|
||||
#define DMA1_IPR_ADDR INTC_IPRE
|
||||
#define DMA1_IPR_POS 3
|
||||
#define DMA1_PRIORITY 7
|
||||
|
||||
/* DMAC(2) */
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#define DMA2_IPR_ADDR INTC_IPRF
|
||||
#define DMA2_IPR_POS 2
|
||||
#define DMA2_PRIORITY 7
|
||||
|
||||
/* SCIF0 */
|
||||
#define SCIF_ERI_IRQ 80
|
||||
#define SCIF_RXI_IRQ 81
|
||||
#define SCIF_BRI_IRQ 82
|
||||
#define SCIF_TXI_IRQ 83
|
||||
#define SCIF_IPR_ADDR INTC_IPRG
|
||||
#define SCIF_IPR_POS 3
|
||||
#define SCIF_PRIORITY 3
|
||||
|
||||
/* SIOF0 */
|
||||
#define SIOF0_IRQ 84
|
||||
#define SIOF0_IPR_ADDR INTC_IPRH
|
||||
#define SIOF0_IPR_POS 3
|
||||
#define SIOF0_PRIORITY 3
|
||||
|
||||
/* FLCTL (Flash Memory Controller) */
|
||||
#define FLSTE_IRQ 92
|
||||
#define FLTEND_IRQ 93
|
||||
#define FLTRQ0_IRQ 94
|
||||
#define FLTRQ1_IRQ 95
|
||||
#define FLCTL_IPR_ADDR INTC_IPRH
|
||||
#define FLCTL_IPR_POS 1
|
||||
#define FLCTL_PRIORITY 3
|
||||
|
||||
/* IIC(0) (IIC Bus Interface) */
|
||||
#define IIC0_ALI_IRQ 96
|
||||
#define IIC0_TACKI_IRQ 97
|
||||
#define IIC0_WAITI_IRQ 98
|
||||
#define IIC0_DTEI_IRQ 99
|
||||
#define IIC0_IPR_ADDR INTC_IPRH
|
||||
#define IIC0_IPR_POS 0
|
||||
#define IIC0_PRIORITY 3
|
||||
|
||||
/* IIC(1) (IIC Bus Interface) */
|
||||
#define IIC1_ALI_IRQ 44
|
||||
#define IIC1_TACKI_IRQ 45
|
||||
#define IIC1_WAITI_IRQ 46
|
||||
#define IIC1_DTEI_IRQ 47
|
||||
#define IIC1_IPR_ADDR INTC_IPRI
|
||||
#define IIC1_IPR_POS 0
|
||||
#define IIC1_PRIORITY 3
|
||||
|
||||
/* SIO0 */
|
||||
#define SIO0_IRQ 88
|
||||
#define SIO0_IPR_ADDR INTC_IPRI
|
||||
#define SIO0_IPR_POS 3
|
||||
#define SIO0_PRIORITY 3
|
||||
|
||||
/* SDHI */
|
||||
#define SDHI_SDHII0_IRQ 100
|
||||
#define SDHI_SDHII1_IRQ 101
|
||||
#define SDHI_SDHII2_IRQ 102
|
||||
#define SDHI_SDHII3_IRQ 103
|
||||
#define SDHI_IPR_ADDR INTC_IPRK
|
||||
#define SDHI_IPR_POS 0
|
||||
#define SDHI_PRIORITY 3
|
||||
|
||||
/* SIU (Sound Interface Unit) */
|
||||
#define SIU_IRQ 108
|
||||
#define SIU_IPR_ADDR INTC_IPRJ
|
||||
#define SIU_IPR_POS 1
|
||||
#define SIU_PRIORITY 3
|
||||
|
||||
#define PORT_PACR 0xA4050100UL
|
||||
#define PORT_PBCR 0xA4050102UL
|
||||
#define PORT_PCCR 0xA4050104UL
|
||||
#define PORT_PDCR 0xA4050106UL
|
||||
#define PORT_PECR 0xA4050108UL
|
||||
#define PORT_PFCR 0xA405010AUL
|
||||
#define PORT_PGCR 0xA405010CUL
|
||||
#define PORT_PHCR 0xA405010EUL
|
||||
#define PORT_PJCR 0xA4050110UL
|
||||
#define PORT_PKCR 0xA4050112UL
|
||||
#define PORT_PLCR 0xA4050114UL
|
||||
#define PORT_SCPCR 0xA4050116UL
|
||||
#define PORT_PMCR 0xA4050118UL
|
||||
#define PORT_PNCR 0xA405011AUL
|
||||
#define PORT_PQCR 0xA405011CUL
|
||||
#define PORT_PRCR 0xA405011EUL
|
||||
#define PORT_PTCR 0xA405014CUL
|
||||
#define PORT_PUCR 0xA405014EUL
|
||||
#define PORT_PVCR 0xA4050150UL
|
||||
|
||||
#define PORT_PSELA 0xA4050140UL
|
||||
#define PORT_PSELB 0xA4050142UL
|
||||
#define PORT_PSELC 0xA4050144UL
|
||||
#define PORT_PSELE 0xA4050158UL
|
||||
|
||||
#define PORT_HIZCRA 0xA4050146UL
|
||||
#define PORT_HIZCRB 0xA4050148UL
|
||||
#define PORT_DRVCR 0xA405014AUL
|
||||
|
||||
#define PORT_PADR 0xA4050120UL
|
||||
#define PORT_PBDR 0xA4050122UL
|
||||
#define PORT_PCDR 0xA4050124UL
|
||||
#define PORT_PDDR 0xA4050126UL
|
||||
#define PORT_PEDR 0xA4050128UL
|
||||
#define PORT_PFDR 0xA405012AUL
|
||||
#define PORT_PGDR 0xA405012CUL
|
||||
#define PORT_PHDR 0xA405012EUL
|
||||
#define PORT_PJDR 0xA4050130UL
|
||||
#define PORT_PKDR 0xA4050132UL
|
||||
#define PORT_PLDR 0xA4050134UL
|
||||
#define PORT_SCPDR 0xA4050136UL
|
||||
#define PORT_PMDR 0xA4050138UL
|
||||
#define PORT_PNDR 0xA405013AUL
|
||||
#define PORT_PQDR 0xA405013CUL
|
||||
#define PORT_PRDR 0xA405013EUL
|
||||
#define PORT_PTDR 0xA405016CUL
|
||||
#define PORT_PUDR 0xA405016EUL
|
||||
#define PORT_PVDR 0xA4050170UL
|
||||
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
#define IRQ2_IRQ 34
|
||||
#define IRQ3_IRQ 35
|
||||
#define IRQ4_IRQ 36
|
||||
#define IRQ5_IRQ 37
|
||||
#define IRQ6_IRQ 38
|
||||
#define IRQ7_IRQ 39
|
||||
|
||||
#define INTPRI00 0xA4140010UL
|
||||
|
||||
#define IRQ0_IPR_ADDR INTPRI00
|
||||
#define IRQ1_IPR_ADDR INTPRI00
|
||||
#define IRQ2_IPR_ADDR INTPRI00
|
||||
#define IRQ3_IPR_ADDR INTPRI00
|
||||
#define IRQ4_IPR_ADDR INTPRI00
|
||||
#define IRQ5_IPR_ADDR INTPRI00
|
||||
#define IRQ6_IPR_ADDR INTPRI00
|
||||
#define IRQ7_IPR_ADDR INTPRI00
|
||||
|
||||
#define IRQ0_IPR_POS 7
|
||||
#define IRQ1_IPR_POS 6
|
||||
#define IRQ2_IPR_POS 5
|
||||
#define IRQ3_IPR_POS 4
|
||||
#define IRQ4_IPR_POS 3
|
||||
#define IRQ5_IPR_POS 2
|
||||
#define IRQ6_IPR_POS 1
|
||||
#define IRQ7_IPR_POS 0
|
||||
|
||||
#define IRQ0_PRIORITY 1
|
||||
#define IRQ1_PRIORITY 1
|
||||
#define IRQ2_PRIORITY 1
|
||||
#define IRQ3_PRIORITY 1
|
||||
#define IRQ4_PRIORITY 1
|
||||
#define IRQ5_PRIORITY 1
|
||||
#define IRQ6_PRIORITY 1
|
||||
#define IRQ7_PRIORITY 1
|
||||
|
||||
#endif /* __ASM_SH_IRQ_SH7343_H */
|
@ -192,7 +192,7 @@
|
||||
|
||||
#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \
|
||||
defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \
|
||||
defined (CONFIG_CPU_SUBTYPE_SH7751)
|
||||
defined (CONFIG_CPU_SUBTYPE_SH7751) || defined (CONFIG_CPU_SUBTYPE_SH7706)
|
||||
#define SCI_ERI_IRQ 23
|
||||
#define SCI_RXI_IRQ 24
|
||||
#define SCI_TXI_IRQ 25
|
||||
@ -207,6 +207,7 @@
|
||||
#define SCIF0_IPR_POS 3
|
||||
#define SCIF0_PRIORITY 3
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
#define SCIF_ERI_IRQ 56
|
||||
@ -261,9 +262,12 @@
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
|
||||
# define ONCHIP_NR_IRQS 32
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
# define ONCHIP_NR_IRQS 64 // Actually 61
|
||||
# define PINT_NR_IRQS 16
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
# define ONCHIP_NR_IRQS 104
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
|
||||
# define ONCHIP_NR_IRQS 48 // Actually 44
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
|
||||
@ -275,7 +279,8 @@
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
|
||||
# define ONCHIP_NR_IRQS 144
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH73180)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH73180) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7343)
|
||||
# define ONCHIP_NR_IRQS 109
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
|
||||
# define ONCHIP_NR_IRQS 111
|
||||
@ -476,8 +481,10 @@ extern int ipr_irq_demux(int irq);
|
||||
|
||||
#define INTC_ICR 0xfffffee0UL
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709)
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define INTC_IRR0 0xa4000004UL
|
||||
#define INTC_IRR1 0xa4000006UL
|
||||
#define INTC_IRR2 0xa4000008UL
|
||||
@ -496,8 +503,105 @@ extern int ipr_irq_demux(int irq);
|
||||
#define INTC_IPRF 0xa4080000UL
|
||||
#define INTC_IPRG 0xa4080002UL
|
||||
#define INTC_IPRH 0xa4080004UL
|
||||
#endif
|
||||
#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
/* Interrupt Controller Registers */
|
||||
#undef INTC_IPRA
|
||||
#undef INTC_IPRB
|
||||
#define INTC_IPRA 0xA414FEE2UL
|
||||
#define INTC_IPRB 0xA414FEE4UL
|
||||
#define INTC_IPRF 0xA4080000UL
|
||||
#define INTC_IPRG 0xA4080002UL
|
||||
#define INTC_IPRH 0xA4080004UL
|
||||
#define INTC_IPRI 0xA4080006UL
|
||||
|
||||
#undef INTC_ICR0
|
||||
#undef INTC_ICR1
|
||||
#define INTC_ICR0 0xA414FEE0UL
|
||||
#define INTC_ICR1 0xA4140010UL
|
||||
|
||||
#define INTC_IRR0 0xa4000004UL
|
||||
#define INTC_IRR1 0xa4000006UL
|
||||
#define INTC_IRR2 0xa4000008UL
|
||||
#define INTC_IRR3 0xa400000AUL
|
||||
#define INTC_IRR4 0xa400000CUL
|
||||
#define INTC_IRR5 0xa4080020UL
|
||||
#define INTC_IRR7 0xa4080024UL
|
||||
#define INTC_IRR8 0xa4080026UL
|
||||
|
||||
/* Interrupt numbers */
|
||||
#define TIMER2_IRQ 18
|
||||
#define TIMER2_IPR_ADDR INTC_IPRA
|
||||
#define TIMER2_IPR_POS 1
|
||||
#define TIMER2_PRIORITY 2
|
||||
|
||||
/* WDT */
|
||||
#define WDT_IRQ 27
|
||||
#define WDT_IPR_ADDR INTC_IPRB
|
||||
#define WDT_IPR_POS 3
|
||||
#define WDT_PRIORITY 2
|
||||
|
||||
#define SCIF0_ERI_IRQ 52
|
||||
#define SCIF0_RXI_IRQ 53
|
||||
#define SCIF0_BRI_IRQ 54
|
||||
#define SCIF0_TXI_IRQ 55
|
||||
#define SCIF0_IPR_ADDR INTC_IPRE
|
||||
#define SCIF0_IPR_POS 2
|
||||
#define SCIF0_PRIORITY 3
|
||||
|
||||
#define DMTE4_IRQ 76
|
||||
#define DMTE5_IRQ 77
|
||||
#define DMA2_IPR_ADDR INTC_IPRF
|
||||
#define DMA2_IPR_POS 2
|
||||
#define DMA2_PRIORITY 7
|
||||
|
||||
#define IPSEC_IRQ 79
|
||||
#define IPSEC_IPR_ADDR INTC_IPRF
|
||||
#define IPSEC_IPR_POS 3
|
||||
#define IPSEC_PRIORITY 3
|
||||
|
||||
/* EDMAC */
|
||||
#define EDMAC0_IRQ 80
|
||||
#define EDMAC0_IPR_ADDR INTC_IPRG
|
||||
#define EDMAC0_IPR_POS 3
|
||||
#define EDMAC0_PRIORITY 3
|
||||
|
||||
#define EDMAC1_IRQ 81
|
||||
#define EDMAC1_IPR_ADDR INTC_IPRG
|
||||
#define EDMAC1_IPR_POS 2
|
||||
#define EDMAC1_PRIORITY 3
|
||||
|
||||
#define EDMAC2_IRQ 82
|
||||
#define EDMAC2_IPR_ADDR INTC_IPRG
|
||||
#define EDMAC2_IPR_POS 1
|
||||
#define EDMAC2_PRIORITY 3
|
||||
|
||||
/* SIOF */
|
||||
#define SIOF0_ERI_IRQ 96
|
||||
#define SIOF0_TXI_IRQ 97
|
||||
#define SIOF0_RXI_IRQ 98
|
||||
#define SIOF0_CCI_IRQ 99
|
||||
#define SIOF0_IPR_ADDR INTC_IPRH
|
||||
#define SIOF0_IPR_POS 0
|
||||
#define SIOF0_PRIORITY 7
|
||||
|
||||
#define SIOF1_ERI_IRQ 100
|
||||
#define SIOF1_TXI_IRQ 101
|
||||
#define SIOF1_RXI_IRQ 102
|
||||
#define SIOF1_CCI_IRQ 103
|
||||
#define SIOF1_IPR_ADDR INTC_IPRI
|
||||
#define SIOF1_IPR_POS 1
|
||||
#define SIOF1_PRIORITY 7
|
||||
#endif /* CONFIG_CPU_SUBTYPE_SH7710 */
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7710)
|
||||
#define PORT_PACR 0xa4050100UL
|
||||
#define PORT_PBCR 0xa4050102UL
|
||||
#define PORT_PCCR 0xa4050104UL
|
||||
#define PORT_PETCR 0xa4050106UL
|
||||
#define PORT_PADR 0xa4050120UL
|
||||
#define PORT_PBDR 0xa4050122UL
|
||||
#define PORT_PCDR 0xa4050124UL
|
||||
#else
|
||||
#define PORT_PACR 0xa4000100UL
|
||||
#define PORT_PBCR 0xa4000102UL
|
||||
#define PORT_PCCR 0xa4000104UL
|
||||
@ -506,6 +610,7 @@ extern int ipr_irq_demux(int irq);
|
||||
#define PORT_PBDR 0xa4000122UL
|
||||
#define PORT_PCDR 0xa4000124UL
|
||||
#define PORT_PFDR 0xa400012aUL
|
||||
#endif
|
||||
|
||||
#define IRQ0_IRQ 32
|
||||
#define IRQ1_IRQ 33
|
||||
@ -599,6 +704,8 @@ void intc2_add_clear_irq(int irq, int (*fn)(int));
|
||||
|
||||
#endif
|
||||
|
||||
extern int shmse_irq_demux(int irq);
|
||||
|
||||
static inline int generic_irq_demux(int irq)
|
||||
{
|
||||
return irq;
|
||||
@ -614,4 +721,8 @@ static inline int generic_irq_demux(int irq)
|
||||
#include <asm/irq-sh73180.h>
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7343)
|
||||
#include <asm/irq-sh7343.h>
|
||||
#endif
|
||||
|
||||
#endif /* __ASM_SH_IRQ_H */
|
||||
|
@ -38,13 +38,15 @@ enum cpu_type {
|
||||
CPU_SH7604,
|
||||
|
||||
/* SH-3 types */
|
||||
CPU_SH7705, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
|
||||
CPU_SH7709, CPU_SH7709A, CPU_SH7729, CPU_SH7300,
|
||||
CPU_SH7705, CPU_SH7706, CPU_SH7707,
|
||||
CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
|
||||
CPU_SH7709, CPU_SH7709A, CPU_SH7710,
|
||||
CPU_SH7729, CPU_SH7300,
|
||||
|
||||
/* SH-4 types */
|
||||
CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
|
||||
CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501,
|
||||
CPU_SH73180, CPU_SH7770, CPU_SH7780, CPU_SH7781,
|
||||
CPU_SH73180, CPU_SH7343, CPU_SH7770, CPU_SH7780, CPU_SH7781,
|
||||
|
||||
/* Unknown subtype */
|
||||
CPU_SH_NONE
|
||||
|
Loading…
Reference in New Issue
Block a user