imx: reorder mx3x.h
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
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@ -34,21 +34,6 @@
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* C0000000 64M PCMCIA/CF
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* C0000000 64M PCMCIA/CF
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*/
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*/
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#define CS0_BASE_ADDR 0xA0000000
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#define CS1_BASE_ADDR 0xA8000000
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#define CS2_BASE_ADDR 0xB0000000
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#define CS3_BASE_ADDR 0xB2000000
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#define CS4_BASE_ADDR 0xB4000000
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#define CS4_BASE_ADDR_VIRT 0xF4000000
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#define CS4_SIZE SZ_32M
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#define CS5_BASE_ADDR 0xB6000000
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#define CS5_BASE_ADDR_VIRT 0xF6000000
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#define CS5_SIZE SZ_32M
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#define PCMCIA_MEM_BASE_ADDR 0xBC000000
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/*
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/*
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* L2CC
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* L2CC
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*/
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*/
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@ -101,6 +86,7 @@
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#define AIPS2_BASE_ADDR 0x53F00000
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#define AIPS2_BASE_ADDR 0x53F00000
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#define AIPS2_BASE_ADDR_VIRT 0xFC200000
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#define AIPS2_BASE_ADDR_VIRT 0xFC200000
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#define AIPS2_SIZE SZ_1M
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#define AIPS2_SIZE SZ_1M
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#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define CCM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
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#define GPT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
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#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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#define EPIT1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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@ -129,6 +115,27 @@
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#define AVIC_BASE_ADDR_VIRT 0xFC400000
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#define AVIC_BASE_ADDR_VIRT 0xFC400000
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#define AVIC_SIZE SZ_1M
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#define AVIC_SIZE SZ_1M
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/*
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* Memory regions and CS
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*/
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#define IPU_MEM_BASE_ADDR 0x70000000
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#define CSD0_BASE_ADDR 0x80000000
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#define CSD1_BASE_ADDR 0x90000000
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#define CS0_BASE_ADDR 0xA0000000
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#define CS1_BASE_ADDR 0xA8000000
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#define CS2_BASE_ADDR 0xB0000000
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#define CS3_BASE_ADDR 0xB2000000
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#define CS4_BASE_ADDR 0xB4000000
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#define CS4_BASE_ADDR_VIRT 0xF4000000
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#define CS4_SIZE SZ_32M
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#define CS5_BASE_ADDR 0xB6000000
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#define CS5_BASE_ADDR_VIRT 0xF6000000
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#define CS5_SIZE SZ_32M
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/*
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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*/
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@ -142,12 +149,7 @@
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#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
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#define EMI_CTL_BASE_ADDR (X_MEMC_BASE_ADDR + 0x4000)
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#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
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#define PCMCIA_CTL_BASE_ADDR EMI_CTL_BASE_ADDR
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/*
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#define PCMCIA_MEM_BASE_ADDR 0xBC000000
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* Memory regions and CS
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*/
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#define IPU_MEM_BASE_ADDR 0x70000000
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#define CSD0_BASE_ADDR 0x80000000
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#define CSD1_BASE_ADDR 0x90000000
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/*!
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/*!
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* This macro defines the physical to virtual address mapping for all the
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* This macro defines the physical to virtual address mapping for all the
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@ -272,4 +274,3 @@ static inline int mx31_revision(void)
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#endif
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#endif
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#endif /* __ASM_ARCH_MXC_MX31_H__ */
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#endif /* __ASM_ARCH_MXC_MX31_H__ */
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