Commit Graph

1729 Commits

Author SHA1 Message Date
Roel Kluin
c0f2a9d75a mips: undo locking on error path returns
[akpm@linux-foundation.org: coding-style cleanups]
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-14 18:45:42 -08:00
Ralf Baechle
74521c28e5 Use i8253.c lock for PC speaker on MIPS, too.
The Jazz machines have to use the PIT timer for dyntick and highresolution
kernels.  This may break because currently just like i386 used to do MIPS
uses two separate spinlocks in the actual PIT code and the PC speaker
code.  So switch to do it the same that x86 currently does PIT locking.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-02 19:39:18 -07:00
Thomas Bogendoerfer
3be51f70e1 [MIPS] Jazz: disable PIT; cleanup R4030 clockevent
Fix ISA irq acknowledge.
Make r4030 clockevent code look like other mips clockevent code.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
651194f820 [MIPS] Bigsur supports highmem.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
9603a23d3b [MIPS] mtx-1: Enable -Werror.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
e7c9d6b927 [MIPS] mtx-1: Remove unused mtx1_sys_btn.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
ae11e3214b [MIPS] Pb1200: Enable -Werror.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Thomas Bogendoerfer
c9294022af [MIPS] SNI: register a02r clockevent; don't use PIT timer
Register A20R clockevent.
Remove PIT timer setup because it doesn't work

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
dd3db6eb0e [MIPS] i8253: Cleanup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
db0c19e1a6 [MIPS] Pb1200: Fix warning.
arch/mips/au1000/pb1200/irqmap.c:101: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result

And while at it a few coding style cleanups.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
f5cd9f14e2 [MIPS] Pb1200: Fix warning.
arch/mips/au1000/pb1200/board_setup.c:71: warning: unused variable 'pin_func'

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
c8925297e8 [MIPS] IP27: Fix build error.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
07f6169cff [MIPS] Excite: Fix build error.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
217dd11e9d [MIPS] Sibyte: Split and move clock code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
f3f9ad0edc [MIPS] Sibyte: Fixes for oneshot timer mode.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
faf2782bf3 [MIPS] Sibyte: Remove blank line.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Thiemo Seufer
211a29a87c [MIPS] Swarm: Fix build failure
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Atsushi Nemoto
d9eec1a5d6 [MIPS] time: Code cleanups
* Do not include unnecessary headers.
* Do not mention time.README.
* Do not mention mips_timer_ack.
* Make clocksource_mips static.  It is now dedicated to c0_timer.
* Initialize clocksource_mips.read statically.
* Remove null_hpt_read.
* Remove an argument of plat_timer_setup.  It is just a placeholder.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
1d0a909cfc [MIPS] time: Remove now unused local_timer_interrupt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
81b635ef36 [MIPS] IP32: Fix address of 2nd serial interface.
Found by Giuseppe Sacco <giuseppe@eppesuigoccas.homedns.org>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
46abf4b39a [MIPS] SB1250: Use the right irqaction for the timer interrupt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
d1598b6adb [MIPS] SB1250: Remove stray assignment of cpumask.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
2e5dcd2b4c [MIPS] Sibyte: Fix names of the clockevent devices.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
9e32a510af [MIPS] Sibyte: Build fixes / dead code removal.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
1a3b7920fe [MIPS] tb0219: Update copyright message.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
Ralf Baechle
a76ab5c10d [MIPS] MT: Fix bug in multithreaded kernels.
When GDB writes a breakpoint into address area of inferior process the
kernel needs to invalidate the modified memory in the inferior which
is done by calling flush_cache_page which in turns calls
r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC
kernel via r4k_on_each_cpu().

As the VSMP and SMTC SMP kernels for 34K are running on a single shared
caches it is possible to get away without interprocessor function calls.
This optimization is implemented in r4k_on_each_cpu, so
local_r4k_flush_cache_page is only ever called on the local CPU.

This is where the following code in local_r4k_flush_cache_page() strikes:

        /*
         * If ownes no valid ASID yet, cannot possibly have gotten
         * this page into the cache.
         */
        if (cpu_context(smp_processor_id(), mm) == 0)
                return;

On VSMP and SMTC had a function of cpu_context() for each CPU(TC).

So in case another CPU than the CPU executing local_r4k_cache_flush_page
has not accessed the mm but one of the other CPUs has there may be data
to be flushed in the cache yet local_r4k_cache_flush_page will falsely
return leaving the I-cache inconsistent for the breakpoint.

While the issue was discovered with GDB it also exists in
local_r4k_flush_cache_range() and local_r4k_flush_cache().

Fixed by introducing a new function has_valid_asid which on MT kernels
returns true if a mm is active on any processor in the system.

This is relativly expensive since for memory acccesses in that loop
cache misses have to be assumed but it seems the most viable solution
for 2.6.23 and older -stable kernels.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
Ralf Baechle
a370605594 [MIPS] Alchemy: Remove CONFIG_TS_AU1X00_ADS7846 from defconfigs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
Ralf Baechle
1553f6a2ca Author: Ralf Baechle <ralf@linux-mips.org>
[MIPS] MSP71xx: Fix bitrot.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
Maciej W. Rozycki
d9ba26a93a [MIPS] sb1250: Enable GenBus IDE in defconfig.
Enable the onboard GenBus IDE interface in the default configuration.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
Franck Bui-Huu
16be243589 [MIPS] vmlinux.ld.S: correctly indent .data section
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:37 +00:00
Maciej W. Rozycki
21b2aecaae [MIPS] c-r3k: Implement flush_cache_range()
Contrary to the belief of some, the R3000 and related processors did have
caches, both a data and an instruction cache.  Here is an implementation
of r3k_flush_cache_page(), which is the processor-specific back-end for
flush_cache_range(), done according to the spec in
Documentation/cachetlb.txt.

While at it, remove an unused local function: get_phys_page(), do some
trivial formatting fixes and modernise debugging facilities.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Atsushi Nemoto
62b14c24b1 [MIPS] Store sign-extend register values for PTRACE_GETREGS
A comment on ptrace_getregs() states "Registers are sign extended to
fill the available space." but it is not true.  Fix code to match the
comment.  Also fix casts on each caller to get rid of some warnings.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Florian Fainelli
26c288f82c [MIPS] Alchemy: Register platform devices
This patch separates the platform devices registration for the MTX-1
specific devices: GPIO leds and watchdog.

[Minor fixup and formatting change -- Ralf]

Signed-off-by: Florian Fainelli <florian.fainelli@telecomint.eu>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
David Daney
098362e720 [MIPS] Add len and addr validation for MAP_FIXED mappings.
Mmap with MAP_FIXED was not validating the addr and len parameters.  This
leads to the failure of GCC's gcc.c-torture/execute/loop-2[fg].c testcases
when using the o32 ABI on a 64 bit kernel.

These testcases try to mmap 65536 bytes at 0x7fff8000 and then access all
the memory.  In 2.6.18 and 2.6.23.1 (and likely other versions as well)
the kernel maps the requested memory, but since half of it is above
0x80000000 a SIGBUS is generated when it is accessed.

This patch moves the len validation above the MAP_FIXED processing so that
it is always validated.  It also adds validation to the addr parameter for
MAP_FIXED mappings.

Signed-off-by: David Daney  <ddaney@avtrex.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Ralf Baechle
c4e8308c30 [MIPS] IRIX: Fix off-by-one error in signal compat code.
Based on original patch by Roel Kluin <12o3l@tiscali.nl>.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Ralf Baechle
38760d40ca [MIPS] time: Replace plat_timer_setup with modern APIs.
plat_timer_setup is no longer getting called.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Ralf Baechle
1238d5d868 [MIPS] time: Fix cut'n'paste bug in Sibyte clockevent driver.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:36 +00:00
Atsushi Nemoto
3a6c43a787 [MIPS] time: Make c0_compare_int_usable faster
Try increasingly longer time periods starting of at 0x10 cycles.  This
should be fast on hardware and work nicely with emulators.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Atsushi Nemoto
c637fecb4f [MIPS] time: Fix cevt-r4k.c for 64-bit kernel
The expression "(long)(read_c0_count() - cnt)" can never be a negative
value on 64-bit kernel.  Cast to "int" before comparison.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Ralf Baechle
11ca25aa31 [MIPS] Sibyte: Delete {sb1250,bcm1480}_steal_irq().
They break the timer interrupt initialization and only seem to be a kludge
for initialization happening in the wrong order.  Further testing done by
Thiemo confirms the suspicion that the other invocations also seem to have
useless.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Atsushi Nemoto
229f773ef4 [MIPS] txx9tmr clockevent/clocksource driver
Convert jmr3927_clock_event_device to more generic
txx9tmr_clock_event_device which supports one-shot mode.  The
txx9tmr_clock_event_device can be used for TX49 too if the cp0 timer
interrupt was not available.

Convert jmr3927_hpt_read to txx9_clocksource driver which does not
depends jiffies anymore.  The txx9_clocksource itself can be used for
TX49, but normally TX49 uses higher precision clocksource_mips.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Yoichi Yuasa
22df3f53e3 [MIPS] Add mips_hpt_frequency check to mips_clockevent_init().
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Ralf Baechle
8a13ecd7b2 [MIPS] IP32: Fixes after interrupt renumbering.
And general untangling.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Ralf Baechle
725d7b36c3 [MIPS] IP27: Fix slice logic to work for arbitrary number of slices.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:35 +00:00
Ralf Baechle
84953b39f9 [MIPS] SNI: Convert a20r timer to clockevent device.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:34 +00:00
Ralf Baechle
e0511f7524 [MIPS] time: Merge eXcite plat_timer_setup into plat_time_init.
Fixme: At the time of this writing cevt-r4k.c doesn't yet know about how
to handle the alternate timer interrupt of the RM9000.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:34 +00:00
Ralf Baechle
ba5eac515f [MIPS] time: Merge lasat plat_timer_setup into plat_time_init.
Since the cp0 compare interrupt handler isn't initialized by the time
plat_time_init is called don't set IE_IRQ5 anymore, cevt-r4k.c will do
that a little later itself.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:34 +00:00
Ralf Baechle
da349bef97 [MIPS] time: Remove wrppmc's definition of plat_timer_setup.
The only thing it used to do is now done by cevt-r4k.c.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:34 +00:00
Ralf Baechle
656db5061d [MIPS] time: Cause platform definitions of plat_timer_setup to cause error.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:34 +00:00
Ralf Baechle
bc2f2a24d9 [MIPS] Alchemy: Convert from plat_timer_setup to plat_time_init.
The old plat_timer_setup hook is no longer getting called so the Alchemy
time initialization was getting skipped.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-10-29 19:35:33 +00:00