Commit Graph

1760 Commits

Author SHA1 Message Date
Ralf Baechle
e6a1bb725e [MIPS] Fix build.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-12-01 00:39:37 +00:00
Thomas Bogendoerfer
68576cf122 IP22ZILOG: fix lockup and sysrq
- fix lockup when switching from early console to real console
 - make sysrq reliable
 - fix panic, if sysrq is issued before console is opened

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Alan Cox <alan@lxorguk.ukuu.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-29 09:24:53 -08:00
Joe Perches
b1e3afa001 [MIPS] vpe: Add missing "space"
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:15 +00:00
Richard Knutsson
8142294dda [MIPS] Compliment va_start() with va_end().
Signed-off-by: Richard Knutsson <ricknu-0@student.ltu.se>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:15 +00:00
Thomas Bogendoerfer
5b3af8f19f [MIPS] IP22: Fix broken eeprom access by using __raw_readl/__raw_writel
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Thomas Bogendoerfer
68de480372 [MIPS] IP22: Fix broken EISA interrupt setup by switching to generic i8259
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
cce335ae47 [MIPS] 64-bit Sibyte kernels need DMA32.
Sibyte SOCs only have 32-bit PCI.  Due to the sparse use of the address
space only the first 1GB of memory is mapped at physical addresses
below 1GB.  If a system has more than 1GB of memory 32-bit DMA will
not be able to reach all of it.

For now this patch is good enough to keep Sibyte users happy but it seems
eventually something like swiotlb will be needed for Sibyte.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
940f6b48a1 [MIPS] Only build r4k clocksource for systems that work ok with it.
In particular as-is it's not suited for multicore and mutiprocessors
systems where there is on guarantee that the counter are synchronized
or running from the same clock at all.  This broke Sibyte and probably
others since the "[MIPS] Handle R4000/R4400 mfc0 from count register."
commit.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:14 +00:00
Ralf Baechle
5aa85c9fc4 [MIPS] Handle R4000/R4400 mfc0 from count register.
The R4000 and R4400 have an errata where if the cp0 count register is read
in the exact moment when it matches the compare register no interrupt will
be generated.

This bug may be triggered if the cp0 count register is being used as
clocksource and the compare interrupt as clockevent.  So a simple
workaround is to avoid using the compare for both facilities on the
affected CPUs.

This is different from the workaround suggested in the old errata documents;
at some opportunity probably the official version should be implemented
and tested.  Another thing to find out is which processor versions
exactly are affected.  I only have errata documents upto R4400 V3.0
available so for the moment the code treats all R4000 and R4400 as broken.

This is potencially a problem for some machines that have no other decent
clocksource available; this workaround will cause them to fall back to
another clocksource, worst case the "jiffies" source.
2007-11-26 17:26:14 +00:00
Ralf Baechle
98ce472181 [MIPS] IP32: More interrupt renumbering fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Ralf Baechle
526a677069 [MIPS] time: MIPSsim's plat_time_init doesn't need to be irq safe.
It's running early during the bootup process so interrupts are still off.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Ralf Baechle
aea6863944 [MIPS] time: Fix negated condition in cevt-r4k driver.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-26 17:26:13 +00:00
Ralf Baechle
72e510654c [MIPS] N32 needs to use the compat version of sys_nfsservctl.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:52 +00:00
Ralf Baechle
30e748a507 [MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.
This matters to any sort of device that is wired to one of the CPU
interrupt pins on an SMP system.  Typically the scenario is most easily
triggered with the count/compare timer interrupt where the same interrupt
number and thus irq_desc is used on each processor.

   CPU A			CPU B

   do_IRQ()
   generic_handle_irq()
   handle_level_irq()
   spin_lock(desc_lock)
   set IRQ_INPROGRESS
   spin_unlock(desc_lock)
				do_IRQ()
				generic_handle_irq()
				handle_level_irq()
				spin_lock(desc_lock)
				IRQ_INPROGRESS set => bail out
   spin_lock(desc_lock)
   clear IRQ_INPROGRESS
   spin_unlock(desc_lock)

In case of the cp0 compare interrupt this means the interrupt will be
acked and not handled or re-armed on CPU b, so there won't be any timer
interrupt until the count register wraps around.

With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just
working right on VSMP because the count registers are synchronized on
bootup so it takes something that disables interrupts for a long time on
one processor to trigger this one.

For scenarios where an interrupt is multicasted or broadcasted over several
CPUs the existing code was safe and the fix will break it.  There is no
way to know in the interrupt controller code because it is abstracted from
the platform code.  I think we do not have such a setup currently, so this
should be ok.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:52 +00:00
Ralf Baechle
f99f2cc936 [MIPS] Sibyte: Fix name of clocksource.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:51 +00:00
Maciej W. Rozycki
eae5fdc3e5 [MIPS] SNI: s/achknowledge/acknowledge/
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:51 +00:00
Maciej W. Rozycki
3247989ee8 [MIPS] Makefile: Fix canonical system names
The GNU `config.guess' uses "linux-gnu" as the canonical system name.
Fix the list of compiler prefixes checked to spell it correctly.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:51 +00:00
Nigel Stephens
7c3a622d9c [MIPS] vpe: handle halting TCs in an errata safe way.
Adds a JR.HB after halting a TC, to ensure that the TC has really halted.
only modifies the TCSTATUS register when the TC is safely halted.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:50 +00:00
Ralf Baechle
8dfa741f14 [MIPS] Sibyte: Stop timers before programming next even.
We have no guarantee by the generic time code that the timer is stopped
when the ->next_event method is called.  Modifying the Timer Initial Count
register while the timer is enabled has UNPREDICTABLE effect according to
the BCM1250/BCM1125/BCM1125H User Manual.  So stop the timer before
reprogramming.

This is a paranoia fix; no ill effects have been observed previously.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:50 +00:00
Ralf Baechle
622477533d [MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.
For the old minimum of a single tick a value of zero would be programmed
into the init value register which in the BCM1250/BCM1125/BCM1125H User
Manual in the Timer Special Cases section is documented to have
UNPREDICTABLE effect.

Observable sympthoms of this bug were hangs of several seconds on the
console during bootup and later if both dyntick and highres timer options
were activated.

In theory contiguous mode of the timers is also affected but in an act of
hopeless lack of realism I'll assume nobody will ever configure a KERNEL
for HZ > 500kHz but if so I leave that to evolution to sort out.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:50 +00:00
Yoichi Yuasa
89becf5c0d [MIPS] Lasat: Fix overlap of interrupt number ranges.
The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.

Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:50 +00:00
Thomas Bogendoerfer
fcee3faf83 [MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:50 +00:00
Ralf Baechle
f6771dbb27 [MIPS] Fix shadow register support.
Shadow register support would not possibly have worked on multicore
systems.  The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.

SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code.  So fix
the allocator by ditching it.  Move the remaining CPU probe bits into
the generic CPU probe.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Atsushi Nemoto
c6563e85f7 [MIPS] Fix typo in R3000 TRACE_IRQFLAGS code
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Ralf Baechle
33b75e5c51 [MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Roel Kluin
bb856c5b49 [MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz
iounmap if pci clock is over 33MHz.  Cosmetic because the iomap() in this
case is just a bit of address magic.

Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Ralf Baechle
a8401fa57f [MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:49 +00:00
Ralf Baechle
07a80e4924 [MIPS] Sibyte: pin timer interrupt to their cores.
Or strange things will happen.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:48 +00:00
Ralf Baechle
a57c228935 [MIPS] Qemu: Add early printk, your friend in a cold night.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:48 +00:00
Ralf Baechle
a8049c53cd [MIPS] Convert reference to mem_map to pfn_to_page().
This was crashing the combination of highmem and sparsemem.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:48 +00:00
Ralf Baechle
a754f70886 [MIPS] Sibyte: resurrect old cache hack.
The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack

    [MIPS] Hack for SB1 cache issues

    Removing flush_icache_page a while ago broke SB1 which was using an empty
    flush_data_cache_page function.  This glues things well enough so a more
    efficient but also more intrusive solution can be found later.

    Signed-Off-By: Thiemo Seufer <ths@networkno.de>
    Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

in the hope it was no longer needed.  As it turns it still is so resurrect
it until there is a better solution.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-15 23:21:48 +00:00
Roel Kluin
c0f2a9d75a mips: undo locking on error path returns
[akpm@linux-foundation.org: coding-style cleanups]
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-14 18:45:42 -08:00
Ralf Baechle
74521c28e5 Use i8253.c lock for PC speaker on MIPS, too.
The Jazz machines have to use the PIT timer for dyntick and highresolution
kernels.  This may break because currently just like i386 used to do MIPS
uses two separate spinlocks in the actual PIT code and the PC speaker
code.  So switch to do it the same that x86 currently does PIT locking.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-11-02 19:39:18 -07:00
Thomas Bogendoerfer
3be51f70e1 [MIPS] Jazz: disable PIT; cleanup R4030 clockevent
Fix ISA irq acknowledge.
Make r4030 clockevent code look like other mips clockevent code.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
651194f820 [MIPS] Bigsur supports highmem.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
9603a23d3b [MIPS] mtx-1: Enable -Werror.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
e7c9d6b927 [MIPS] mtx-1: Remove unused mtx1_sys_btn.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:49 +00:00
Ralf Baechle
ae11e3214b [MIPS] Pb1200: Enable -Werror.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Thomas Bogendoerfer
c9294022af [MIPS] SNI: register a02r clockevent; don't use PIT timer
Register A20R clockevent.
Remove PIT timer setup because it doesn't work

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
dd3db6eb0e [MIPS] i8253: Cleanup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
db0c19e1a6 [MIPS] Pb1200: Fix warning.
arch/mips/au1000/pb1200/irqmap.c:101: warning: ignoring return value of 'request_irq', declared with attribute warn_unused_result

And while at it a few coding style cleanups.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:48 +00:00
Ralf Baechle
f5cd9f14e2 [MIPS] Pb1200: Fix warning.
arch/mips/au1000/pb1200/board_setup.c:71: warning: unused variable 'pin_func'

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
c8925297e8 [MIPS] IP27: Fix build error.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
07f6169cff [MIPS] Excite: Fix build error.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
217dd11e9d [MIPS] Sibyte: Split and move clock code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
f3f9ad0edc [MIPS] Sibyte: Fixes for oneshot timer mode.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Ralf Baechle
faf2782bf3 [MIPS] Sibyte: Remove blank line.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Thiemo Seufer
211a29a87c [MIPS] Swarm: Fix build failure
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:47 +00:00
Atsushi Nemoto
d9eec1a5d6 [MIPS] time: Code cleanups
* Do not include unnecessary headers.
* Do not mention time.README.
* Do not mention mips_timer_ack.
* Make clocksource_mips static.  It is now dedicated to c0_timer.
* Initialize clocksource_mips.read statically.
* Remove null_hpt_read.
* Remove an argument of plat_timer_setup.  It is just a placeholder.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00
Ralf Baechle
1d0a909cfc [MIPS] time: Remove now unused local_timer_interrupt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2007-11-02 16:13:46 +00:00