Commit Graph

64 Commits

Author SHA1 Message Date
Martin Schwidefsky
0b59268285 [PATCH] remove unused ibcs2/PER_SVR4 in SET_PERSONALITY
The SET_PERSONALITY macro is always called with a second argument of 0.
Remove the ibcs argument and the various tests to set the PER_SVR4
personality.

Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
2008-10-16 15:40:05 +02:00
David Woodhouse
e758936e02 Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts:

	include/asm-x86/statfs.h
2008-10-13 17:13:56 +01:00
Linus Torvalds
7cc4e87f91 Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (236 commits)
  [ARM] 5300/1: fixup spitz reset during boot
  [ARM] 5295/1: make ZONE_DMA optional
  [ARM] 5239/1: Palm Zire 72 power management support
  [ARM] 5298/1: Drop desc_handle_irq()
  [ARM] 5297/1: [KS8695] Fix two compile-time warnings
  [ARM] 5296/1: [KS8695] Replace macro's with trailing underscores.
  [ARM] pxa: allow multi-machine PCMCIA builds
  [ARM] pxa: add preliminary CPUFREQ support for PXA3xx
  [ARM] pxa: add missing ACCR bit definitions to pxa3xx-regs.h
  [ARM] pxa: rename cpu-pxa.c to cpufreq-pxa2xx.c
  [ARM] pxa/zylonite: add support for USB OHCI
  [ARM] ohci-pxa27x: use ioremap() and offset for register access
  [ARM] ohci-pxa27x: introduce pxa27x_clear_otgph()
  [ARM] ohci-pxa27x: use platform_get_{irq,resource} for the resource
  [ARM] ohci-pxa27x: move OHCI controller specific registers into the driver
  [ARM] ohci-pxa27x: introduce flags to avoid direct access to OHCI registers
  [ARM] pxa: move I2S register and bit definitions into pxa2xx-i2s.c
  [ARM] pxa: simplify DMA register definitions
  [ARM] pxa: make additional DCSR bits valid for PXA3xx
  [ARM] pxa: move i2c register and bit definitions into i2c-pxa.c
  ...

Fixed up conflicts in
	arch/arm/mach-versatile/core.c
	sound/soc/pxa/pxa2xx-ac97.c
	sound/soc/pxa/pxa2xx-i2s.c
manually.
2008-10-11 10:09:45 -07:00
Russell King
c97f68145e Merge branch 'for-rmk' of git://source.mvista.com/git/linux-davinci-2.6.git
Merge branch 'davinci' into devel
2008-10-09 21:33:05 +01:00
Russell King
3f30a09a61 Merge branch 'pxa-all' into devel
Conflicts:

	arch/arm/mach-pxa/Kconfig
	arch/arm/mach-pxa/corgi.c
	arch/arm/mach-pxa/include/mach/hardware.h
	arch/arm/mach-pxa/spitz.c
2008-10-09 21:33:02 +01:00
Russell King
9e165acf1b Merge branch 'at91' into devel 2008-10-09 21:31:58 +01:00
Russell King
6a4690c22f Merge branch 'ptebits' into devel
Conflicts:

	arch/arm/Kconfig
2008-10-09 21:31:56 +01:00
Nicolas Pitre
3bca103a1e [ARM] 5295/1: make ZONE_DMA optional
Most ARM machines don't need a special "DMA" memory zone, and
when configured out, the kernel becomes a bit smaller:

|   text    data     bss     dec     hex filename
|3826182  102384  111700 4040266  3da64a vmlinux
|3823593  101616  111700 4036909  3d992d vmlinux.nodmazone

This is because the system now has only one zone total which effect is
to optimize away many conditionals in page allocation paths.

So let's configure this zone only on machines that need split zones.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-09 21:29:46 +01:00
Russell King
5a89770daa Merge branches 'pxa-core' and 'pxa-machines' into pxa-all
Conflicts:

	arch/arm/mach-pxa/Kconfig
	arch/arm/mach-pxa/pxa25x.c
	arch/arm/mach-pxa/pxa27x.c
2008-10-07 19:08:56 +01:00
Russell King
07f841b7c5 [ARM] mm: enable sparsemem on clps7500 and RiscPC
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:24:04 +01:00
Russell King
d2a38ef9c1 [ARM] mm: provide helpers for accessing membanks
Provide helpers for getting physical addresses or pfns from the
meminfo array, and use them.  Move for_each_nodebank() to
asm/setup.h alongside the meminfo structure definition.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 17:22:02 +01:00
Russell King
8ec53663d2 [ARM] Improve non-executable support
Add support for detecting non-executable stack binaries, and adjust
permissions to prevent execution from data and stack areas.  Also,
ensure that READ_IMPLIES_EXEC is enabled for older CPUs where that
is true, and for any executable-stack binary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:10 +01:00
Russell King
5ec9407dd1 [ARM] Don't include asm/elf.h in asm code
asm code really wants asm/hwcap.h, so include that instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:10 +01:00
Russell King
9b727abdff [ARM] Remove MT_NONSHARED_DEVICE alias
Use MT_DEVICE_NONSHARED instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:07 +01:00
Russell King
db5b716947 [ARM] Remove MT_DEVICE_IXP2000 and associated definitions
As of the previous commit, MT_DEVICE_IXP2000 encodes to the same
PTE bit encoding as MT_DEVICE, so it's now redundant.  Convert
MT_DEVICE_IXP2000 to use MT_DEVICE instead, and remove its aliases.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:06 +01:00
Russell King
639b0ae7f5 [ARM] Convert ARMv6 and ARMv7 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:41:00 +01:00
Russell King
9e8b5199a7 [ARM] Convert Xscale and Xscale3 to use new memory types
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:58 +01:00
Russell King
bb30f36f9b [ARM] Introduce new PTE memory type bits
Provide L_PTE_MT_xxx definitions to describe the memory types that we
use in Linux/ARM.  These definitions are carefully picked such that:

1. their LSBs match what is required for pre-ARMv6 CPUs.
2. they all have a unique encoding, including after modification
   by build_mem_type_table() (the result being that some have more
   than one combination.)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:56 +01:00
Russell King
9cff96e5bf [ARM] Re-jig Linux PTE bits to allow room for 4 memory type bits
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-10-01 16:40:54 +01:00
Russell King
6c5da7aced [ARM] mm: move vmalloc= parsing to arch/arm/mm/mmu.c
There's no point scattering this around the tree, the parsing
of the parameter might as well live beside the code which uses
it.  That also means we can make vmalloc_reserve a static
variable.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 21:34:16 +01:00
Nicolas Pitre
dfcc64497c [ARM] 5271/1: get rid of pages_to_mb()
There is no use of this in the whole tree.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 16:40:59 +01:00
Russell King
7807c6098a [ARM] dma: fix some comments in dma-mapping.h
... to prevent people being mislead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 11:30:53 +01:00
Russell King
309dbbabee [ARM] dma: don't touch cache on dma_*_for_cpu()
As per the dma_unmap_* calls, we don't touch the cache when a DMA
buffer transitions from device to CPU ownership.  Presently, no
problems have been identified with speculative cache prefetching
which in itself is a new feature in later architectures.  We may
have to revisit the DMA API later for these architectures anyway.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-30 11:01:36 +01:00
Russell King
0e18b5d7c6 [ARM] dma: add validation of DMA params
Validate the direction argument like x86 does.  In addition,
validate the dma_unmap_* parameters against those passed to
dma_map_* when using the DMA bounce code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29 13:54:28 +01:00
Russell King
3216a97bb0 [ARM] dma: coding style cleanups
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29 10:41:02 +01:00
Russell King
125ab12acf [ARM] dma: fix dmabounce dma_sync_xxx() implementations
The dmabounce dma_sync_xxx() implementation have been broken for
quite some time; they all copy data between the DMA buffer and
the CPU visible buffer no irrespective of the change of ownership.
(IOW, a DMA_FROM_DEVICE mapping copies data from the DMA buffer
to the CPU buffer during a call to dma_sync_single_for_device().)

Fix it by getting rid of sync_single(), moving the contents into
the recently created dmabounce_sync_for_xxx() functions and adjusting
appropriately.

This also makes it possible to properly support the DMA range sync
functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29 10:40:22 +01:00
Russell King
8c8a0ec57e [ARM] dma: use new dmabounce_sync_for_xxx() for dma_sync_single_xxx()
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29 10:40:16 +01:00
Russell King
2638b4dbe7 [ARM] dma: Reduce to one dma_sync_sg_* implementation
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-29 10:40:16 +01:00
David Howells
bc173c5789 ARM: Delete ARM's own cnt32_to_63.h
Delete ARM's own cnt32_to_63.h as the copy in include/linux/ should now be
used instead.

Signed-off-by: David Howells <dhowells@redhat.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2008-09-26 08:49:04 -07:00
Russell King
56f55f8b58 [ARM] dma: provide a better dma_map_page() implementation
We can translate a struct page directly to a DMA address using
page_to_dma().  No need to use page_address() followed by
virt_to_dma().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 23:39:24 +01:00
Russell King
afd1a321c4 [ARM] Update dma_map_sg()/dma_unmap_sg() API
Update the ARM DMA scatter gather APIs for the scatterlist changes.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 20:48:45 +01:00
Russell King
c0e9587841 [ARM] Introduce new bitmask based cache type macros
Rather than trying to (inaccurately) decode the cache type from the
registers each time we need to decide what type of cache we have,
use a bitmask initialized early during boot.

Since the setup is a one-off initialization, we can be a little more
clever and take account of the CPU architecture as well.

Note that we continue to achieve the compactness on optimised kernels
by forcing tests to always-false or always-true as appropriate, thereby
allowing the compiler to do build-time code elimination.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 15:35:28 +01:00
Russell King
73b610affe [ARM] pxa: remove references to pxa_gpio_mode() in comments
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-25 13:35:27 +01:00
Russell King
88c381bf09 [ARM] Fix PCI_DMA_BUS_IS_PHYS for ARM
PCI_DMA_BUS_IS_PHYS was defined to be zero, which meant we ignored
the DMA mask for IDE and SCSI transfers.  This is wrong - we have
no DMA translation hardware.  We want to obey DMA masks so that the
block layer performs bouncing itself.

Reported-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-13 21:35:55 +01:00
Linus Torvalds
4ced08b89f Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 5241/1: provide ioremap_wc()
  [ARM] omap: fix virtual vs physical address space confusions
  [ARM] remove unused #include <version.h>
  [ARM] omap: fix build error in ohci-omap.c
  [ARM] omap: fix gpio.c build error
2008-09-08 15:50:19 -07:00
Lennert Buytenhek
1ad77a876d [ARM] 5241/1: provide ioremap_wc()
This patch provides an ARM implementation of ioremap_wc().

We use different page table attributes depending on which CPU we
are running on:

- Non-XScale ARMv5 and earlier systems: The ARMv5 ARM documents four
  possible mapping types (CB=00/01/10/11).  We can't use any of the
  cached memory types (CB=10/11), since that breaks coherency with
  peripheral devices.  Both CB=00 and CB=01 are suitable for _wc, and
  CB=01 (Uncached/Buffered) allows the hardware more freedom than
  CB=00, so we'll use that.

  (The ARMv5 ARM seems to suggest that CB=01 is allowed to delay stores
  but isn't allowed to merge them, but there is no other mapping type
  we can use that allows the hardware to delay and merge stores, so
  we'll go with CB=01.)

- XScale v1/v2 (ARMv5): same as the ARMv5 case above, with the slight
  difference that on these platforms, CB=01 actually _does_ allow
  merging stores.  (If you want noncoalescing bufferable behavior
  on Xscale v1/v2, you need to use XCB=101.)

- Xscale v3 (ARMv5) and ARMv6+: on these systems, we use TEXCB=00100
  mappings (Inner/Outer Uncacheable in xsc3 parlance, Uncached Normal
  in ARMv6 parlance).

  The ARMv6 ARM explicitly says that any accesses to Normal memory can
  be merged, which makes Normal memory more suitable for _wc mappings
  than Device or Strongly Ordered memory, as the latter two mapping
  types are guaranteed to maintain transaction number, size and order.
  We use the Uncached variety of Normal mappings for the same reason
  that we can't use C=1 mappings on ARMv5.

  The xsc3 Architecture Specification documents TEXCB=00100 as being
  Uncacheable and allowing coalescing of writes, which is also just
  what we need.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 13:13:44 +01:00
Russell King
fced80c735 [ARM] Convert asm/io.h to linux/io.h
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 12:10:45 +01:00
Russell King
446616dbb4 [ARM] sparse: quieten arch/arm/kernel/irq.c
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 10:56:27 +01:00
Russell King
1de765c1e9 [ARM] remove pc_pointer()
pc_pointer() was a function to mask the PC for 26-bit ARMs, which
we no longer support.  Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-06 10:35:51 +01:00
David Woodhouse
b35de672e7 Revert "[ARM] use the new byteorder headers"
This reverts commit ae82cbfc8b. It
needs the new byteorder headers to be exported to userspace, and
they aren't yet -- and probably shouldn't be, at this point in the
2.6.27 release cycle (or ever, for that matter).

Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-05 17:01:50 +01:00
David Woodhouse
a5e48a28d0 ARM: Use <asm-generic/statfs.h>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
2008-09-04 09:46:11 +01:00
Catalin Marinas
4e6a0c397f [ARM] 5230/1: Replace post-indexed LDRT/STRT in uaccess.h
The post-index immediate value is optional if it is 0 and this patch
removes it. The reason is to allow such instructions to compile to
Thumb-2 where only pre-indexed LDRT/STRT instructions are allowed.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:35 +01:00
Lennert Buytenhek
8d5796d2ec [ARM] 5222/1: Allow configuring user:kernel split via Kconfig
This patch adds a config option (CONFIG_VMSPLIT_*) to allow choosing
between 3:1, 2:2 and 1:3 user:kernel memory splits.

Tested-by: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:33 +01:00
Nicolas Pitre
d81030a1ba [ARM] 5211/2: fix a couple warnings from BUG() usage
When CONFIG_DEBUG_BUGVERBOSE is not set, we get warnings such as:

arch/arm/mm/ioremap.c: In function ‘remap_area_pte’:
arch/arm/mm/ioremap.c:67: warning: control reaches end of non-void function
mm/bootmem.c: In function ‘mark_bootmem’:
mm/bootmem.c:321: warning: control reaches end of non-void function
fs/dcache.c: In function ‘d_materialise_unique’:
fs/dcache.c:1875: warning: control reaches end of non-void function
fs/nfs/client.c: In function ‘nfs_sockaddr_match_ipaddr’:
fs/nfs/client.c:251: warning: control reaches end of non-void function
block/cfq-iosched.c: In function ‘cfq_async_queue_prio’:
block/cfq-iosched.c:1501: warning: control reaches end of non-void function

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:27 +01:00
Mikael Pettersson
e589ed23dd [ARM] 5218/1: arm: improved futex support
Linux/ARM currently doesn't support robust or PI futexes.
The problem is that the kernel wants to perform certain ops
(cmpxchg, set, add, or, andn, xor) atomically on user-space
addresses, and ARM's futex.h doesn't support that.

This patch adds that support, but only for uniprocessor machines.
For UP it's enough to disable preemption to ensure mutual exclusion
with other software agents (futexes don't need to care about other
hardware agents, fortunately).

This patch is based on one posted by Khem Raj on 2007-08-01
<http://marc.info/?l=linux-arm-kernel&m=118599407413016&w=2>.
(That patch is included in the -RT kernel patches.)
My changes since that version include:
* corrected implementation of FUTEX_OP_ANDN (must complement oparg)
* added missing memory clobber to futex_atomic_cmpxchg_inatomic()
* removed spinlock because it's unnecessary for UP and insufficient
  for SMP, instead the code is restricted to UP and relies on the
  fact that pagefault_disable() also disables preemption
* coding style cleanups

Tested on ARMv5 XScales with the glibc-2.6 nptl test suite.

Tested-by: Bruce Ashfield <bruce.ashfield@windriver.com>

Signed-off-by: Mikael Pettersson <mikpe@it.uu.se>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:26 +01:00
Nicolas Pitre
3305a60795 [ARM] 5206/1: remove kprobe_trap_handler() hack
As mentioned in commit 796969104c,
and because of commit b03a5b7559,
the direct calling of kprobe_trap_handler() can be removed.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:26 +01:00
Russell King
46097c7dd8 [ARM] cachetype: move definitions to separate header
Rather than pollute asm/cacheflush.h with the cache type definitions,
move them to asm/cachetype.h, and include this new header where
necessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:24 +01:00
Russell King
0ba8b9b273 [ARM] cputype: separate definitions, use them
Add asm/cputype.h, moving functions and definitions from asm/system.h
there.  Convert all users of 'processor_id' to the more efficient
read_cpuid_id() function.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-09-01 12:06:23 +01:00
Harvey Harrison
ae82cbfc8b [ARM] use the new byteorder headers
Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2008-08-27 20:05:27 +01:00
Linus Torvalds
9c0d2a20fe Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (38 commits)
  [ARM] 5191/1: ARM: remove CVS keywords
  [ARM] pxafb: fix the warning of incorrect lccr when lcd_conn is specified
  [ARM] pxafb: add flag to specify output format on LDD pins when base is RGBT16
  [ARM] pxafb: fix the incorrect configuration of GPIO77 as ACBIAS for TFT LCD
  [ARM] 5198/1: PalmTX: PCMCIA fixes
  [ARM] Fix a pile of broken watchdog drivers
  [ARM] update mach-types
  [ARM] 5196/1: fix inline asm constraints for preload
  [ARM] 5194/1: update .gitignore
  [ARM] add proc-macros.S include to proc-arm940 and proc-arm946
  [ARM] 5192/1: ARM TLB: add v7wbi_{possible,always}_flags to {possible,always}_tlb_flags
  [ARM] 5193/1: Wire up missing syscalls
  [ARM] traps: don't call undef hook functions with spinlock held
  [ARM] 5183/2: Provide Poodle LoCoMo GPIO names
  [ARM] dma-mapping: provide sync_range APIs
  [ARM] dma-mapping: improve type-safeness of DMA translations
  [ARM] Kirkwood: instantiate the orion_spi driver in the platform code
  [ARM] prevent crashing when too much RAM installed
  [ARM] Kirkwood: Instantiate mv_xor driver
  [ARM] Orion: Instantiate mv_xor driver for 5182
  ...
2008-08-16 16:48:45 -07:00