Some PLLs had one half the step size added to the offset, so that the
divisor would be rounded to the nearest integer. Some didn't and so
would always be rounded down.
This makes dvb-pll round to the nearest when calculating the divisor,
without the offset needing to be fudged. PLLs that had a fudged offset
have the offset changed to be just the IF frequency.
The satellite PLL dvb_pll_philips_sd1878_tda8261 was rounding up for some
reason, and I've kept it that way.
In addition, frequencies that were rounded to the nearest kHz are
extended to full Hz resolution. One sixth MHz step sizes that were
listed as 166,666 Hz are changed to 166,667 Hz, which is slightly closer.
PLLs that were already rounding:
dvb_pll_tda665x, offset was 36 1/6 (to nearest kHz) + step/2
dvb_pll_fmd1216me, offset was 36 1/8 (to two digits) + step/2
dvb_pll_thomson_fe6600, offset was 36 1/8 (to two digits) + step/2
dvb_pll_env57h1xd5, offset was 36 1/8 + step
Note that the last PLL, dvb_pll_env57h1xd5, appears to have had a bug in
the offset. Rather than adding stepsize/2, it was adding a full
stepsize. The PLL definition originally came from the dibusb driver,
which used 36 1/8 + step/2. The change to 36 1/8 + step was probably a
mistake added when the tuner was converted to dvb-pll.
Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
Acked-by: Michael Krufky <mkrufky@linuxtv.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab@infradead.org>
0fd17d6da8