e2fee5723b
The built-in Loongson 2E/2F northbridge in is bonito64-compatible but not identical with it. To avoid influencing the original bonito64 support and make the loongson support more maintainable, it's better to separate the Bonito64 code from the Loongson code. This also prepares the kernel for the coming Loongson 2f machines family support. Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: Zhang Le <r0bertz@gentoo.org> Cc: zhangfx@lemote.com, Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
72 lines
1.7 KiB
C
72 lines
1.7 KiB
C
/*
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* Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
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* Author: Fuxin Zhang, zhangfx@lemote.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <asm/irq_cpu.h>
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#include <asm/i8259.h>
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#include <loongson.h>
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static void i8259_irqdispatch(void)
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{
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int irq;
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irq = i8259_irq();
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if (irq >= 0)
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do_IRQ(irq);
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else
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spurious_interrupt();
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}
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asmlinkage void mach_irq_dispatch(unsigned int pending)
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{
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if (pending & CAUSEF_IP7)
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do_IRQ(MIPS_CPU_IRQ_BASE + 7);
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else if (pending & CAUSEF_IP6) /* perf counter loverflow */
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do_IRQ(LOONGSON2_PERFCNT_IRQ);
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else if (pending & CAUSEF_IP5)
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i8259_irqdispatch();
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else if (pending & CAUSEF_IP2)
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bonito_irqdispatch();
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else
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spurious_interrupt();
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}
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static struct irqaction cascade_irqaction = {
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.handler = no_action,
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.name = "cascade",
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};
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void __init set_irq_trigger_mode(void)
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{
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/* most bonito irq should be level triggered */
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LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR |
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LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES;
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}
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void __init mach_init_irq(void)
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{
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/* init all controller
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* 0-15 ------> i8259 interrupt
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* 16-23 ------> mips cpu interrupt
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* 32-63 ------> bonito irq
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*/
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/* Sets the first-level interrupt dispatcher. */
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mips_cpu_irq_init();
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init_i8259_irqs();
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bonito_irq_init();
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/* bonito irq at IP2 */
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setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
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/* 8259 irq at IP5 */
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setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
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}
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