7b7bcefa35
Correspondence with the TI OMAP hardware team indicates that SDRC_DLLA_CTRL.FIXEDDELAY should be initialized to 0x0f. This number was apparently derived from process validation. This is only used when the SDRC DLL is unlocked (e.g., SDRC clock frequency less than 83MHz). Signed-off-by: Paul Walmsley <paul@pwsan.com>
226 lines
6.7 KiB
ArmAsm
226 lines
6.7 KiB
ArmAsm
/*
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* linux/arch/arm/mach-omap3/sram.S
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*
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* Omap3 specific functions that need to be run in internal SRAM
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*
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* Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
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* Copyright (C) 2008 Nokia Corporation
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*
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* Rajendra Nayak <rnayak@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include "sdrc.h"
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#include "cm.h"
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.text
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/* r4 parameters */
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#define SDRC_NO_UNLOCK_DLL 0x0
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#define SDRC_UNLOCK_DLL 0x1
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/* SDRC_DLLA_CTRL bit settings */
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#define FIXEDDELAY_SHIFT 24
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#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
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#define DLLIDLE_MASK 0x4
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/*
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* SDRC_DLLA_CTRL default values: TI hardware team indicates that
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* FIXEDDELAY should be initialized to 0xf. This apparently was
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* empirically determined during process testing, so no derivation
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* was provided.
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*/
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#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
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/* SDRC_DLLA_STATUS bit settings */
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#define LOCKSTATUS_MASK 0x4
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/* SDRC_POWER bit settings */
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#define SRFRONIDLEREQ_MASK 0x40
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#define PWDENA_MASK 0x4
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/* CM_IDLEST1_CORE bit settings */
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#define ST_SDRC_MASK 0x2
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/* CM_ICLKEN1_CORE bit settings */
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#define EN_SDRC_MASK 0x2
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/* CM_CLKSEL1_PLL bit settings */
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#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
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/*
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* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
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* r0 = new SDRC_RFR_CTRL register contents
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* r1 = new SDRC_ACTIM_CTRLA register contents
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* r2 = new SDRC_ACTIM_CTRLB register contents
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* r3 = new M2 divider setting (only 1 and 2 supported right now)
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* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = new SDRC_MR_0 register value
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* r7 = increasing SDRC rate? (1 = yes, 0 = no)
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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ldr r7, [sp, #64] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r7, #1 @ if increasing SDRC clk rate,
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bleq configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
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bleq unlock_dll
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blne lock_dll
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bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
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bl configure_core_dpll @ change the DPLL3 M2 divider
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bl enable_sdrc @ take SDRC out of idle
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cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r7, #1 @ if increasing SDRC clk rate,
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beq return_to_sdram @ return to SDRAM code, otherwise,
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bl configure_sdrc @ reprogram SDRC regs now
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mov r12, r5
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bl wait_clk_stable @ wait for SDRC to stabilize
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return_to_sdram:
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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unlock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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and r12, r12, #FIXEDDELAY_MASK
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orr r12, r12, #FIXEDDELAY_DEFAULT
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orr r12, r12, #DLLIDLE_MASK
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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lock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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bic r12, r12, #DLLIDLE_MASK
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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sdram_in_selfrefresh:
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ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
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bic r12, r12, #PWDENA_MASK @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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idle_sdrc:
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
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cmp r12, #ST_SDRC_MASK
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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ldr r11, omap3_cm_clksel1_pll
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ldr r12, [r11]
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ldr r10, core_m2_mask_val @ modify m2 for core dpll
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and r12, r12, r10
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orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
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str r12, [r11]
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ldr r12, [r11] @ posted-write barrier for CM
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bx lr
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wait_clk_stable:
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subs r12, r12, #1
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bne wait_clk_stable
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bx lr
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enable_sdrc:
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ldr r11, omap3_cm_iclken1_core
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ldr r12, [r11]
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orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle1:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #ST_SDRC_MASK
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cmp r12, #0
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bne wait_sdrc_idle1
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restore_sdrc_power_val:
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ldr r11, omap3_sdrc_power
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str r9, [r11] @ restore SDRC_POWER, no barrier needed
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bx lr
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wait_dll_lock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #LOCKSTATUS_MASK
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cmp r12, #LOCKSTATUS_MASK
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #LOCKSTATUS_MASK
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cmp r12, #0x0
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bne wait_dll_unlock
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bx lr
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configure_sdrc:
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ldr r11, omap3_sdrc_rfr_ctrl
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str r0, [r11]
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ldr r11, omap3_sdrc_actim_ctrla
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str r1, [r11]
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ldr r11, omap3_sdrc_actim_ctrlb
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str r2, [r11]
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ldr r11, omap3_sdrc_mr_0
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str r6, [r11]
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ldr r6, [r11] @ posted-write barrier for SDRC
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bx lr
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omap3_sdrc_power:
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.word OMAP34XX_SDRC_REGADDR(SDRC_POWER)
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omap3_cm_clksel1_pll:
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.word OMAP34XX_CM_REGADDR(PLL_MOD, CM_CLKSEL1)
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omap3_cm_idlest1_core:
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.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
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omap3_cm_iclken1_core:
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.word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
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omap3_sdrc_rfr_ctrl:
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.word OMAP34XX_SDRC_REGADDR(SDRC_RFR_CTRL_0)
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omap3_sdrc_actim_ctrla:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
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omap3_sdrc_actim_ctrlb:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
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omap3_sdrc_mr_0:
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.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
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omap3_sdrc_dlla_status:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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omap3_sdrc_dlla_ctrl:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
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core_m2_mask_val:
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.word 0x07FFFFFF
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ENTRY(omap3_sram_configure_core_dpll_sz)
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.word . - omap3_sram_configure_core_dpll
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