1b374e4d6f
Introduce basic apic operations which handle the apic programming. This will be used later to introduce another specific operations for x2apic. For the perfomance critial accesses like IPI's, EOI etc, we use the native operations as they are already referenced by different indirections like genapic, irq_chip etc. 64bit Paravirt ops can also define their apic operations accordingly. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: akpm@linux-foundation.org Cc: arjan@linux.intel.com Cc: andi@firstfloor.org Cc: ebiederm@xmission.com Cc: jbarnes@virtuousgeek.org Cc: steiner@sgi.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
139 lines
2.9 KiB
C
139 lines
2.9 KiB
C
#ifndef __ASM_IPI_H
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#define __ASM_IPI_H
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/*
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* Copyright 2004 James Cleverdon, IBM.
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* Subject to the GNU Public License, v.2
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*
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* Generic APIC InterProcessor Interrupt code.
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*
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* Moved to include file by James Cleverdon from
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* arch/x86-64/kernel/smp.c
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*
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* Copyrights from kernel/smp.c:
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998-99, 2000 Ingo Molnar <mingo@redhat.com>
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* (c) 2002,2003 Andi Kleen, SuSE Labs.
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* Subject to the GNU Public License, v.2
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*/
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#include <asm/hw_irq.h>
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#include <asm/apic.h>
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#include <asm/smp.h>
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/*
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* the following functions deal with sending IPIs between CPUs.
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*
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* We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
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*/
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static inline unsigned int __prepare_ICR(unsigned int shortcut, int vector,
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unsigned int dest)
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{
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unsigned int icr = shortcut | dest;
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switch (vector) {
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default:
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icr |= APIC_DM_FIXED | vector;
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break;
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case NMI_VECTOR:
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icr |= APIC_DM_NMI;
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break;
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}
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return icr;
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}
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static inline int __prepare_ICR2(unsigned int mask)
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{
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return SET_APIC_DEST_FIELD(mask);
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}
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static inline void __xapic_wait_icr_idle(void)
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{
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while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)
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cpu_relax();
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}
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static inline void __send_IPI_shortcut(unsigned int shortcut, int vector,
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unsigned int dest)
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{
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/*
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* Subtle. In the case of the 'never do double writes' workaround
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* we have to lock out interrupts to be safe. As we don't care
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* of the value read we use an atomic rmw access to avoid costly
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* cli/sti. Otherwise we use an even cheaper single atomic write
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* to the APIC.
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*/
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unsigned int cfg;
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/*
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* Wait for idle.
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*/
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__xapic_wait_icr_idle();
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/*
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* No need to touch the target chip field
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*/
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cfg = __prepare_ICR(shortcut, vector, dest);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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native_apic_mem_write(APIC_ICR, cfg);
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}
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/*
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* This is used to send an IPI with no shorthand notation (the destination is
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* specified in bits 56 to 63 of the ICR).
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*/
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static inline void __send_IPI_dest_field(unsigned int mask, int vector,
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unsigned int dest)
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{
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unsigned long cfg;
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/*
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* Wait for idle.
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*/
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if (unlikely(vector == NMI_VECTOR))
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safe_apic_wait_icr_idle();
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else
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__xapic_wait_icr_idle();
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/*
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* prepare target chip field
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*/
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cfg = __prepare_ICR2(mask);
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native_apic_mem_write(APIC_ICR2, cfg);
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/*
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* program the ICR
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*/
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cfg = __prepare_ICR(0, vector, dest);
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/*
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* Send the IPI. The write to APIC_ICR fires this off.
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*/
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native_apic_mem_write(APIC_ICR, cfg);
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}
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static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
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{
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unsigned long flags;
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unsigned long query_cpu;
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/*
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* Hack. The clustered APIC addressing mode doesn't allow us to send
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* to an arbitrary mask, so I do a unicast to each CPU instead.
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* - mbligh
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*/
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local_irq_save(flags);
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for_each_cpu_mask(query_cpu, mask) {
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__send_IPI_dest_field(per_cpu(x86_cpu_to_apicid, query_cpu),
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vector, APIC_DEST_PHYSICAL);
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}
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local_irq_restore(flags);
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}
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#endif /* __ASM_IPI_H */
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