2f135eaf18
On the OMAP3, initialize SDRC timings when the kernel boots. This ensures that the kernel is running with known, optimized SDRC timings, rather than whatever was configured by the bootloader. Signed-off-by: Paul Walmsley <paul@pwsan.com>
291 lines
6.6 KiB
C
291 lines
6.6 KiB
C
/*
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* linux/arch/arm/mach-omap2/io.c
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*
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* OMAP2 I/O mapping code
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*
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* Copyright (C) 2005 Nokia Corporation
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* Copyright (C) 2007-2009 Texas Instruments
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*
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* Author:
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* Juha Yrjola <juha.yrjola@nokia.com>
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* Syed Khasim <x0khasim@ti.com>
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*
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/tlb.h>
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#include <asm/mach/map.h>
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#include <mach/mux.h>
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#include <mach/omapfb.h>
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#include <mach/sram.h>
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#include <mach/sdrc.h>
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#include <mach/gpmc.h>
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#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
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#include "clock.h"
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#include <mach/powerdomain.h>
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#include "powerdomains.h"
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#include <mach/clockdomain.h>
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#include "clockdomains.h"
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#endif
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/*
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* The machine specific code may provide the extra mapping besides the
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* default mapping provided here.
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*/
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#ifdef CONFIG_ARCH_OMAP24XX
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static struct map_desc omap24xx_io_desc[] __initdata = {
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{
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.virtual = L3_24XX_VIRT,
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.pfn = __phys_to_pfn(L3_24XX_PHYS),
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.length = L3_24XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_24XX_VIRT,
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.pfn = __phys_to_pfn(L4_24XX_PHYS),
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.length = L4_24XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#ifdef CONFIG_ARCH_OMAP2420
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static struct map_desc omap242x_io_desc[] __initdata = {
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{
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.virtual = DSP_MEM_24XX_VIRT,
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.pfn = __phys_to_pfn(DSP_MEM_24XX_PHYS),
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.length = DSP_MEM_24XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_IPI_24XX_VIRT,
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.pfn = __phys_to_pfn(DSP_IPI_24XX_PHYS),
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.length = DSP_IPI_24XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = DSP_MMU_24XX_VIRT,
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.pfn = __phys_to_pfn(DSP_MMU_24XX_PHYS),
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.length = DSP_MMU_24XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP2430
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static struct map_desc omap243x_io_desc[] __initdata = {
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{
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.virtual = L4_WK_243X_VIRT,
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.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
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.length = L4_WK_243X_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
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.length = OMAP243X_GPMC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
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.length = OMAP243X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP243X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
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.length = OMAP243X_SMS_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#endif
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#ifdef CONFIG_ARCH_OMAP34XX
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static struct map_desc omap34xx_io_desc[] __initdata = {
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{
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.virtual = L3_34XX_VIRT,
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.pfn = __phys_to_pfn(L3_34XX_PHYS),
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.length = L3_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_34XX_PHYS),
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.length = L4_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_WK_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_34XX_PHYS),
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.length = L4_WK_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP34XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
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.length = OMAP34XX_GPMC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SMS_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
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.length = OMAP343X_SMS_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = OMAP343X_SDRC_VIRT,
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.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
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.length = OMAP343X_SDRC_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_PER_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
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.length = L4_PER_34XX_SIZE,
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.type = MT_DEVICE
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},
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{
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.virtual = L4_EMU_34XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
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.length = L4_EMU_34XX_SIZE,
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.type = MT_DEVICE
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},
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};
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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static struct map_desc omap44xx_io_desc[] __initdata = {
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{
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.virtual = L3_44XX_VIRT,
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.pfn = __phys_to_pfn(L3_44XX_PHYS),
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.length = L3_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_44XX_PHYS),
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.length = L4_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_WK_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_WK_44XX_PHYS),
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.length = L4_WK_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = OMAP44XX_GPMC_VIRT,
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.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
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.length = OMAP44XX_GPMC_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_PER_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
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.length = L4_PER_44XX_SIZE,
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.type = MT_DEVICE,
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},
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{
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.virtual = L4_EMU_44XX_VIRT,
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.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
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.length = L4_EMU_44XX_SIZE,
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.type = MT_DEVICE,
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},
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};
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#endif
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void __init omap2_map_common_io(void)
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{
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#if defined(CONFIG_ARCH_OMAP2420)
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
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#endif
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#if defined(CONFIG_ARCH_OMAP2430)
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iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
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iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
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#endif
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#if defined(CONFIG_ARCH_OMAP34XX)
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iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
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#endif
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#if defined(CONFIG_ARCH_OMAP4)
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iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
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#endif
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/* Normally devicemaps_init() would flush caches and tlb after
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* mdesc->map_io(), but we must also do it here because of the CPU
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* revision check below.
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*/
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local_flush_tlb_all();
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flush_cache_all();
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omap2_check_revision();
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omap_sram_init();
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omapfb_reserve_sdram();
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}
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/*
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* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
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*
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* Sets the CORE DPLL3 M2 divider to the same value that it's at
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* currently. This has the effect of setting the SDRC SDRAM AC timing
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* registers to the values currently defined by the kernel. Currently
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* only defined for OMAP3; will return 0 if called on OMAP2. Returns
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* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
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* or passes along the return value of clk_set_rate().
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*/
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static int __init _omap2_init_reprogram_sdrc(void)
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{
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struct clk *dpll3_m2_ck;
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int v = -EINVAL;
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long rate;
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if (!cpu_is_omap34xx())
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return 0;
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dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
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if (!dpll3_m2_ck)
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return -EINVAL;
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rate = clk_get_rate(dpll3_m2_ck);
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pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
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v = clk_set_rate(dpll3_m2_ck, rate);
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if (v)
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pr_err("dpll3_m2_clk rate change failed: %d\n", v);
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clk_put(dpll3_m2_ck);
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return v;
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}
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void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
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{
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omap2_mux_init();
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#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once the clkdev is ready */
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pwrdm_init(powerdomains_omap);
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clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
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omap2_clk_init();
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omap2_sdrc_init(sp);
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_omap2_init_reprogram_sdrc();
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#endif
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gpmc_init();
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}
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