58d0831928
The header files describe the hardware registers available in both these chips, note that most of this documentation is automatically generated from the hardware implementation.
32 lines
668 B
C
32 lines
668 B
C
#ifndef _ASM_ARCH_CRIS_DMA_H
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#define _ASM_ARCH_CRIS_DMA_H
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/* Defines for using and allocating dma channels. */
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#define MAX_DMA_CHANNELS 12 /* 8 and 10 not used. */
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enum dma_owner {
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dma_eth,
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dma_ser0,
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dma_ser1,
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dma_ser2,
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dma_ser3,
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dma_ser4,
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dma_iop,
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dma_sser,
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dma_strp,
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dma_h264,
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dma_jpeg
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};
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int crisv32_request_dma(unsigned int dmanr, const char *device_id,
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unsigned options, unsigned bandwidth, enum dma_owner owner);
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void crisv32_free_dma(unsigned int dmanr);
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/* Masks used by crisv32_request_dma options: */
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#define DMA_VERBOSE_ON_ERROR 1
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#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR)
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#define DMA_INT_MEM 4
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#endif /* _ASM_ARCH_CRIS_DMA_H */
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