bd40791e1d
As the RSS grows, grow the TSB in order to reduce the likelyhood of hash collisions and thus poor hit rates in the TSB. This definitely needs some serious tuning. Signed-off-by: David S. Miller <davem@davemloft.net>
113 lines
3.4 KiB
C
113 lines
3.4 KiB
C
#ifndef __MMU_H
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#define __MMU_H
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#include <linux/config.h>
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#include <asm/page.h>
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#include <asm/const.h>
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/*
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* For the 8k pagesize kernel, use only 10 hw context bits to optimize some
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* shifts in the fast tlbmiss handlers, instead of all 13 bits (specifically
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* for vpte offset calculation). For other pagesizes, this optimization in
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* the tlbhandlers can not be done; but still, all 13 bits can not be used
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* because the tlb handlers use "andcc" instruction which sign extends 13
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* bit arguments.
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*/
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#if PAGE_SHIFT == 13
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#define CTX_NR_BITS 10
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#else
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#define CTX_NR_BITS 12
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#endif
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#define TAG_CONTEXT_BITS ((_AC(1,UL) << CTX_NR_BITS) - _AC(1,UL))
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/* UltraSPARC-III+ and later have a feature whereby you can
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* select what page size the various Data-TLB instances in the
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* chip. In order to gracefully support this, we put the version
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* field in a spot outside of the areas of the context register
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* where this parameter is specified.
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*/
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#define CTX_VERSION_SHIFT 22
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#define CTX_VERSION_MASK ((~0UL) << CTX_VERSION_SHIFT)
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#define CTX_PGSZ_8KB _AC(0x0,UL)
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#define CTX_PGSZ_64KB _AC(0x1,UL)
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#define CTX_PGSZ_512KB _AC(0x2,UL)
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#define CTX_PGSZ_4MB _AC(0x3,UL)
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#define CTX_PGSZ_BITS _AC(0x7,UL)
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#define CTX_PGSZ0_NUC_SHIFT 61
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#define CTX_PGSZ1_NUC_SHIFT 58
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#define CTX_PGSZ0_SHIFT 16
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#define CTX_PGSZ1_SHIFT 19
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#define CTX_PGSZ_MASK ((CTX_PGSZ_BITS << CTX_PGSZ0_SHIFT) | \
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(CTX_PGSZ_BITS << CTX_PGSZ1_SHIFT))
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#if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
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#define CTX_PGSZ_BASE CTX_PGSZ_8KB
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#elif defined(CONFIG_SPARC64_PAGE_SIZE_64KB)
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#define CTX_PGSZ_BASE CTX_PGSZ_64KB
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#elif defined(CONFIG_SPARC64_PAGE_SIZE_512KB)
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#define CTX_PGSZ_BASE CTX_PGSZ_512KB
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#elif defined(CONFIG_SPARC64_PAGE_SIZE_4MB)
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#define CTX_PGSZ_BASE CTX_PGSZ_4MB
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#else
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#error No page size specified in kernel configuration
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#endif
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#if defined(CONFIG_HUGETLB_PAGE_SIZE_4MB)
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#define CTX_PGSZ_HUGE CTX_PGSZ_4MB
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_512K)
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#define CTX_PGSZ_HUGE CTX_PGSZ_512KB
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#elif defined(CONFIG_HUGETLB_PAGE_SIZE_64K)
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#define CTX_PGSZ_HUGE CTX_PGSZ_64KB
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#endif
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#define CTX_PGSZ_KERN CTX_PGSZ_4MB
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/* Thus, when running on UltraSPARC-III+ and later, we use the following
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* PRIMARY_CONTEXT register values for the kernel context.
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*/
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#define CTX_CHEETAH_PLUS_NUC \
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((CTX_PGSZ_KERN << CTX_PGSZ0_NUC_SHIFT) | \
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(CTX_PGSZ_BASE << CTX_PGSZ1_NUC_SHIFT))
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#define CTX_CHEETAH_PLUS_CTX0 \
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((CTX_PGSZ_KERN << CTX_PGSZ0_SHIFT) | \
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(CTX_PGSZ_BASE << CTX_PGSZ1_SHIFT))
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/* If you want "the TLB context number" use CTX_NR_MASK. If you
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* want "the bits I program into the context registers" use
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* CTX_HW_MASK.
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*/
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#define CTX_NR_MASK TAG_CONTEXT_BITS
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#define CTX_HW_MASK (CTX_NR_MASK | CTX_PGSZ_MASK)
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#define CTX_FIRST_VERSION ((_AC(1,UL) << CTX_VERSION_SHIFT) + _AC(1,UL))
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#define CTX_VALID(__ctx) \
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(!(((__ctx.sparc64_ctx_val) ^ tlb_context_cache) & CTX_VERSION_MASK))
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#define CTX_HWBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_HW_MASK)
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#define CTX_NRBITS(__ctx) ((__ctx.sparc64_ctx_val) & CTX_NR_MASK)
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#ifndef __ASSEMBLY__
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#define TSB_ENTRY_ALIGNMENT 16
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struct tsb {
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unsigned long tag;
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unsigned long pte;
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} __attribute__((aligned(TSB_ENTRY_ALIGNMENT)));
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typedef struct {
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unsigned long sparc64_ctx_val;
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struct tsb *tsb;
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unsigned long tsb_rss_limit;
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unsigned long tsb_nentries;
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unsigned long tsb_reg_val;
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unsigned long tsb_map_vaddr;
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unsigned long tsb_map_pte;
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} mm_context_t;
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#endif /* !__ASSEMBLY__ */
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#endif /* __MMU_H */
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