d0e96f5a71
Allow device drivers to enqueue URBs to control endpoints on devices under an xHCI host controller. Each control transfer is represented by a series of Transfer Descriptors (TDs) written to an endpoint ring. There is one TD for the Setup phase, (optionally) one TD for the Data phase, and one TD for the Status phase. Enqueue these TDs onto the endpoint ring that represents the control endpoint. The host controller hardware will return an event on the event ring that points to the (DMA) address of one of the TDs on the endpoint ring. If the transfer was successful, the transfer event TRB will have a completion code of success, and it will point to the Status phase TD. Anything else is considered an error. This should work for control endpoints besides the default endpoint, but that hasn't been tested. Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
830 lines
24 KiB
C
830 lines
24 KiB
C
/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/irq.h>
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#include <linux/module.h>
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#include "xhci.h"
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#define DRIVER_AUTHOR "Sarah Sharp"
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#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
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/* TODO: copied from ehci-hcd.c - can this be refactored? */
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/*
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* handshake - spin reading hc until handshake completes or fails
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* @ptr: address of hc register to be read
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* @mask: bits to look at in result of read
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* @done: value of those bits when handshake succeeds
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* @usec: timeout in microseconds
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*
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* Returns negative errno, or zero on success
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*
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* Success happens when the "mask" bits have the specified value (hardware
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* handshake done). There are two failure modes: "usec" have passed (major
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* hardware flakeout), or the register reads as all-ones (hardware removed).
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*/
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static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
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u32 mask, u32 done, int usec)
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{
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u32 result;
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do {
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result = xhci_readl(xhci, ptr);
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if (result == ~(u32)0) /* card removed */
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return -ENODEV;
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result &= mask;
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if (result == done)
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return 0;
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udelay(1);
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usec--;
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} while (usec > 0);
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return -ETIMEDOUT;
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}
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/*
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* Force HC into halt state.
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*
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* Disable any IRQs and clear the run/stop bit.
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* HC will complete any current and actively pipelined transactions, and
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* should halt within 16 microframes of the run/stop bit being cleared.
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* Read HC Halted bit in the status register to see when the HC is finished.
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* XXX: shouldn't we set HC_STATE_HALT here somewhere?
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*/
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int xhci_halt(struct xhci_hcd *xhci)
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{
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u32 halted;
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u32 cmd;
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u32 mask;
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xhci_dbg(xhci, "// Halt the HC\n");
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/* Disable all interrupts from the host controller */
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mask = ~(XHCI_IRQS);
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halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
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if (!halted)
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mask &= ~CMD_RUN;
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cmd = xhci_readl(xhci, &xhci->op_regs->command);
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cmd &= mask;
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xhci_writel(xhci, cmd, &xhci->op_regs->command);
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return handshake(xhci, &xhci->op_regs->status,
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STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
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}
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/*
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* Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
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*
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* This resets pipelines, timers, counters, state machines, etc.
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* Transactions will be terminated immediately, and operational registers
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* will be set to their defaults.
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*/
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int xhci_reset(struct xhci_hcd *xhci)
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{
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u32 command;
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u32 state;
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state = xhci_readl(xhci, &xhci->op_regs->status);
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BUG_ON((state & STS_HALT) == 0);
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xhci_dbg(xhci, "// Reset the HC\n");
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command |= CMD_RESET;
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xhci_writel(xhci, command, &xhci->op_regs->command);
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/* XXX: Why does EHCI set this here? Shouldn't other code do this? */
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xhci_to_hcd(xhci)->state = HC_STATE_HALT;
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return handshake(xhci, &xhci->op_regs->command, CMD_RESET, 0, 250 * 1000);
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}
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/*
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* Stop the HC from processing the endpoint queues.
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*/
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static void xhci_quiesce(struct xhci_hcd *xhci)
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{
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/*
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* Queues are per endpoint, so we need to disable an endpoint or slot.
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*
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* To disable a slot, we need to insert a disable slot command on the
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* command ring and ring the doorbell. This will also free any internal
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* resources associated with the slot (which might not be what we want).
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*
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* A Release Endpoint command sounds better - doesn't free internal HC
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* memory, but removes the endpoints from the schedule and releases the
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* bandwidth, disables the doorbells, and clears the endpoint enable
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* flag. Usually used prior to a set interface command.
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*
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* TODO: Implement after command ring code is done.
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*/
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BUG_ON(!HC_IS_RUNNING(xhci_to_hcd(xhci)->state));
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xhci_dbg(xhci, "Finished quiescing -- code not written yet\n");
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}
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#if 0
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/* Set up MSI-X table for entry 0 (may claim other entries later) */
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static int xhci_setup_msix(struct xhci_hcd *xhci)
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{
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int ret;
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struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
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xhci->msix_count = 0;
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/* XXX: did I do this right? ixgbe does kcalloc for more than one */
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xhci->msix_entries = kmalloc(sizeof(struct msix_entry), GFP_KERNEL);
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if (!xhci->msix_entries) {
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xhci_err(xhci, "Failed to allocate MSI-X entries\n");
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return -ENOMEM;
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}
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xhci->msix_entries[0].entry = 0;
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ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
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if (ret) {
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xhci_err(xhci, "Failed to enable MSI-X\n");
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goto free_entries;
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}
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/*
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* Pass the xhci pointer value as the request_irq "cookie".
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* If more irqs are added, this will need to be unique for each one.
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*/
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ret = request_irq(xhci->msix_entries[0].vector, &xhci_irq, 0,
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"xHCI", xhci_to_hcd(xhci));
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if (ret) {
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xhci_err(xhci, "Failed to allocate MSI-X interrupt\n");
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goto disable_msix;
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}
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xhci_dbg(xhci, "Finished setting up MSI-X\n");
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return 0;
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disable_msix:
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pci_disable_msix(pdev);
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free_entries:
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kfree(xhci->msix_entries);
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xhci->msix_entries = NULL;
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return ret;
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}
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/* XXX: code duplication; can xhci_setup_msix call this? */
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/* Free any IRQs and disable MSI-X */
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static void xhci_cleanup_msix(struct xhci_hcd *xhci)
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{
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struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
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if (!xhci->msix_entries)
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return;
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free_irq(xhci->msix_entries[0].vector, xhci);
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pci_disable_msix(pdev);
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kfree(xhci->msix_entries);
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xhci->msix_entries = NULL;
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xhci_dbg(xhci, "Finished cleaning up MSI-X\n");
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}
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#endif
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/*
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* Initialize memory for HCD and xHC (one-time init).
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*
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* Program the PAGESIZE register, initialize the device context array, create
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* device contexts (?), set up a command ring segment (or two?), create event
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* ring (one for now).
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*/
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int xhci_init(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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int retval = 0;
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xhci_dbg(xhci, "xhci_init\n");
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spin_lock_init(&xhci->lock);
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retval = xhci_mem_init(xhci, GFP_KERNEL);
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xhci_dbg(xhci, "Finished xhci_init\n");
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return retval;
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}
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/*
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* Called in interrupt context when there might be work
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* queued on the event ring
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*
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* xhci->lock must be held by caller.
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*/
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static void xhci_work(struct xhci_hcd *xhci)
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{
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u32 temp;
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/*
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* Clear the op reg interrupt status first,
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* so we can receive interrupts from other MSI-X interrupters.
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* Write 1 to clear the interrupt status.
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*/
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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temp |= STS_EINT;
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xhci_writel(xhci, temp, &xhci->op_regs->status);
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/* FIXME when MSI-X is supported and there are multiple vectors */
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/* Clear the MSI-X event interrupt status */
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/* Acknowledge the interrupt */
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temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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temp |= 0x3;
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xhci_writel(xhci, temp, &xhci->ir_set->irq_pending);
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/* Flush posted writes */
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xhci_readl(xhci, &xhci->ir_set->irq_pending);
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/* FIXME this should be a delayed service routine that clears the EHB */
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handle_event(xhci);
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/* Clear the event handler busy flag; the event ring should be empty. */
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temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
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xhci_writel(xhci, temp & ~ERST_EHB, &xhci->ir_set->erst_dequeue[0]);
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/* Flush posted writes -- FIXME is this necessary? */
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xhci_readl(xhci, &xhci->ir_set->irq_pending);
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}
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/*-------------------------------------------------------------------------*/
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/*
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* xHCI spec says we can get an interrupt, and if the HC has an error condition,
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* we might get bad data out of the event ring. Section 4.10.2.7 has a list of
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* indicators of an event TRB error, but we check the status *first* to be safe.
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*/
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irqreturn_t xhci_irq(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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u32 temp, temp2;
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spin_lock(&xhci->lock);
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/* Check if the xHC generated the interrupt, or the irq is shared */
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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temp2 = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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if (!(temp & STS_EINT) && !ER_IRQ_PENDING(temp2)) {
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spin_unlock(&xhci->lock);
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return IRQ_NONE;
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}
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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if (temp & STS_FATAL) {
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xhci_warn(xhci, "WARNING: Host System Error\n");
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xhci_halt(xhci);
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xhci_to_hcd(xhci)->state = HC_STATE_HALT;
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return -ESHUTDOWN;
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}
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xhci_work(xhci);
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spin_unlock(&xhci->lock);
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return IRQ_HANDLED;
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}
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#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
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void event_ring_work(unsigned long arg)
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{
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unsigned long flags;
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int temp;
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struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
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int i, j;
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xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
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spin_lock_irqsave(&xhci->lock, flags);
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
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temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
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xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
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xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
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xhci->error_bitmask = 0;
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xhci_dbg(xhci, "Event ring:\n");
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xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
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xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
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temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
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temp &= ERST_PTR_MASK;
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xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
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xhci_dbg(xhci, "Command ring:\n");
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xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
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xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
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xhci_dbg_cmd_ptrs(xhci);
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for (i = 0; i < MAX_HC_SLOTS; ++i) {
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if (xhci->devs[i]) {
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for (j = 0; j < 31; ++j) {
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if (xhci->devs[i]->ep_rings[j]) {
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xhci_dbg(xhci, "Dev %d endpoint ring %d:\n", i, j);
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xhci_debug_segment(xhci, xhci->devs[i]->ep_rings[j]->deq_seg);
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}
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}
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}
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}
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if (xhci->noops_submitted != NUM_TEST_NOOPS)
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if (setup_one_noop(xhci))
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ring_cmd_db(xhci);
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spin_unlock_irqrestore(&xhci->lock, flags);
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if (!xhci->zombie)
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mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
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else
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xhci_dbg(xhci, "Quit polling the event ring.\n");
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}
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#endif
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/*
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* Start the HC after it was halted.
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*
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* This function is called by the USB core when the HC driver is added.
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* Its opposite is xhci_stop().
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*
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* xhci_init() must be called once before this function can be called.
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* Reset the HC, enable device slot contexts, program DCBAAP, and
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* set command ring pointer and event ring pointer.
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*
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* Setup MSI-X vectors and enable interrupts.
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*/
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int xhci_run(struct usb_hcd *hcd)
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{
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u32 temp;
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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void (*doorbell)(struct xhci_hcd *) = NULL;
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hcd->uses_new_polling = 1;
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hcd->poll_rh = 0;
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xhci_dbg(xhci, "xhci_run\n");
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#if 0 /* FIXME: MSI not setup yet */
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/* Do this at the very last minute */
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ret = xhci_setup_msix(xhci);
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if (!ret)
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return ret;
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return -ENOSYS;
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#endif
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#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
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init_timer(&xhci->event_ring_timer);
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xhci->event_ring_timer.data = (unsigned long) xhci;
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xhci->event_ring_timer.function = event_ring_work;
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/* Poll the event ring */
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xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
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xhci->zombie = 0;
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xhci_dbg(xhci, "Setting event ring polling timer\n");
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add_timer(&xhci->event_ring_timer);
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#endif
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xhci_dbg(xhci, "// Set the interrupt modulation register\n");
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temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
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temp &= 0xffff;
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temp |= (u32) 160;
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xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
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/* Set the HCD state before we enable the irqs */
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hcd->state = HC_STATE_RUNNING;
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temp = xhci_readl(xhci, &xhci->op_regs->command);
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temp |= (CMD_EIE);
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xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
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temp);
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xhci_writel(xhci, temp, &xhci->op_regs->command);
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temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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xhci_dbg(xhci, "// Enabling event ring interrupter 0x%x"
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" by writing 0x%x to irq_pending\n",
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(unsigned int) xhci->ir_set,
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(unsigned int) ER_IRQ_ENABLE(temp));
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xhci_writel(xhci, ER_IRQ_ENABLE(temp),
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&xhci->ir_set->irq_pending);
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xhci_print_ir_set(xhci, xhci->ir_set, 0);
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if (NUM_TEST_NOOPS > 0)
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doorbell = setup_one_noop(xhci);
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xhci_dbg(xhci, "Command ring memory map follows:\n");
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xhci_debug_ring(xhci, xhci->cmd_ring);
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xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
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xhci_dbg_cmd_ptrs(xhci);
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xhci_dbg(xhci, "ERST memory map follows:\n");
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xhci_dbg_erst(xhci, &xhci->erst);
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xhci_dbg(xhci, "Event ring:\n");
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xhci_debug_ring(xhci, xhci->event_ring);
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xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
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temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[1]);
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xhci_dbg(xhci, "ERST deq upper = 0x%x\n", temp);
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temp = xhci_readl(xhci, &xhci->ir_set->erst_dequeue[0]);
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temp &= ERST_PTR_MASK;
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xhci_dbg(xhci, "ERST deq = 0x%x\n", temp);
|
|
|
|
temp = xhci_readl(xhci, &xhci->op_regs->command);
|
|
temp |= (CMD_RUN);
|
|
xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
|
|
temp);
|
|
xhci_writel(xhci, temp, &xhci->op_regs->command);
|
|
/* Flush PCI posted writes */
|
|
temp = xhci_readl(xhci, &xhci->op_regs->command);
|
|
xhci_dbg(xhci, "// @%x = 0x%x\n",
|
|
(unsigned int) &xhci->op_regs->command, temp);
|
|
if (doorbell)
|
|
(*doorbell)(xhci);
|
|
|
|
xhci_dbg(xhci, "Finished xhci_run\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Stop xHCI driver.
|
|
*
|
|
* This function is called by the USB core when the HC driver is removed.
|
|
* Its opposite is xhci_run().
|
|
*
|
|
* Disable device contexts, disable IRQs, and quiesce the HC.
|
|
* Reset the HC, finish any completed transactions, and cleanup memory.
|
|
*/
|
|
void xhci_stop(struct usb_hcd *hcd)
|
|
{
|
|
u32 temp;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
spin_lock_irq(&xhci->lock);
|
|
if (HC_IS_RUNNING(hcd->state))
|
|
xhci_quiesce(xhci);
|
|
xhci_halt(xhci);
|
|
xhci_reset(xhci);
|
|
spin_unlock_irq(&xhci->lock);
|
|
|
|
#if 0 /* No MSI yet */
|
|
xhci_cleanup_msix(xhci);
|
|
#endif
|
|
#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
|
|
/* Tell the event ring poll function not to reschedule */
|
|
xhci->zombie = 1;
|
|
del_timer_sync(&xhci->event_ring_timer);
|
|
#endif
|
|
|
|
xhci_dbg(xhci, "// Disabling event ring interrupts\n");
|
|
temp = xhci_readl(xhci, &xhci->op_regs->status);
|
|
xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
|
|
temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
|
|
xhci_writel(xhci, ER_IRQ_DISABLE(temp),
|
|
&xhci->ir_set->irq_pending);
|
|
xhci_print_ir_set(xhci, xhci->ir_set, 0);
|
|
|
|
xhci_dbg(xhci, "cleaning up memory\n");
|
|
xhci_mem_cleanup(xhci);
|
|
xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
|
|
xhci_readl(xhci, &xhci->op_regs->status));
|
|
}
|
|
|
|
/*
|
|
* Shutdown HC (not bus-specific)
|
|
*
|
|
* This is called when the machine is rebooting or halting. We assume that the
|
|
* machine will be powered off, and the HC's internal state will be reset.
|
|
* Don't bother to free memory.
|
|
*/
|
|
void xhci_shutdown(struct usb_hcd *hcd)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
spin_lock_irq(&xhci->lock);
|
|
xhci_halt(xhci);
|
|
spin_unlock_irq(&xhci->lock);
|
|
|
|
#if 0
|
|
xhci_cleanup_msix(xhci);
|
|
#endif
|
|
|
|
xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
|
|
xhci_readl(xhci, &xhci->op_regs->status));
|
|
}
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/**
|
|
* xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
|
|
* HCDs. Find the index for an endpoint given its descriptor. Use the return
|
|
* value to right shift 1 for the bitmask.
|
|
*
|
|
* Index = (epnum * 2) + direction - 1,
|
|
* where direction = 0 for OUT, 1 for IN.
|
|
* For control endpoints, the IN index is used (OUT index is unused), so
|
|
* index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
|
|
*/
|
|
unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
|
|
{
|
|
unsigned int index;
|
|
if (usb_endpoint_xfer_control(desc))
|
|
index = (unsigned int) (usb_endpoint_num(desc)*2);
|
|
else
|
|
index = (unsigned int) (usb_endpoint_num(desc)*2) +
|
|
(usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
|
|
return index;
|
|
}
|
|
|
|
/* Returns 1 if the arguments are OK;
|
|
* returns 0 this is a root hub; returns -EINVAL for NULL pointers.
|
|
*/
|
|
int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
|
|
struct usb_host_endpoint *ep, int check_ep, const char *func) {
|
|
if (!hcd || (check_ep && !ep) || !udev) {
|
|
printk(KERN_DEBUG "xHCI %s called with invalid args\n",
|
|
func);
|
|
return -EINVAL;
|
|
}
|
|
if (!udev->parent) {
|
|
printk(KERN_DEBUG "xHCI %s called for root hub\n",
|
|
func);
|
|
return 0;
|
|
}
|
|
if (!udev->slot_id) {
|
|
printk(KERN_DEBUG "xHCI %s called with unaddressed device\n",
|
|
func);
|
|
return -EINVAL;
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* non-error returns are a promise to giveback() the urb later
|
|
* we drop ownership so next owner (or urb unlink) can get it
|
|
*/
|
|
int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
unsigned int slot_id, ep_index;
|
|
|
|
if (!urb || xhci_check_args(hcd, urb->dev, urb->ep, true, __func__) <= 0)
|
|
return -EINVAL;
|
|
|
|
slot_id = urb->dev->slot_id;
|
|
ep_index = xhci_get_endpoint_index(&urb->ep->desc);
|
|
/* Only support ep 0 control transfers for now */
|
|
if (ep_index != 0) {
|
|
xhci_dbg(xhci, "WARN: urb submitted to unsupported ep %x\n",
|
|
urb->ep->desc.bEndpointAddress);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (!xhci->devs || !xhci->devs[slot_id]) {
|
|
if (!in_interrupt())
|
|
dev_warn(&urb->dev->dev, "WARN: urb submitted for dev with no Slot ID\n");
|
|
return -EINVAL;
|
|
}
|
|
if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
|
|
if (!in_interrupt())
|
|
xhci_dbg(xhci, "urb submitted during PCI suspend\n");
|
|
ret = -ESHUTDOWN;
|
|
goto exit;
|
|
}
|
|
ret = queue_ctrl_tx(xhci, mem_flags, urb, slot_id, ep_index);
|
|
exit:
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
/* Remove from hardware lists
|
|
* completions normally happen asynchronously
|
|
*/
|
|
int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
|
|
{
|
|
return -ENOSYS;
|
|
}
|
|
|
|
/*
|
|
* At this point, the struct usb_device is about to go away, the device has
|
|
* disconnected, and all traffic has been stopped and the endpoints have been
|
|
* disabled. Free any HC data structures associated with that device.
|
|
*/
|
|
void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
unsigned long flags;
|
|
|
|
if (udev->slot_id == 0)
|
|
return;
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
return;
|
|
}
|
|
ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
/*
|
|
* Event command completion handler will free any data structures
|
|
* associated with the slot
|
|
*/
|
|
}
|
|
|
|
/*
|
|
* Returns 0 if the xHC ran out of device slots, the Enable Slot command
|
|
* timed out, or allocating memory failed. Returns 1 on success.
|
|
*/
|
|
int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
unsigned long flags;
|
|
int timeleft;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
ret = queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
|
|
if (ret) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
return 0;
|
|
}
|
|
ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* XXX: how much time for xHC slot assignment? */
|
|
timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
|
|
USB_CTRL_SET_TIMEOUT);
|
|
if (timeleft <= 0) {
|
|
xhci_warn(xhci, "%s while waiting for a slot\n",
|
|
timeleft == 0 ? "Timeout" : "Signal");
|
|
/* FIXME cancel the enable slot request */
|
|
return 0;
|
|
}
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (!xhci->slot_id) {
|
|
xhci_err(xhci, "Error while assigning device slot ID\n");
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return 0;
|
|
}
|
|
if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_KERNEL)) {
|
|
/* Disable slot, if we can do it without mem alloc */
|
|
xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
|
|
if (!queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
|
|
ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return 0;
|
|
}
|
|
udev->slot_id = xhci->slot_id;
|
|
/* Is this a LS or FS device under a HS hub? */
|
|
/* Hub or peripherial? */
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Issue an Address Device command (which will issue a SetAddress request to
|
|
* the device).
|
|
* We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
|
|
* we should only issue and wait on one address command at the same time.
|
|
*
|
|
* We add one to the device address issued by the hardware because the USB core
|
|
* uses address 1 for the root hubs (even though they're not really devices).
|
|
*/
|
|
int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
unsigned long flags;
|
|
int timeleft;
|
|
struct xhci_virt_device *virt_dev;
|
|
int ret = 0;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
u32 temp;
|
|
|
|
if (!udev->slot_id) {
|
|
xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
|
|
/* If this is a Set Address to an unconfigured device, setup ep 0 */
|
|
if (!udev->config)
|
|
xhci_setup_addressable_virt_dev(xhci, udev);
|
|
/* Otherwise, assume the core has the device configured how it wants */
|
|
|
|
ret = queue_address_device(xhci, virt_dev->in_ctx_dma, udev->slot_id);
|
|
if (ret) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
return ret;
|
|
}
|
|
ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
|
|
timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
|
|
USB_CTRL_SET_TIMEOUT);
|
|
/* FIXME: From section 4.3.4: "Software shall be responsible for timing
|
|
* the SetAddress() "recovery interval" required by USB and aborting the
|
|
* command on a timeout.
|
|
*/
|
|
if (timeleft <= 0) {
|
|
xhci_warn(xhci, "%s while waiting for a slot\n",
|
|
timeleft == 0 ? "Timeout" : "Signal");
|
|
/* FIXME cancel the address device command */
|
|
return -ETIME;
|
|
}
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
switch (virt_dev->cmd_status) {
|
|
case COMP_CTX_STATE:
|
|
case COMP_EBADSLT:
|
|
xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
|
|
udev->slot_id);
|
|
ret = -EINVAL;
|
|
break;
|
|
case COMP_TX_ERR:
|
|
dev_warn(&udev->dev, "Device not responding to set address.\n");
|
|
ret = -EPROTO;
|
|
break;
|
|
case COMP_SUCCESS:
|
|
xhci_dbg(xhci, "Successful Address Device command\n");
|
|
break;
|
|
default:
|
|
xhci_err(xhci, "ERROR: unexpected command completion "
|
|
"code 0x%x.\n", virt_dev->cmd_status);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
if (ret) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return ret;
|
|
}
|
|
temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[0]);
|
|
xhci_dbg(xhci, "Op regs DCBAA ptr[0] = %#08x\n", temp);
|
|
temp = xhci_readl(xhci, &xhci->op_regs->dcbaa_ptr[1]);
|
|
xhci_dbg(xhci, "Op regs DCBAA ptr[1] = %#08x\n", temp);
|
|
xhci_dbg(xhci, "Slot ID %d dcbaa entry[0] @%08x = %#08x\n",
|
|
udev->slot_id,
|
|
(unsigned int) &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id],
|
|
xhci->dcbaa->dev_context_ptrs[2*udev->slot_id]);
|
|
xhci_dbg(xhci, "Slot ID %d dcbaa entry[1] @%08x = %#08x\n",
|
|
udev->slot_id,
|
|
(unsigned int) &xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1],
|
|
xhci->dcbaa->dev_context_ptrs[2*udev->slot_id+1]);
|
|
xhci_dbg(xhci, "Output Context DMA address = %#08x\n",
|
|
virt_dev->out_ctx_dma);
|
|
xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
|
|
xhci_dbg_ctx(xhci, virt_dev->in_ctx, virt_dev->in_ctx_dma, 2);
|
|
xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
|
|
xhci_dbg_ctx(xhci, virt_dev->out_ctx, virt_dev->out_ctx_dma, 2);
|
|
/*
|
|
* USB core uses address 1 for the roothubs, so we add one to the
|
|
* address given back to us by the HC.
|
|
*/
|
|
udev->devnum = (virt_dev->out_ctx->slot.dev_state & DEV_ADDR_MASK) + 1;
|
|
/* FIXME: Zero the input context control for later use? */
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
xhci_dbg(xhci, "Device address = %d\n", udev->devnum);
|
|
/* XXX Meh, not sure if anyone else but choose_address uses this. */
|
|
set_bit(udev->devnum, udev->bus->devmap.devicemap);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int xhci_get_frame(struct usb_hcd *hcd)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
/* EHCI mods by the periodic size. Why? */
|
|
return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
|
|
}
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_LICENSE("GPL");
|
|
|
|
static int __init xhci_hcd_init(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
int retval = 0;
|
|
|
|
retval = xhci_register_pci();
|
|
|
|
if (retval < 0) {
|
|
printk(KERN_DEBUG "Problem registering PCI driver.");
|
|
return retval;
|
|
}
|
|
#endif
|
|
return 0;
|
|
}
|
|
module_init(xhci_hcd_init);
|
|
|
|
static void __exit xhci_hcd_cleanup(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
xhci_unregister_pci();
|
|
#endif
|
|
}
|
|
module_exit(xhci_hcd_cleanup);
|