d6c7e5f8fa
Remove unnecessary MMIO accesses in time critical irq handling path. Also ensured that the mailbox ack field is read in last, so we know for sure if we have a stale mailbox or not on receipt. Signed-off-by: Andy Walls <awalls@radix.net> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
/*
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* cx18 interrupt handling
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*
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* Copyright (C) 2007 Hans Verkuil <hverkuil@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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* 02111-1307 USA
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*/
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#include "cx18-driver.h"
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#include "cx18-io.h"
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#include "cx18-irq.h"
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#include "cx18-mailbox.h"
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#include "cx18-scb.h"
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static void xpu_ack(struct cx18 *cx, u32 sw2)
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{
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if (sw2 & IRQ_CPU_TO_EPU_ACK)
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wake_up(&cx->mb_cpu_waitq);
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if (sw2 & IRQ_APU_TO_EPU_ACK)
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wake_up(&cx->mb_apu_waitq);
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}
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static void epu_cmd(struct cx18 *cx, u32 sw1)
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{
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if (sw1 & IRQ_CPU_TO_EPU)
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cx18_api_epu_cmd_irq(cx, CPU);
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if (sw1 & IRQ_APU_TO_EPU)
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cx18_api_epu_cmd_irq(cx, APU);
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}
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irqreturn_t cx18_irq_handler(int irq, void *dev_id)
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{
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struct cx18 *cx = (struct cx18 *)dev_id;
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u32 sw1, sw2, hw2;
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sw1 = cx18_read_reg(cx, SW1_INT_STATUS) & cx->sw1_irq_mask;
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sw2 = cx18_read_reg(cx, SW2_INT_STATUS) & cx->sw2_irq_mask;
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hw2 = cx18_read_reg(cx, HW2_INT_CLR_STATUS) & cx->hw2_irq_mask;
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if (sw1)
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cx18_write_reg_expect(cx, sw1, SW1_INT_STATUS, ~sw1, sw1);
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if (sw2)
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cx18_write_reg_expect(cx, sw2, SW2_INT_STATUS, ~sw2, sw2);
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if (hw2)
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cx18_write_reg_expect(cx, hw2, HW2_INT_CLR_STATUS, ~hw2, hw2);
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if (sw1 || sw2 || hw2)
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CX18_DEBUG_HI_IRQ("received interrupts "
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"SW1: %x SW2: %x HW2: %x\n", sw1, sw2, hw2);
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/*
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* SW1 responses have to happen first. The sending XPU times out the
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* incoming mailboxes on us rather rapidly.
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*/
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if (sw1)
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epu_cmd(cx, sw1);
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/* To do: interrupt-based I2C handling
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if (hw2 & (HW2_I2C1_INT|HW2_I2C2_INT)) {
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}
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*/
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if (sw2)
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xpu_ack(cx, sw2);
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return (sw1 || sw2 || hw2) ? IRQ_HANDLED : IRQ_NONE;
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}
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