e08e6c5213
On SN2, MMIO writes which are issued from separate processors are not guaranteed to arrive in any particular order at the IO hardware. When performing such writes from the kernel this is not a problem, as a kernel thread will not migrate to another CPU during execution, and mmiowb() calls can guarantee write ordering when control of the IO resource is allowed to move between threads. However, when MMIO writes can be performed from user space (e.g. DRM) there are no such guarantees and mechanisms, as the process may context-switch at any time, and may migrate to a different CPU as part of the switch. For such programs/hardware to operate correctly, it is required that the MMIO writes from the old CPU be accepted by the IO hardware before subsequent writes from the new CPU can be issued. The following patch implements this behavior on SN2 by waiting for a Shub register to indicate that these writes have been accepted. This is placed in the context switch-in path, and only performs the wait when the newly scheduled task changes CPUs. Signed-off-by: Prarit Bhargava <prarit@sgi.com> Signed-off-by: Brent Casavant <bcasavan@sgi.com>
129 lines
5.3 KiB
C
129 lines
5.3 KiB
C
/*
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* Copyright (c) 2002-2003,2006 Silicon Graphics, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it would be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Further, this software is distributed without any warranty that it is
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* free of the rightful claim of any third person regarding infringement
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* or the like. Any license provided herein, whether implied or
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* otherwise, applies only to this software file. Patent licenses, if
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* any, provided herein do not apply to combinations of this program with
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* other software, or any other product whatsoever.
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*
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* You should have received a copy of the GNU General Public
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* License along with this program; if not, write the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
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*
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* Contact information: Silicon Graphics, Inc., 1600 Amphitheatre Pkwy,
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* Mountain View, CA 94043, or:
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*
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* http://www.sgi.com
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*
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* For further information regarding this notice, see:
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*
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* http://oss.sgi.com/projects/GenInfo/NoticeExplan
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*/
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#ifndef _ASM_IA64_MACHVEC_SN2_H
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#define _ASM_IA64_MACHVEC_SN2_H
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extern ia64_mv_setup_t sn_setup;
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extern ia64_mv_cpu_init_t sn_cpu_init;
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extern ia64_mv_irq_init_t sn_irq_init;
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extern ia64_mv_send_ipi_t sn2_send_IPI;
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extern ia64_mv_timer_interrupt_t sn_timer_interrupt;
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extern ia64_mv_global_tlb_purge_t sn2_global_tlb_purge;
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extern ia64_mv_tlb_migrate_finish_t sn_tlb_migrate_finish;
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extern ia64_mv_local_vector_to_irq sn_local_vector_to_irq;
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extern ia64_mv_pci_get_legacy_mem_t sn_pci_get_legacy_mem;
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extern ia64_mv_pci_legacy_read_t sn_pci_legacy_read;
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extern ia64_mv_pci_legacy_write_t sn_pci_legacy_write;
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extern ia64_mv_inb_t __sn_inb;
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extern ia64_mv_inw_t __sn_inw;
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extern ia64_mv_inl_t __sn_inl;
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extern ia64_mv_outb_t __sn_outb;
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extern ia64_mv_outw_t __sn_outw;
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extern ia64_mv_outl_t __sn_outl;
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extern ia64_mv_mmiowb_t __sn_mmiowb;
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extern ia64_mv_readb_t __sn_readb;
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extern ia64_mv_readw_t __sn_readw;
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extern ia64_mv_readl_t __sn_readl;
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extern ia64_mv_readq_t __sn_readq;
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extern ia64_mv_readb_t __sn_readb_relaxed;
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extern ia64_mv_readw_t __sn_readw_relaxed;
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extern ia64_mv_readl_t __sn_readl_relaxed;
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extern ia64_mv_readq_t __sn_readq_relaxed;
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extern ia64_mv_dma_alloc_coherent sn_dma_alloc_coherent;
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extern ia64_mv_dma_free_coherent sn_dma_free_coherent;
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extern ia64_mv_dma_map_single sn_dma_map_single;
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extern ia64_mv_dma_unmap_single sn_dma_unmap_single;
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extern ia64_mv_dma_map_sg sn_dma_map_sg;
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extern ia64_mv_dma_unmap_sg sn_dma_unmap_sg;
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extern ia64_mv_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu;
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extern ia64_mv_dma_sync_sg_for_cpu sn_dma_sync_sg_for_cpu;
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extern ia64_mv_dma_sync_single_for_device sn_dma_sync_single_for_device;
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extern ia64_mv_dma_sync_sg_for_device sn_dma_sync_sg_for_device;
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extern ia64_mv_dma_mapping_error sn_dma_mapping_error;
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extern ia64_mv_dma_supported sn_dma_supported;
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extern ia64_mv_migrate_t sn_migrate;
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/*
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* This stuff has dual use!
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*
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* For a generic kernel, the macros are used to initialize the
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* platform's machvec structure. When compiling a non-generic kernel,
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* the macros are used directly.
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*/
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#define platform_name "sn2"
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#define platform_setup sn_setup
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#define platform_cpu_init sn_cpu_init
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#define platform_irq_init sn_irq_init
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#define platform_send_ipi sn2_send_IPI
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#define platform_timer_interrupt sn_timer_interrupt
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#define platform_global_tlb_purge sn2_global_tlb_purge
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#define platform_tlb_migrate_finish sn_tlb_migrate_finish
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#define platform_pci_fixup sn_pci_fixup
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#define platform_inb __sn_inb
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#define platform_inw __sn_inw
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#define platform_inl __sn_inl
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#define platform_outb __sn_outb
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#define platform_outw __sn_outw
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#define platform_outl __sn_outl
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#define platform_mmiowb __sn_mmiowb
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#define platform_readb __sn_readb
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#define platform_readw __sn_readw
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#define platform_readl __sn_readl
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#define platform_readq __sn_readq
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#define platform_readb_relaxed __sn_readb_relaxed
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#define platform_readw_relaxed __sn_readw_relaxed
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#define platform_readl_relaxed __sn_readl_relaxed
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#define platform_readq_relaxed __sn_readq_relaxed
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#define platform_local_vector_to_irq sn_local_vector_to_irq
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#define platform_pci_get_legacy_mem sn_pci_get_legacy_mem
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#define platform_pci_legacy_read sn_pci_legacy_read
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#define platform_pci_legacy_write sn_pci_legacy_write
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#define platform_dma_init machvec_noop
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#define platform_dma_alloc_coherent sn_dma_alloc_coherent
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#define platform_dma_free_coherent sn_dma_free_coherent
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#define platform_dma_map_single sn_dma_map_single
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#define platform_dma_unmap_single sn_dma_unmap_single
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#define platform_dma_map_sg sn_dma_map_sg
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#define platform_dma_unmap_sg sn_dma_unmap_sg
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#define platform_dma_sync_single_for_cpu sn_dma_sync_single_for_cpu
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#define platform_dma_sync_sg_for_cpu sn_dma_sync_sg_for_cpu
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#define platform_dma_sync_single_for_device sn_dma_sync_single_for_device
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#define platform_dma_sync_sg_for_device sn_dma_sync_sg_for_device
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#define platform_dma_mapping_error sn_dma_mapping_error
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#define platform_dma_supported sn_dma_supported
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#define platform_migrate sn_migrate
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#include <asm/sn/io.h>
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#endif /* _ASM_IA64_MACHVEC_SN2_H */
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