e055d5bff3
Trying to compile a kerel for ARCH_CO285 fails with the following error: <-- snip --> ... CC arch/arm/mach-footbridge/dc21285.o /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c: In function 'dc21285_base_address': /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:54: error: 'PCICFG0_BASE' undeclared (first use in this function) /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:54: error: (Each undeclared identifier is reported only once /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:54: error: for each function it appears in.) /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:57: error: 'PCICFG1_BASE' undeclared (first use in this function) /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c: In function 'dc21285_scan_bus': /home/bunk/linux/kernel-2.6/git/linux-2.6/arch/arm/mach-footbridge/dc21285.c:286: error: implicit declaration of function 'pci_scan_bus' ... make[2]: *** [arch/arm/mach-footbridge/dc21285.o] Error 1 <-- snip --> This does not seem to be a recent breakage. The ARCH_CO285 support is old - kernel 2.2.0 contains first traces of it, an it seems to have been pretty complete in later 2.2 kernels. Since it seems to be completely dead code now this patch therefore removes it. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
106 lines
2.8 KiB
C
106 lines
2.8 KiB
C
/*
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* linux/include/asm-arm/arch-ebsa285/hardware.h
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*
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* Copyright (C) 1998-1999 Russell King.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This file contains the hardware definitions of the EBSA-285.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#include <asm/arch/memory.h>
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/* Virtual Physical Size
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* 0xff800000 0x40000000 1MB X-Bus
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* 0xff000000 0x7c000000 1MB PCI I/O space
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* 0xfe000000 0x42000000 1MB CSR
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* 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
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* 0xfc000000 0x79000000 1MB PCI IACK/special space
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* 0xfb000000 0x7a000000 16MB PCI Config type 1
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* 0xfa000000 0x7b000000 16MB PCI Config type 0
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* 0xf9000000 0x50000000 1MB Cache flush
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* 0xf0000000 0x80000000 16MB ISA memory
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*/
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#define XBUS_SIZE 0x00100000
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#define XBUS_BASE 0xff800000
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#define PCIO_SIZE 0x00100000
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#define PCIO_BASE 0xff000000
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#define ARMCSR_SIZE 0x00100000
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#define ARMCSR_BASE 0xfe000000
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#define WFLUSH_SIZE 0x00100000
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#define WFLUSH_BASE 0xfd000000
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#define PCIIACK_SIZE 0x00100000
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#define PCIIACK_BASE 0xfc000000
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#define PCICFG1_SIZE 0x01000000
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#define PCICFG1_BASE 0xfb000000
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#define PCICFG0_SIZE 0x01000000
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#define PCICFG0_BASE 0xfa000000
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#define PCIMEM_SIZE 0x01000000
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#define PCIMEM_BASE 0xf0000000
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#define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000))
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#define XBUS_LED_AMBER (1 << 0)
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#define XBUS_LED_GREEN (1 << 1)
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#define XBUS_LED_RED (1 << 2)
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#define XBUS_LED_TOGGLE (1 << 8)
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#define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000))
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#define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15)
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#define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4))
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#define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
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#define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
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#define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108)
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/* PIC irq control */
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#define PIC_LO 0x20
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#define PIC_MASK_LO 0x21
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#define PIC_HI 0xA0
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#define PIC_MASK_HI 0xA1
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/* GPIO pins */
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#define GPIO_CCLK 0x800
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#define GPIO_DSCLK 0x400
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#define GPIO_E2CLK 0x200
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#define GPIO_IOLOAD 0x100
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#define GPIO_RED_LED 0x080
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#define GPIO_WDTIMER 0x040
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#define GPIO_DATA 0x020
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#define GPIO_IOCLK 0x010
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#define GPIO_DONE 0x008
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#define GPIO_FAN 0x004
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#define GPIO_GREEN_LED 0x002
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#define GPIO_RESET 0x001
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/* CPLD pins */
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#define CPLD_DS_ENABLE 8
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#define CPLD_7111_DISABLE 4
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#define CPLD_UNMUTE 2
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#define CPLD_FLASH_WR_ENABLE 1
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#ifndef __ASSEMBLY__
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extern void gpio_modify_op(int mask, int set);
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extern void gpio_modify_io(int mask, int in);
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extern int gpio_read(void);
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extern void cpld_modify(int mask, int set);
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#endif
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#define pcibios_assign_all_busses() 1
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#define PCIBIOS_MIN_IO 0x1000
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#define PCIBIOS_MIN_MEM 0x81000000
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#endif
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