13dccb9e65
This merges the 32-bit and 64-bit implementations of pci_process_bridge_OF_ranges(). The new function is cleaner than both the old ones, and supports 64 bits ranges on ppc32 which is necessary for the 4xx port. It also adds some better (hopefully) output to the kernel log which should help diagnose problems and makes better use of existing OF parsing helpers (avoiding a few bugs of both implementations along the way). There are still a few unfortunate ifdef's but there is no way around these for now at least not until some other bits of the PCI code are made common. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
279 lines
8.5 KiB
C
279 lines
8.5 KiB
C
#ifndef _ASM_POWERPC_PCI_BRIDGE_H
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#define _ASM_POWERPC_PCI_BRIDGE_H
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#ifdef __KERNEL__
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/*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/pci.h>
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#include <linux/list.h>
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#include <linux/ioport.h>
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struct device_node;
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/*
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* Structure of a PCI controller (host bridge)
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*/
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struct pci_controller {
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struct pci_bus *bus;
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char is_dynamic;
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#ifdef CONFIG_PPC64
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int node;
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#endif
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struct device_node *dn;
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struct list_head list_node;
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struct device *parent;
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int first_busno;
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int last_busno;
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#ifndef CONFIG_PPC64
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int self_busno;
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#endif
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void __iomem *io_base_virt;
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#ifdef CONFIG_PPC64
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void *io_base_alloc;
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#endif
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resource_size_t io_base_phys;
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#ifndef CONFIG_PPC64
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resource_size_t pci_io_size;
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#endif
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/* Some machines (PReP) have a non 1:1 mapping of
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* the PCI memory space in the CPU bus space
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*/
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resource_size_t pci_mem_offset;
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#ifdef CONFIG_PPC64
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unsigned long pci_io_size;
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#endif
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struct pci_ops *ops;
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volatile unsigned int __iomem *cfg_addr;
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volatile void __iomem *cfg_data;
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#ifndef CONFIG_PPC64
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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* EXT_REG - provides access to PCI-e extended registers
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* SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
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* on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
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* to determine which bus number to match on when generating type0
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* config cycles
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* NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
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* hanging if we don't have link and try to do config cycles to
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* anything but the PHB. Only allow talking to the PHB if this is
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* set.
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* BIG_ENDIAN - cfg_addr is a big endian register
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*/
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#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
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#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
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#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004
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#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
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u32 indirect_type;
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#endif /* !CONFIG_PPC64 */
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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struct resource io_resource;
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struct resource mem_resources[3];
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int global_number; /* PCI domain number */
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#ifdef CONFIG_PPC64
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unsigned long buid;
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unsigned long dma_window_base_cur;
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unsigned long dma_window_size;
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void *private_data;
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#endif /* CONFIG_PPC64 */
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};
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#ifndef CONFIG_PPC64
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static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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static inline int isa_vaddr_is_ioport(void __iomem *address)
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{
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/* No specific ISA handling on ppc32 at this stage, it
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* all goes through PCI
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*/
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return 0;
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}
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/* These are used for config access before all the PCI probing
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has been done. */
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extern int early_read_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 *val);
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extern int early_read_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 *val);
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extern int early_read_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 *val);
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extern int early_write_config_byte(struct pci_controller *hose, int bus,
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int dev_fn, int where, u8 val);
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extern int early_write_config_word(struct pci_controller *hose, int bus,
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int dev_fn, int where, u16 val);
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extern int early_write_config_dword(struct pci_controller *hose, int bus,
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int dev_fn, int where, u32 val);
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extern int early_find_capability(struct pci_controller *hose, int bus,
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int dev_fn, int cap);
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extern void setup_indirect_pci(struct pci_controller* hose,
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resource_size_t cfg_addr,
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resource_size_t cfg_data, u32 flags);
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extern void setup_grackle(struct pci_controller *hose);
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extern void __init update_bridge_resource(struct pci_dev *dev,
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struct resource *res);
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#else /* CONFIG_PPC64 */
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/*
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* PCI stuff, for nodes representing PCI devices, pointed to
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* by device_node->data.
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*/
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struct iommu_table;
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struct pci_dn {
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int busno; /* pci bus number */
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int bussubno; /* pci subordinate bus number */
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int devfn; /* pci device and function number */
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int class_code; /* pci device class */
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struct pci_controller *phb; /* for pci devices */
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struct iommu_table *iommu_table; /* for phb's or bridges */
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struct pci_dev *pcidev; /* back-pointer to the pci device */
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struct device_node *node; /* back-pointer to the device_node */
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int pci_ext_config_space; /* for pci devices */
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#ifdef CONFIG_EEH
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int eeh_mode; /* See eeh.h for possible EEH_MODEs */
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int eeh_config_addr;
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int eeh_pe_config_addr; /* new-style partition endpoint address */
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int eeh_check_count; /* # times driver ignored error */
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int eeh_freeze_count; /* # times this device froze up. */
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int eeh_false_positives; /* # times this device reported #ff's */
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u32 config_space[16]; /* saved PCI config space */
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#endif
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};
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/* Get the pointer to a device_node's pci_dn */
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#define PCI_DN(dn) ((struct pci_dn *) (dn)->data)
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extern struct device_node *fetch_dev_dn(struct pci_dev *dev);
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/* Get a device_node from a pci_dev. This code must be fast except
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* in the case where the sysdata is incorrect and needs to be fixed
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* up (this will only happen once).
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* In this case the sysdata will have been inherited from a PCI host
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* bridge or a PCI-PCI bridge further up the tree, so it will point
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* to a valid struct pci_dn, just not the one we want.
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*/
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static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
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{
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struct device_node *dn = dev->sysdata;
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struct pci_dn *pdn = dn->data;
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if (pdn && pdn->devfn == dev->devfn && pdn->busno == dev->bus->number)
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return dn; /* fast path. sysdata is good */
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return fetch_dev_dn(dev);
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}
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static inline int pci_device_from_OF_node(struct device_node *np,
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u8 *bus, u8 *devfn)
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{
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if (!PCI_DN(np))
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return -ENODEV;
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*bus = PCI_DN(np)->busno;
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*devfn = PCI_DN(np)->devfn;
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return 0;
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}
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static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
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{
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if (bus->self)
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return pci_device_to_OF_node(bus->self);
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else
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return bus->sysdata; /* Must be root bus (PHB) */
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}
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/** Find the bus corresponding to the indicated device node */
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extern struct pci_bus *pcibios_find_pci_bus(struct device_node *dn);
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/** Remove all of the PCI devices under this bus */
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extern void pcibios_remove_pci_devices(struct pci_bus *bus);
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/** Discover new pci devices under this bus, and add them */
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extern void pcibios_add_pci_devices(struct pci_bus *bus);
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extern void pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus);
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extern int pcibios_remove_root_bus(struct pci_controller *phb);
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static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
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{
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struct device_node *busdn = bus->sysdata;
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BUG_ON(busdn == NULL);
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return PCI_DN(busdn)->phb;
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}
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extern void isa_bridge_find_early(struct pci_controller *hose);
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static inline int isa_vaddr_is_ioport(void __iomem *address)
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{
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/* Check if address hits the reserved legacy IO range */
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unsigned long ea = (unsigned long)address;
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return ea >= ISA_IO_BASE && ea < ISA_IO_END;
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}
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extern int pcibios_unmap_io_space(struct pci_bus *bus);
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extern int pcibios_map_io_space(struct pci_bus *bus);
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/* Return values for ppc_md.pci_probe_mode function */
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#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
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#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
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#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
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#ifdef CONFIG_NUMA
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#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
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#else
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#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
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#endif
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#endif /* CONFIG_PPC64 */
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/* Get the PCI host controller for an OF device */
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extern struct pci_controller *pci_find_hose_for_OF_device(
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struct device_node* node);
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/* Fill up host controller resources from the OF node */
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extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
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struct device_node *dev, int primary);
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/* Allocate & free a PCI host bridge structure */
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extern struct pci_controller *pcibios_alloc_controller(struct device_node *dev);
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extern void pcibios_free_controller(struct pci_controller *phb);
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#ifdef CONFIG_PCI
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extern unsigned long pci_address_to_pio(phys_addr_t address);
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extern int pcibios_vaddr_is_ioport(void __iomem *address);
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#else
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static inline unsigned long pci_address_to_pio(phys_addr_t address)
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{
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return (unsigned long)-1;
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}
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static inline int pcibios_vaddr_is_ioport(void __iomem *address)
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{
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return 0;
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}
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#endif /* CONFIG_PCI */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_PCI_BRIDGE_H */
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