687 lines
28 KiB
Plaintext
687 lines
28 KiB
Plaintext
// THIS FILE IS INCLUDED to South Bridge device scope
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//*************************************************************************
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//*************************************************************************
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//** **
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//** (C)Copyright 1985-2013, American Megatrends, Inc. **
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//** **
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//** All Rights Reserved. **
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//** **
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//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
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//** **
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//** Phone: (770)-246-8600 **
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//** **
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//*************************************************************************
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//*************************************************************************
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//<AMI_FHDR_START>
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//
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// Name: <IT8728FDEV.ASL>
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//
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// Description: Define ACPI method or namespce For Super IO.
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//
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//<AMI_FHDR_END>
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//*************************************************************************
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//Scope(\_SB.PCI0.SBRG) {
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//-----------------------------------------------------------------------
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// SET OF COMMON DATA/CONTROL METHODS USED FOR ALL LDN BASED SIO DEVICES
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//-----------------------------------------------------------------------
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// LIST of objects defined in this file:
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// SIO specific: SIOR - Device node (_HID=0c02, UID=SPIO), SIO index/DAta IO access & SIO GPIO address space if available
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// SIO specific: DCAT - Table correspondence the LDNs to Device order in Routing Table.
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// SIO specific: ENFG & EXFG - Control methods to Enter and Exit configuration mode. ENFG & EXFG correspondingly
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// SIO specific: LPTM - current parralel port mode
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// SIO specific: UHID - PnP ID for given Serial port
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// SIO specific: SIOS - SIO Chipset specific code called from _PTS
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// SIO specific: SIOW - SIO Chipset specific code called from _WAK
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// SIO specific: SIOH - SIO event handler, to be called from correspondent _Lxx method
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// SIO specific: PowerResources & _PR0 object to control Power management for FDC, LPT, UART1,2.
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//
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// Generic :OpRegion & common Fields to access SIO configuration space
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// Generic :CGLD - Convert Device category to LDN
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// Generic :DSTA - Get device status according to ACTR register in LD IO space
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// Generic :DCNT - Enable/Disable Decoding of Device resources, Route/Release resources to LPC bus
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// Generic :DCRS - Returns Byte stream of device's Current resources
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// Generic :DSRS - Configures new Resources to be decoded by a Device
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// Device node:Motherboard resources
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// SIO index/DAta IO access & SIO GPIO address space if available
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//====================================================================================
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//Following commented line will be included in PciTree.asl
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//Device(SIO1) {
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// Name(_HID, EISAID("PNP0C02")) // System board resources device node ID
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// Name(_UID,0x111) // Unique ID. First IO use 0x111, Second IO use 0x222 ...
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//====================================================================================
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Name(CRS, ResourceTemplate(){
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IO(Decode16, 0, 0, 0, 0, IOI) // Index/Data Io address
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IO(Decode16, 0, 0, 0, 0, IO1) // GP IO space
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IO(Decode16, 0, 0, 0, 0, IO2) // PME IO space
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IO(Decode16, 0, 0, 0, 0, IO3) // HWM IO space
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}) // end CRS
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Method (_CRS, 0){
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// Reserve Super I/O Configuration Port
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// 0x0 to 0xF0 already reserved
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// 0x3F0 - 0x3F1 are reserved in FDC
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If(LAnd(LLess(SP1O, 0x3F0), LGreater(SP1O, 0x0F0))){
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CreateWordField(CRS, ^IOI._MIN, GPI0)
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CreateWordField(CRS, ^IOI._MAX, GPI1)
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CreateByteField(CRS, ^IOI._LEN, GPIL)
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Store(SP1O, GPI0) //Index/Data Base address
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Store(SP1O, GPI1)
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Store(0x02, GPIL) //IO range
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}
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// Reserve SIO GP IO space
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If(IO1B){
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CreateWordField(CRS, ^IO1._MIN, GP10)
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CreateWordField(CRS, ^IO1._MAX, GP11)
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CreateByteField(CRS, ^IO1._LEN, GPL1)
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Store(IO1B, GP10) //GP IO base address
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Store(IO1B, GP11)
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Store(IO1L, GPL1) //IO range
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}
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// Reserve SIO PME IO space
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If(IO2B){
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CreateWordField(CRS, ^IO2._MIN, GP20)
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CreateWordField(CRS, ^IO2._MAX, GP21)
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CreateByteField(CRS, ^IO2._LEN, GPL2)
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Store(IO2B, GP20) //PME IO base address
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Store(IO2B, GP21)
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Store(IO2L, GPL2) //IO range
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}
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// Reserve SIO HWM IO space
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If(IO3B){
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CreateWordField(CRS, ^IO3._MIN, GP30)
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CreateWordField(CRS, ^IO3._MAX, GP31)
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CreateByteField(CRS, ^IO3._LEN, GPL3)
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Store(IO3B, GP30) //HWM IO base address
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Store(IO3B, GP31)
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Store(IO3L, GPL3) //IO range
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}
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Return(CRS)
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} //End _CRS
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//---------------------------------------------------------------------
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// Table correspondence the LDNs to Device order in Routing Table
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// Device type selection is achieved by picking the value from DCAT Package by Offset = LDN
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//----------------------------------------------------------------------
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// Elements in the package contain LDN numbers for each category of devices.
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// Default value 0xFF -> no device present.
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// Make sure number of elements not less or equal to largest LDN
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Name (DCAT, Package(0x15){
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// AMI_TODO: fill the table with the present LDN
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// LDN number, 0xFF if device not present
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// We keep category 0x00~0x0F as SIO_DEV_STATUS layout in AmiGenericSio.h to Update IOST
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0x01, // 0x00 - Serial A (SP1)
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0x02, // 01 - Serial B (SP2)
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0x03, // 02 - LPT
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0x00, // 03 - FDD
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0xFF, // 04 - SB16 Audio
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0xFF, // 05 - MIDI
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0xFF, // 06 - MSS Audio
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0xFF, // 07 - AdLib sound (FM synth)
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0xFF, // 08 - Game port #1
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0xFF, // 09 - Game port #2
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0x05, // 0A - KBC 60 & 64
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0xFF, // 0B - EC 62 & 66
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0xFF, // 0C - Reserved
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0xFF, // 0D - Reserved
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0x06, // 0E - PS/2 Mouse
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0xFF, // 0F - Reserved
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//----add your other device,if no,please cut and modify Package number----------//
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0x0A, // 10 - CIR
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0xFF, // 11 - Serial C (SP3)
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0xFF, // 12 - Serial D (SP4)
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0xFF, // 13 - Serial E (SP5)
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0xFF, // 14 - Serial F (SP6)
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})
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//---------------------------------------------------------------------
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// Mutex object to sincronize the access to Logical devices
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//---------------------------------------------------------------------
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Mutex(MUT0, 0)
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//---------------------------------------------------------------------
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// Enter Config Mode, Select LDN
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// Arg0 : Logical Device number
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//---------------------------------------------------------------------
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Method(ENFG, 1) {
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Acquire(MUT0, 0xFFF)
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//AMI_TODO: enter config mode and Select LDN.
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Store(0x87, INDX)
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Store(0x01, INDX)
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Store(0x55, INDX)
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If(LEqual(SP1O, 0x2E)){
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Store(0x55, INDX)
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}Else{
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Store(0xAA, INDX)
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}
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Store(Arg0, LDN) //Select LDN
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}
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//---------------------------------------------------------------------
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// Exit Config Mode
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//---------------------------------------------------------------------
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Method(EXFG, 0) {
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//AMI_TODO: exit config mode
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Store(0x02, INDX)
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Store(0x02, DATA)
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Release(MUT0)
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}
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//---------------------------------------------------------------------
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// Return current LPT mode : 0-plain LPT, non Zero-ECP mode
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// Arg0 : Device LDN
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//---------------------------------------------------------------------
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Method(LPTM, 1){
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ENFG(CGLD(Arg0)) //Enter Config Mode, Select LDN
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//AMI_TODO: if it's ECP mode .
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And(OPT0, 0x02, Local0) //ECP Mode?
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EXFG() //Exit Config Mode
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Return(Local0)
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}
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//-------------------------------------------------------------------------
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// !!! BELOW ARE GENERIC SIO CONTROL METHODS. DO NOT REQUIRE MODIFICATIONS
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//-------------------------------------------------------------------------
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//<AMI_THDR_START>
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//------------------------------------------------------------------------
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// Name: IOID
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//
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// Type: OperationRegion
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//
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// Description: Operation Region to point to SuperIO configuration space
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//
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// Notes: OpeRegion address is defined by 'SP1O' global name.
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// 'SPIO' is a field isnside AML_Exchange data area defined in SDL file.
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//
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// Referrals: BIOS, AMLDATA
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//
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//-------------------------------------------------------------------------
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//<AMI_THDR_END>
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//---------------------------------------------------------------------
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// Set of Field names to be used to access SIO configuration space.
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//---------------------------------------------------------------------
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OperationRegion(IOID, // Name of Operation Region for SuperIO device
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SystemIO, // Type of address space
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SP1O, // Offset to start of region
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2) // Size of region in bytes
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// End of Operation Region
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Field(IOID, ByteAcc, NoLock,Preserve){
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INDX, 8, // Field named INDX is 8 bit wide
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DATA, 8 // Field DATA is 8 bit wide
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}
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//---------------------------------------------------------------------
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// Set of Field names to be used to access SIO configuration space.
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//---------------------------------------------------------------------
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IndexField(INDX, DATA, ByteAcc, NoLock, Preserve){
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Offset(0x07),
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LDN, 8, //Logical Device Number
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Offset(0x21),
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SCF1, 8, //Set SCF1
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Offset(0x22),
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SCF2, 8, //Set SCF2
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Offset(0x23),
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SCF3, 8, //Set SCF3
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Offset(0x24),
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SCF4, 8, //Set SCF4
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Offset(0x25),
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SCF5, 8, //Set SCF5
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Offset(0x26),
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SCF6, 8, //Set SCF6
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Offset(0x29),
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CKCF, 8, //Multi Function Select 1 Register
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Offset(0x2D),
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CR2D, 8, //kbc/mouse wakeup register
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Offset(0x30),
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ACTR, 8, //Activate register
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Offset(0x60),
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IOAH, 8, //Base I/O High addr
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IOAL, 8, //Base I/O Low addr
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IOH2, 8, //Base2 I/O High addr
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IOL2, 8, //Base2 I/O Low addr
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Offset(0x70),
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INTR, 4, //IRQ
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INTT, 4, //IRQ type
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Offset(0x74),
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DMCH, 8, //DMA channel
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Offset(0xE0),
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RGE0, 8, //Option Register E0
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RGE1, 8, //Option Register E1
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RGE2, 8, //Option Register E2
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RGE3, 8, //Option Register E3
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RGE4, 8, //Option Register E4
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RGE5, 8, //Option Register E5
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RGE6, 8, //Option Register E6
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RGE7, 8, //Option Register E7
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RGE8, 8, //Option Register E8
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RGE9, 8, //Option Register E9
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Offset(0xF0),
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OPT0, 8, //Option register 0xF0
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OPT1, 8, //Option register 0xF1
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OPT2, 8, //Option register 0xF2
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OPT3, 8, //Option register 0xF3
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OPT4, 8, //Option register 0xF4
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OPT5, 8, //Option register 0xF5
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OPT6, 8, //Option register 0xF6
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OPT7, 8, //Option register 0xF7
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OPT8, 8, //Option register 0xF8
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OPT9, 8, //Option register 0xF9
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} //End of indexed field
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//-----------------------------------------------------------------------
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// SIO PME block IO registers
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//-----------------------------------------------------------------------
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OperationRegion (RNTR, SystemIO, IO2B, IO2L)
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Field (RNTR, ByteAcc, NoLock, Preserve){
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PMES, 8, //+0 Global PME Status
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Offset(0x04),
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PMEE, 1, //+4 Global PME Enable
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,7,
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Offset(0x08),
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PMS3, 8, //GP2X Wake Status
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PMS2, 8, //GP1X Wake Status
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PMS1, 8, //PME Wake Status
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,8,
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PME3, 8, //GP2X Wake Enable
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PME2, 8, //GP1X Wake Enable
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PME1, 8, //PME Wake Enable
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} //end of indexed field
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// Make sure referred IO devices included in SIO ASL file list ($SIO_ASLS)
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// PS2 port swap feature is not covered in this code
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// Keyboard 2nd Level wake up control method
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// Method(PS2K._PSW, 1){
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// Store(Arg0, KBFG)
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// }
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// Mouse 2nd Level wake up control method
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// Method(PS2M._PSW, 1){
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// Store(Arg0, MSFG)
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// }
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// UART1 RI 2nd Level wake up control method
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// Method(UAR1._PSW, 1){
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// Store(Arg0, UR1F)
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// }
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// UART2 RI 2nd Level wake up control method
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// Method(UAR2._PSW, 1){
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// Store(Arg0, UR2F)
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// }
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//<AMI_PHDR_START>
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//------------------------------------------------------------------------
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// Procedure: CGLD
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// Description: Convert Device Category to Device's LDN
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// Input: Arg0 : Device category #
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// Output: LDN
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//-------------------------------------------------------------------------
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//<AMI_PHDR_END>
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Method(CGLD, 1) {
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Return(DeRefOf(Index(DCAT, Arg0))) // Return LDN
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}
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//<AMI_PHDR_START>
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//------------------------------------------------------------------------
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// Procedure: DSTA
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// Description: GET SIO DEVICE STATUS according to ACTR/IOST(category0x00~0x0F) return values
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// GET SIO DEVICE STATUS according to ACTR/IOAH+IOAL/IOH2+IOL2(category>0x0F)
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// Input: Arg0 : Device category #
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// Output: Device Status
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//-------------------------------------------------------------------------
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//<AMI_PHDR_END>
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Method(DSTA, 1) {
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// IO Device presence status is determined during first _STA invocation.
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// If "Activate" bit is set during first _STA invocation, IO device
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// present status is stored into IOST global variable.
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// IOST global variable contains the bit mask of all enabled Io devices.
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ENFG(CGLD(Arg0)) //Enter Config Mode, Select LDN
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Store(ACTR, Local0) //Local0=ACTR
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Or(ShiftLeft(IOAH, 8),IOAL,Local1) //Local1=Base 1
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EXFG() //Exit Config Mode
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// LDN's not decoded, Device not present.
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If(LEqual(Local0, 0xFF)) {Return(0x0)}
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//Assume register(ACTR) bit0 is "Active" bit.
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//AMI_TODO: If register(ACTR) non-bit0 is "Active" bit, change below code.
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And(Local0, 1, Local0) //Leave only "Activate" bit
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// IOST only have 16 bits,IOST is for category 0x00~0x0F device
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If(LLess(Arg0,0x10)) {Or(IOST, ShiftLeft(Local0, Arg0), IOST)}
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// Update IO device status in IOST according to the category#
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// Note. Once device is detected its status bit cannot be removed
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If(Local0){
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Return(0x0F) // Device present & Active
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}
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Else{
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If(LLess(Arg0,0x10)){//by IOST check
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// Check if IO device detected in Local0(IOST) bit mask
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If(And(ShiftLeft(1, Arg0), IOST)){ Return(0x0D)} // Device Detected & Not Active
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// IO bit not set in Local0: device is disabled during first
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// _STA(GSTA) invocationor disabled in BIOS Setup.
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Else{ Return(0x00)} // Device not present
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}
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Else{//by Base1 & Base2 check
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If(Local1) { Return(0x0D)} // Device Detected & Not Active
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Return(0x00) // Device not present
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}
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}
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} // End Of DSTA
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//<AMI_PHDR_START>
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//------------------------------------------------------------------------
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// Procedure: DCNT
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// Description: Enable/Disable Decoding of Device resources, Route/Release
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// I/O & DMA Resources From, To EIO/LPC Bus
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// Input: Arg0 : Device catagory #
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// Arg1 : 0/1 Disable/Enable resource decoding
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// Output:Nothing
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//-------------------------------------------------------------------------
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//<AMI_PHDR_END>
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//RayWu, MODIFY 2014/07/28 >>
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// Method(DCNT, 2) {
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//
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// ENFG(CGLD(Arg0)) //Enter Config Mode, Select LDN
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//
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// // Route/Release DMA channel from/to being ISA/PCI mode
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// // Note. DMA channel 0 is currently not decoded, although it can be
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// // used on some of SIO chipsets.
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// If(LAnd(LLess(DMCH,4), LNotEqual(And(DMCH, 3, Local1),0))){
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// rDMA(Arg0, Arg1, Increment(Local1))
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// }
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//
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// Store(Arg1, ACTR) // Update Activate Register
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// ShiftLeft(IOAH, 8, local1) // Get IO Base address
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// Or(IOAL, Local1, Local1)
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//
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// // Route/Release I/O resources from/to EIO/LPC Bus
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// // Arg0 Device Category
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// // Arg1 0/1 Disable/Enable resource decoding
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// // Arg2 Port to Route/Release
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// // Arg3 Port SIZE to Route
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// RRIO(Arg0, Arg1, Local1, 0x08)
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//
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// EXFG() // Exit Config Mode
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// } // End DCNT
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Method(DCNT, 2) {
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ENFG(CGLD(Arg0)) //Enter Config Mode, Select LDN
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Store(Arg1, ACTR) // Update Activate Register
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EXFG() // Exit Config Mode
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}
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//RayWu, MODIFY 2014/07/28 <<
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//<AMI_THDR_START>
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//------------------------------------------------------------------------
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// Name: CRS1,CRS2,CRS3
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//
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// Type: ResourceTemplate
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//
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// Description: Current Resources Buffer for Generic SIO devices
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//
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// Notes: Note. DMA channel 0 is currently decoded as reserved,
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// although, it can be used on some of SIO chipsets.
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// Add DMA0 to _PRS if it is used
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// Generic Resourse template for FDC, COMx, LPT and ECP Current Resource Settings
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// (to be initialized and returned by _CRS)
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//-------------------------------------------------------------------------
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//<AMI_THDR_END>
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// CRS buffer with all kinds of resources
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Name(CRS1, ResourceTemplate(){
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IO(Decode16, 0, 0, 1, 0, IO01)
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IRQNoFlags(IRQ1) {}
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DMA(Compatibility, NotBusMaster, Transfer8, DMA1) {}
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})
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CreateWordField(CRS1, IRQ1._INT, IRQM) //IRQ mask 0x1
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CreateByteField(CRS1, DMA1._DMA, DMAM) //DMA 0x4
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CreateWordField(CRS1, IO01._MIN, IO11) //Range 1 Min Base Word 0x8
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CreateWordField(CRS1, IO01._MAX, IO12) //Range 1 Max Base Word 0xa
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CreateByteField(CRS1, IO01._LEN, LEN1) //Length 1 0xd
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// Extended CRS buffer with 2 IO ranges
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Name(CRS2, ResourceTemplate(){
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IO(Decode16, 0, 0, 1, 0, IO02)
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IO(Decode16, 0, 0, 1, 0, IO03)
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IRQNoFlags(IRQ2) {}
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DMA(Compatibility, NotBusMaster, Transfer8, DMA2) {}
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})
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CreateWordField(CRS2, IRQ2._INT, IRQE) //IRQ mask 0x1
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CreateByteField(CRS2, DMA2._DMA, DMAE) //DMA 0x4
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CreateWordField(CRS2, IO02._MIN, IO21) //Range 1 Min Base Word 0x8
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CreateWordField(CRS2, IO02._MAX, IO22) //Range 1 Max Base Word 0xa
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CreateByteField(CRS2, IO02._LEN, LEN2) //Length 1 0xd
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CreateWordField(CRS2, IO03._MIN, IO31) //Range 2 Min Base Word 0x10
|
|
CreateWordField(CRS2, IO03._MAX, IO32) //Range 2 Max Base Word 0x12
|
|
CreateByteField(CRS2, IO03._LEN, LEN3) //Length 2 0x15
|
|
|
|
//<AMI_PHDR_START>
|
|
//------------------------------------------------------------------------
|
|
// Procedure: DCRS
|
|
// Description: Get FDC, LPT, ECP, UART, IRDA resources (_CRS)
|
|
// Returns Byte stream of Current resources. May contain Resources such:
|
|
// 1 IRQ resource
|
|
// 1 DMA resource
|
|
// 1 IO Port
|
|
// Input: Arg0 : Device catagory #
|
|
// Arg1 : Use/No-Use DMA
|
|
// Output: _CRS Resource Buffer
|
|
//-------------------------------------------------------------------------
|
|
//<AMI_PHDR_END>
|
|
Method(DCRS, 2) {
|
|
ENFG(CGLD(Arg0)) //Enter Config Mode, Select LDN
|
|
|
|
// Write Current Settings into Buffer for 1st IO Descriptor
|
|
ShiftLeft(IOAH, 8, IO11) //Get IO Base MSB
|
|
Or(IOAL, IO11, IO11) //Get IO Base LSB
|
|
Store(IO11, IO12) //Set Max Base Word
|
|
|
|
//Store(0x08, LEN1)
|
|
// adjust base/aligment size if base ports are 0x3bc/0x7bc
|
|
//If(LEqual(And(IO1L,0xff), 0xbc))
|
|
//If(And(IO11, 0x04)){
|
|
// Store(0x04, LEN1)
|
|
//}
|
|
Store(0x08, LEN1)
|
|
|
|
// Write Current Settings into IRQ descriptor
|
|
If(INTR){
|
|
ShiftLeft(1, INTR, IRQM)
|
|
}
|
|
Else{
|
|
Store(0, IRQM) // No IRQ used
|
|
}
|
|
// Write Current Settings into DMA descriptor
|
|
// Note. DMA channel 0 is currently decoded as reserved,
|
|
// although, it can be used on some of SIO chipsets.
|
|
//If(Or(LGreater(DMCH,3), LEqual(And(DMCH, 3, Local1),0))){
|
|
If(LOr(LGreater(DMCH,3), LEqual(Arg1, 0))){
|
|
Store(0, DMAM) // No DMA
|
|
}
|
|
Else{
|
|
And(DMCH, 3, Local1)
|
|
ShiftLeft(1, Local1, DMAM)
|
|
}
|
|
EXFG() //Exit Config Mode
|
|
Return(CRS1) //Return Current Resources
|
|
}
|
|
|
|
//<AMI_PHDR_START>
|
|
//------------------------------------------------------------------------
|
|
// Procedure: DCR2
|
|
// Description: Get FDC, LPT, ECP, UART, IRDA resources (_CRS)
|
|
// Returns Byte stream of Current resources. May contain Resources such:
|
|
// 1 IRQ resource
|
|
// 1 DMA resource
|
|
// 2 IO Port
|
|
// Input: Arg0 : Device catagory #
|
|
// Arg1 : Use/No-Use DMA
|
|
// Output: _CRS Resource Buffer
|
|
//-------------------------------------------------------------------------
|
|
//<AMI_PHDR_END>
|
|
Method(DCR2, 2) {
|
|
ENFG(CGLD(Arg0)) //Enter Config Mode, Select LDN
|
|
|
|
// Write Current Settings into Buffer for 1st IO Descriptor
|
|
ShiftLeft(IOAH, 8, IO21) //Get IO Base MSB
|
|
Or(IOAL, IO21, IO21) //Get IO Base LSB
|
|
Store(IO21, IO22) //Set Max Base Word
|
|
Store(0x08, LEN2)
|
|
|
|
// Write Current Settings into Buffer for 2nd IO Descriptor
|
|
ShiftLeft(IOH2, 8, IO31) //Get IO Base MSB
|
|
Or(IOL2, IO31, IO31) //Get IO Base LSB
|
|
Store(IO31, IO32) //Set Max Base Word
|
|
Store(0x08, LEN3)
|
|
|
|
// Write Current Settings into IRQ descriptor
|
|
If(INTR){
|
|
ShiftLeft(1, INTR, IRQE)
|
|
}
|
|
Else{
|
|
Store(0, IRQE) // No IRQ used
|
|
}
|
|
|
|
// Write Current Settings into DMA descriptor
|
|
// Note. DMA channel 0 is currently decoded as reserved,
|
|
// although, it can be used on some of SIO chipsets.
|
|
//If(Or(LGreater(DMCH,3), LEqual(And(DMCH, 3, Local1),0))){
|
|
If(LOr(LGreater(DMCH,3), LEqual(Arg1, 0))){
|
|
Store(0, DMAE) // No DMA
|
|
} Else {
|
|
And(DMCH, 3, Local1)
|
|
ShiftLeft(1, Local1, DMAE)
|
|
}
|
|
|
|
EXFG() //Exit Config Mode
|
|
Return(CRS2) //Return Current Resources
|
|
}
|
|
|
|
//<AMI_PHDR_START>
|
|
//------------------------------------------------------------------------
|
|
// Procedure: DSRS
|
|
// Description: Set FDC, LPT, ECP, UART, IRDA resources (_SRS)
|
|
// Control method can be used for configuring devices with following resource order:
|
|
// 1 IRQ resource
|
|
// 1 DMA resource
|
|
// 1 IO Port
|
|
// Input: Arg0 : PnP Resource String to set
|
|
// Arg1 : Device catagory #
|
|
// Output: Nothing
|
|
//-------------------------------------------------------------------------
|
|
//<AMI_PHDR_END>
|
|
Method(DSRS, 2) {
|
|
If(And(LEqual(Arg1, 0x02),LPTM(Arg1) ) ) { //LPT logical device? Extended LPT mode ?
|
|
DSR2(Arg0, Arg1)
|
|
} Else {
|
|
//Set resource for other devices from CRS1, or just for Parallel Port LPT Mode
|
|
CreateWordField(Arg0, ^IRQ1._INT, IRQM) //IRQ mask 0x1
|
|
CreateByteField(Arg0, ^DMA1._DMA, DMAM) //DMA 0x4
|
|
CreateWordField(Arg0, ^IO01._MIN, IO11) //Range 1 Min Base Word 0x8
|
|
|
|
ENFG(CGLD(Arg1)) //Enter Config Mode, Select LDN
|
|
|
|
// Set Base IO Address
|
|
And(IO11, 0xFF, IOAL) //Set IO Base LSB
|
|
ShiftRight(IO11, 0x8, IOAH) //Set IO Base MSB
|
|
|
|
// Set IRQ
|
|
If(IRQM){
|
|
FindSetRightBit(IRQM, Local0)
|
|
Subtract(Local0, 1, INTR)
|
|
}Else{
|
|
Store(0, INTR) //No IRQ used
|
|
}
|
|
// Set DMA
|
|
If(DMAM){
|
|
FindSetRightBit(DMAM, Local0)
|
|
Subtract(Local0, 1, DMCH)
|
|
}Else{
|
|
Store(4, DMCH) //No DMA
|
|
}
|
|
EXFG() //Exit Config Mode
|
|
|
|
// Enable ACTR
|
|
DCNT(Arg1, 1) //Enable Device (Routing)
|
|
|
|
Store(Arg1, Local2)
|
|
If (LGreater(Local2, 0)){Subtract(Local2, 1, Local2)}
|
|
}//Else end
|
|
}//Method DSRS end
|
|
|
|
//<AMI_PHDR_START>
|
|
//------------------------------------------------------------------------
|
|
// Procedure: DSR2
|
|
// Description: Set FDC, LPT, ECP, UART, IRDA resources (_SRS)
|
|
// Control method can be used for configuring devices with following resource order:
|
|
// 1 IRQ resource
|
|
// 1 DMA resource
|
|
// 2 IO Port
|
|
// Input: Arg0 : PnP Resource String to set
|
|
// Arg1 : Device catagory #
|
|
// Output: Nothing
|
|
//-------------------------------------------------------------------------
|
|
//<AMI_PHDR_END>
|
|
Method(DSR2, 2) {
|
|
CreateWordField(Arg0, ^IRQ2._INT, IRQE) //IRQ mask 0x1
|
|
CreateByteField(Arg0, ^DMA2._DMA, DMAE) //DMA 0x4
|
|
CreateWordField(Arg0, ^IO02._MIN, IO21) //Range 1 Min Base Word 0x8
|
|
CreateWordField(Arg0, ^IO03._MIN, IO31) //Range 1 Min Base Word 0x8
|
|
|
|
ENFG(CGLD(Arg1)) //Enter Config Mode, Select LDN
|
|
|
|
// Set Base IO Address
|
|
And(IO21, 0xFF, IOAL) //Set IO1 Base LSB
|
|
ShiftRight(IO21, 0x8, IOAH) //Set IO1 Base MSB
|
|
|
|
And(IO31, 0xFF, IOL2) //Set IO2 Base LSB
|
|
ShiftRight(IO31, 0x8, IOH2) //Set IO2 Base MSB
|
|
|
|
// Set IRQ
|
|
If(IRQE){
|
|
FindSetRightBit(IRQE, Local0)
|
|
Subtract(Local0, 1, INTR)
|
|
}Else{
|
|
Store(0, INTR) //No IRQ used
|
|
}
|
|
|
|
// Set DMA
|
|
If(DMAE){
|
|
FindSetRightBit(DMAE, Local0)
|
|
Subtract(Local0, 1, DMCH)
|
|
}Else{
|
|
Store(4, DMCH) //No DMA
|
|
}
|
|
|
|
EXFG() //Exit Config Mode
|
|
|
|
// Enable ACTR
|
|
DCNT(Arg1, 1) //Enable Device (Routing)
|
|
|
|
Store(Arg1, Local2)
|
|
If (LGreater(Local2, 0)){Subtract(Local2, 1, Local2)}
|
|
}
|
|
|
|
//====================================================================================
|
|
//Following commented line will be included in PciTree.asl
|
|
//} // End of SIO1
|
|
//====================================================================================
|
|
//**********************************************************************
|
|
//**********************************************************************
|
|
//** **
|
|
//** (C)Copyright 1985-2013, American Megatrends, Inc. **
|
|
//** **
|
|
//** All Rights Reserved. **
|
|
//** **
|
|
//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
|
|
//** **
|
|
//** Phone: (770)-246-8600 **
|
|
//** **
|
|
//**********************************************************************
|
|
//**********************************************************************
|
|
// THIS FILE IS INCLUDED to South Bridge device scope
|