486 lines
17 KiB
C
486 lines
17 KiB
C
//**********************************************************************
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//**********************************************************************
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//** **
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//** (C)Copyright 1985-2013, American Megatrends, Inc. **
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//** **
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//** All Rights Reserved. **
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//** **
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//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
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//** **
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//** Phone: (770)-246-8600 **
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//** **
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//**********************************************************************
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//**********************************************************************
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//**********************************************************************
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//<AMI_FHDR_START>
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//
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// Name: <F81866PeiInit.c>
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//
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// Description: Porting for PEI phase.Just for necessary devices porting.
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//
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//<AMI_FHDR_END>
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//**********************************************************************
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//----------------------------------------------------------------------
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// Include Files
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//----------------------------------------------------------------------
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#include <AmiPeiLib.h>
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#include <Library/AmiSioPeiLib.h>
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#include "F81866PeiIoTable.h"
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#include <Setup.h>
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#include <AmiCspLib.h>
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VOID RayDebug80(UINT8 Time, UINT8 Code){
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UINTN i;
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i = 0x0FFFF | (Time << 16);
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while(i != 0){
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IoWrite8(0x80, Code);
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i--;
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}
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}
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//----------------------------------------------------------------------
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// internal funtion declare; these funtions are only used by this file.
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//----------------------------------------------------------------------
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#define PORT_SELECT_REGISTER 0x27
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#define GPIO_PROG_SEL BIT2|BIT3
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#define GPIO0_EN 0
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#define GPIO1_EN BIT2
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#define GPIO2_EN BIT3
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#define MULTI_FUNCTION_SELECT_1_REGISTER 0x28
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#define LPT_GP_EN BIT5
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#define UART_IRQ_SHARE_REGISTER 0xF0
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#define RS485_EN BIT4
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#define ACPICONTROLREGISTER1 0xF4
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#define PWRCTRL BIT1|BIT2
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#define KEEP_LAST_STATE 0
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#define ALWAYS_ON BIT2
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#define BYPASS_MODE BIT1
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#define ALWAYS_OFF BIT1|BIT2
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#define GPIO0_OUTPUT_ENABLE_REGISTER 0xF0
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#define GPIO0_OUTPUT_DATA_REGISTER 0xF1
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#define GPIO0_DRIVE_ENABLE_REGISTER 0xF3
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#define GPIO1_OUTPUT_ENABLE_REGISTER 0xE0
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#define GPIO1_OUTPUT_DATA_REGISTER 0xE1
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#define GPIO1_DRIVE_ENABLE_REGISTER 0xE3
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#define GPIO2_OUTPUT_ENABLE_REGISTER 0xD0
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#define GPIO2_OUTPUT_DATA_REGISTER 0xD1
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#define GPIO2_DRIVE_ENABLE_REGISTER 0xD3
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#define GPIO3_OUTPUT_ENABLE_REGISTER 0xC0
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#define GPIO3_OUTPUT_DATA_REGISTER 0xC1
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#define GPIO3_DRIVE_ENABLE_REGISTER 0xC3
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#define GPIO4_OUTPUT_ENABLE_REGISTER 0xB0
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#define GPIO4_OUTPUT_DATA_REGISTER 0xB1
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#define GPIO4_DRIVE_ENABLE_REGISTER 0xB3
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#define GPIO5_OUTPUT_ENABLE_REGISTER 0xA0
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#define GPIO5_OUTPUT_DATA_REGISTER 0xA1
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#define GPIO5_DRIVE_ENABLE_REGISTER 0xA3
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#define GPIO6_OUTPUT_ENABLE_REGISTER 0x90
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#define GPIO6_OUTPUT_DATA_REGISTER 0x91
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#define GPIO6_DRIVE_ENABLE_REGISTER 0x93
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#define GPIO7_OUTPUT_ENABLE_REGISTER 0x80
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#define GPIO7_OUTPUT_DATA_REGISTER 0x81
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#define GPIO7_DRIVE_ENABLE_REGISTER 0x83
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#define GPIO8_OUTPUT_ENABLE_REGISTER 0x88
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#define GPIO8_OUTPUT_DATA_REGISTER 0x89
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#define GPIO8_DRIVE_ENABLE_REGISTER 0x8B
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#define GpioOutput 0
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#define GpioInput 1
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#define GpioLow 0
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#define GpioHigh 1
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#define GpioOpenDrain 0
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#define GpioPushPull 1
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VOID F81866ConfigRegisterWrite(UINT8 Index, UINT8 Data)
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{
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IoWrite8(F81866_CONFIG_INDEX, Index);
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IoWrite8(F81866_CONFIG_DATA, Data);
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}
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UINT8 F81866ConfigRegisterRead(UINT8 Index)
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{
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UINT8 Data8;
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IoWrite8(F81866_CONFIG_INDEX, Index);
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Data8 = IoRead8(F81866_CONFIG_DATA);
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return Data8;
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}
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VOID F81866LDNSelect(UINT8 Ldn)
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{
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IoWrite8(F81866_CONFIG_INDEX, F81866_LDN_SEL_REGISTER);
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IoWrite8(F81866_CONFIG_DATA, Ldn);
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}
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VOID F81866EnterConfigMode()
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{
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IoWrite8(F81866_CONFIG_INDEX, F81866_CONFIG_MODE_ENTER_VALUE);
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IoWrite8(F81866_CONFIG_INDEX, F81866_CONFIG_MODE_ENTER_VALUE);
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}
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VOID F81866ExitConfigMode()
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{
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// Exit config mode
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IoWrite8(F81866_CONFIG_INDEX, F81866_CONFIG_MODE_EXIT_VALUE);
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}
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VOID F81866SetGpioPin(IN UINT8 GpioNum, IN UINT8 Type, IN UINT8 Level, IN UINT8 Drive)
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{
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UINT8 Data8, Offset;
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F81866EnterConfigMode();
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F81866LDNSelect(F81866_LDN_GPIO); //GPIO Device Configuration Registers
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if( (GpioNum/10) <= 7 ){
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Offset = ( ~(GpioNum/10) );
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Offset = Offset << 4;
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Offset &= 0xF0;
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}
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else if ( (GpioNum/10) == 8 )
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Offset = 0x88;
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Data8 = F81866ConfigRegisterRead(Offset + 3); //Drive Enable Register
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Data8 &= ~( 1 << ( GpioNum%10 ) );
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if(Drive == 1)
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Data8 |= ( 1 << ( GpioNum%10 ) );
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F81866ConfigRegisterWrite(Offset + 3, Data8);
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Data8 = F81866ConfigRegisterRead(Offset); //Output Enable Register
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Data8 &= ~( 1 << ( GpioNum%10 ) );
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if(Type == 0)
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Data8 |= ( 1 << ( GpioNum%10 ) );
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F81866ConfigRegisterWrite(Offset, Data8);
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Data8 = F81866ConfigRegisterRead(Offset + 1); //Output Data Register
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Data8 &= ~( 1 << ( GpioNum%10 ) );
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if(Level == 1)
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Data8 |= ( 1 << ( GpioNum%10 ) );
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F81866ConfigRegisterWrite(Offset + 1, Data8);
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F81866ExitConfigMode();
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}
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VOID F81866MiscSetupFunction(IN CONST EFI_PEI_SERVICES **PeiServices)
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{
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EFI_STATUS Status;
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SETUP_DATA SetupData;
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UINTN VariableSize = sizeof( SETUP_DATA );
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EFI_GUID gSetupGuid = SETUP_GUID;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *ReadOnlyVariable = NULL;
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Status = (*PeiServices)->LocatePpi( PeiServices, &gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &ReadOnlyVariable );
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Status = ReadOnlyVariable->GetVariable( ReadOnlyVariable, L"Setup", &gSetupGuid, NULL, &VariableSize, &SetupData );
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F81866EnterConfigMode();
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// Restore AC Power Loss control _Begin >>
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{
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UINT8 Data8;
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F81866LDNSelect(F81866_LDN_PME); // PME, ACPI and ERP Device Configuration Registers (LDN CR0A)
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Data8 = F81866ConfigRegisterRead(ACPICONTROLREGISTER1);
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Data8 &= ~(PWRCTRL);
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switch(SetupData.F81866RestoreACPowerLoss)
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{
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default:
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case 0: // Last State
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Data8 |= KEEP_LAST_STATE;
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break;
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case 1: // Always On
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Data8 |= ALWAYS_ON;
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break;
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case 2: // Always Off
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Data8 |= ALWAYS_OFF;
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break;
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case 3: // Bypass
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Data8 |= BYPASS_MODE;
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break;
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}
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F81866ConfigRegisterWrite(ACPICONTROLREGISTER1, Data8);
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}
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// Restore AC Power Loss control _End <<
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// UART RS485 auto flow control Enabled/Disabled _Begin >>
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{
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UINT8 Data8, i;
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UINT8 F81866AllUartLdn[6] = { F81866_LDN_UART1, F81866_LDN_UART2, F81866_LDN_UART3,\
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F81866_LDN_UART4, F81866_LDN_UART5, F81866_LDN_UART6 };
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for(i = 0; i < 6; i++)
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{
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F81866LDNSelect(F81866AllUartLdn[i]); // All UART LDN
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Data8 = F81866ConfigRegisterRead(UART_IRQ_SHARE_REGISTER);
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Data8 &= ~(RS485_EN);
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if(SetupData.F81866UartAutoFlowControlEnable[i] == 1)
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Data8 |= RS485_EN;
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F81866ConfigRegisterWrite(UART_IRQ_SHARE_REGISTER, Data8);
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}
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}
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// UART RS485 auto flow control Enabled/Disabled _End <<
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// Parallel Port / Gpio multi function selection _Begin >>
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{
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UINT8 Data8;
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Data8 = F81866ConfigRegisterRead(PORT_SELECT_REGISTER);
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Data8 &= ~(GPIO_PROG_SEL);
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Data8 |= GPIO0_EN;
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Data8 = F81866ConfigRegisterRead(MULTI_FUNCTION_SELECT_1_REGISTER);
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Data8 &= ~(LPT_GP_EN);
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if(SetupData.F81866Gpio7x8x_Lpt_Switch == 0)
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Data8 |= LPT_GP_EN;
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F81866ConfigRegisterWrite(MULTI_FUNCTION_SELECT_1_REGISTER, Data8);
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}
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// Parallel Port / Gpio multi function selection _End <<
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// GPIO setup variable _Begin >>
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{
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UINT8 i;
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UINT8 Gpio_Oe, Gpio_Val, Gpio_DrvEn;
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F81866LDNSelect(F81866_LDN_GPIO); //GPIO Device Configuration Registers
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO0X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio0x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio0x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio0x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO0_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO0_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO0_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO1X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio1x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio1x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio1x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO1_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO1_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO1_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO2X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio2x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio2x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio2x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO2_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO2_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO2_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO3X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio3x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio3x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio3x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO3_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO3_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO3_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO4X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio4x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio4x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio4x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO4_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO4_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO4_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO5X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio5x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio5x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio5x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO5_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO5_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO5_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO6X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio6x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio6x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio6x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO6_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO6_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO6_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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// GPIO7X Misc configuration
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio7x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio7x_Val[i]) << i ) ;
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio7x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO7_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO7_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO7_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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// GPIO8X Misc configuration
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Gpio_Oe = Gpio_Val = Gpio_DrvEn = 0;
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for (i = 0; i < 8; i++)
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{
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Gpio_Oe |= ( (BOOLEAN)(SetupData.F81866Gpio8x_Oe[i]) << i );
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Gpio_Val |= ( (BOOLEAN)(SetupData.F81866Gpio8x_Val[i]) << i );
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Gpio_DrvEn |= ( (BOOLEAN)(SetupData.F81866Gpio8x_DrvEn[i]) << i );
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}
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F81866ConfigRegisterWrite(GPIO8_OUTPUT_DATA_REGISTER, Gpio_Val);
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F81866ConfigRegisterWrite(GPIO8_DRIVE_ENABLE_REGISTER, Gpio_DrvEn);
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F81866ConfigRegisterWrite(GPIO8_OUTPUT_ENABLE_REGISTER, Gpio_Oe);
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}
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// GPIO setup variable _End <<
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F81866ExitConfigMode();
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}
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//**********************************************************************
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// belows are functions defined
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//**********************************************************************
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// <AMI_PHDR_START>
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//----------------------------------------------------------------------
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//
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// Procedure: F81866_PeiClearDevResource
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//
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// Description:
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// This function will Clear SIO resource
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//
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// Input:
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// IN UINT8 Ldn
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// Output:
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// NONE
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//
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//----------------------------------------------------------------------
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// <AMI_PHDR_END>
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VOID F81866_PeiClearDevResource(
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IN UINT8 Ldn
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)
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{
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// Seclect device LDN
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IoWrite8(F81866_CONFIG_INDEX, F81866_LDN_SEL_REGISTER);
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IoWrite8(F81866_CONFIG_DATA, Ldn);
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// Deactivate Device
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IoWrite8(F81866_CONFIG_INDEX, F81866_ACTIVATE_REGISTER);
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IoWrite8(F81866_CONFIG_DATA, F81866_DEACTIVATE_VALUE);
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// Clear Base Address
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IoWrite8(F81866_CONFIG_INDEX, F81866_BASE1_HI_REGISTER);
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IoWrite8(F81866_CONFIG_DATA, 0);
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IoWrite8(F81866_CONFIG_INDEX, F81866_BASE1_LO_REGISTER);
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IoWrite8(F81866_CONFIG_DATA, 0);
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// Clear Interrupt
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IoWrite8(F81866_CONFIG_INDEX, F81866_IRQ1_REGISTER);
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IoWrite8(F81866_CONFIG_DATA, 0);
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return;
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}
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// <AMI_PHDR_START>
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//----------------------------------------------------------------------
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//
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// Procedure: F81866PeiInitEntryPoint
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//
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// Description:
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// This function provide PEI phase SIO initialization
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//
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// Input:
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// IN EFI_FFS_FILE_HEADER *FfsHeader - Logical Device's information
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// IN EFI_PEI_SERVICES **PeiServices - Read/Write PCI config space
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//
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// Output: None
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//
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// Modified: Nothing
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//
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// Referrals: None
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//
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// Note:
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//----------------------------------------------------------------------
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// <AMI_PHDR_END>
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EFI_STATUS F81866PeiInitEntryPoint(
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IN EFI_PEI_FILE_HANDLE FileHandle,
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IN CONST EFI_PEI_SERVICES **PeiServices
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)
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{
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#if !defined(SecDecodePkg_SUPPORT) || (SecDecodePkg_SUPPORT == 0)
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UINT8 index;
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for(index=0; index<sizeof(F81866PeiDecodeTable)/sizeof(IO_DECODE_DATA); index++)
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AmiSioLibSetLpcDeviceDecoding(NULL, F81866PeiDecodeTable[index].BaseAdd, F81866PeiDecodeTable[index].UID, F81866PeiDecodeTable[index].Type);
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#endif
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ProgramRtRegisterTable(0, F81866PeiInitTable, sizeof(F81866PeiInitTable)/sizeof(SIO_DEVICE_INIT_DATA));
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// Enter Configuration Mode.
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|
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IoWrite8(F81866_CONFIG_INDEX, F81866_CONFIG_MODE_ENTER_VALUE);
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IoWrite8(F81866_CONFIG_INDEX, F81866_CONFIG_MODE_ENTER_VALUE);
|
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// Disable Non-Used Device in Pei Phase,if its default value is actived.
|
|
// F81866_CLEAR_UNUSED_LDN_RES >>
|
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// F81866_PeiClearDevResource(F81866_LDN_UART3);
|
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// F81866_PeiClearDevResource(F81866_LDN_UART4);
|
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// F81866_PeiClearDevResource(F81866_LDN_UART5);
|
|
// F81866_PeiClearDevResource(F81866_LDN_UART6);
|
|
#if !F81866_SERIAL_PORT1_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_UART1);
|
|
#endif
|
|
#if !F81866_SERIAL_PORT2_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_UART2);
|
|
#endif
|
|
#if !F81866_SERIAL_PORT3_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_UART3);
|
|
#endif
|
|
#if !F81866_SERIAL_PORT4_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_UART4);
|
|
#endif
|
|
#if !F81866_SERIAL_PORT5_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_UART5);
|
|
#endif
|
|
#if !F81866_SERIAL_PORT6_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_UART6);
|
|
#endif
|
|
#if !F81866_PARALLEL_PORT_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_LPT);
|
|
#endif
|
|
#if !F81866_KEYBOARD_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_PS2K);
|
|
#endif
|
|
#if !F81866_FLOPPY_PORT_PRESENT
|
|
F81866_PeiClearDevResource(F81866_LDN_FDC);
|
|
#endif
|
|
//F81866_CLEAR_UNUSED_LDN_RES <<
|
|
// Exit Configuration Mode
|
|
IoWrite8(F81866_CONFIG_INDEX, F81866_CONFIG_MODE_EXIT_VALUE);
|
|
|
|
F81866MiscSetupFunction(PeiServices);
|
|
|
|
return EFI_SUCCESS;
|
|
}
|
|
|
|
//**********************************************************************
|
|
//**********************************************************************
|
|
//** **
|
|
//** (C)Copyright 1985-2013, American Megatrends, Inc. **
|
|
//** **
|
|
//** All Rights Reserved. **
|
|
//** **
|
|
//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
|
|
//** **
|
|
//** Phone: (770)-246-8600 **
|
|
//** **
|
|
//**********************************************************************
|
|
//**********************************************************************
|