377 lines
20 KiB
C
377 lines
20 KiB
C
//**********************************************************************
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//**********************************************************************
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//** **
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//** (C)Copyright 1985-2014, American Megatrends, Inc. **
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//** **
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//** All Rights Reserved. **
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//** **
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//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
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//** **
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//** Phone: (770)-246-8600 **
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//** **
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//**********************************************************************
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//**********************************************************************
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/** @file OemPeiIoTable.c
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SIO init table in PEI phase. Any customers have to review below tables
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for themselves platform and make sure each initialization is necessary.
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@note In all tables, only fill with necessary setting. Don't fill with default
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**/
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//----------------------------------------------------------------------
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// Include Files
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//----------------------------------------------------------------------
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#include <Token.h>
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#include <Library/AmiSioPeiLib.h>
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///---------------------------------------------------------------------
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///Decode table for PEI phase.
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///---------------------------------------------------------------------
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IO_DECODE_DATA IT8625PeiDecodeTable[]= {
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// -----------------------------
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//| BaseAdd | UID | Type |
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// -----------------------------
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{IT8625_CONFIG_INDEX, 2, 0xFF},
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//Decode for KBC
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#if (IT8625_KEYBOARD_PRESENT)
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{0x60, 0, dsPS2K}, // KBC decode
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#endif
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//Below decode is for recovery mode
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#if (IT8625_RECOVERY_SUPPORT)
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{RECOVERY_COM_PORT_ADDR, 0x02, dsUART},
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#endif
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//Below decode is for SIO generic IO decode
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#if defined(IT8625_TOTAL_BASE_ADDRESS) && (IT8625_TOTAL_BASE_ADDRESS != 0)
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{IT8625_TOTAL_BASE_ADDRESS, IT8625_TOTAL_LENGTH, 0xFF},
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#endif
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// !!!!Attention!!!!This is necessary
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//OEM_TODO//OEM_TODO//OEM_TODO//OEM_TODO
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// If your com port number > 2 , you'd add more table for more com ports.
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// Add more OEM IO decode below.
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#if (IT8625_CIR_PORT_PRESENT)
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{0x3E0, 0x10, 0xFF},//for CIR
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#endif
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};
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///---------------------------------------------------------------------
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///The PEI decode table count.
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///---------------------------------------------------------------------
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UINT8 IT8625PeiDecodeTableCount = sizeof(IT8625PeiDecodeTable)/sizeof(IO_DECODE_DATA);
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///---------------------------------------------------------------------
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///Init table for PEI phase.
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///---------------------------------------------------------------------
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SIO_DEVICE_INIT_DATA IT8625PeiInitTable[]= {
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// -----------------------------
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//| Addr | DataMask | DataValue |
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// -----------------------------
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//------------------------------------------------------------------
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// >>ITE Workaround for early I/O initialization sequence start
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// Base on IT8625E_09_13_15_16_17_18_56_51_69-BIOS_APNoteV19.pdf, Doc No.: ITEU3-AN-13019
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//------------------------------------------------------------------
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{IT8625_CONFIG_INDEX, 0x00, 0x87},
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{IT8625_CONFIG_INDEX, 0x00, 0x01},
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{IT8625_CONFIG_INDEX, 0x00, 0x55},
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#if (IT8625_CONFIG_INDEX == 0x2E)
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{IT8625_CONFIG_INDEX, 0x00, 0x55},
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#else
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{IT8625_CONFIG_INDEX, 0x00, 0xAA},
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#endif
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//Clock Setting
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{IT8625_CONFIG_INDEX, 0x00, 0x23},
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{IT8625_CONFIG_DATA, 0xE6, (IT8625_WDT_LED_CLOCK_SRC << 4) | (IT8625_CLK_SELECT << 3) | IT8625_CLOCK}, //Bit0: CLKIN Frequence; Bit3: CLK select; Bit4: Clock Source Select of Watch Dog Timer and LED Blinking
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{IT8625_CONFIG_INDEX, 0x00, 0x07},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_GPIO}, //LDN 07
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// >> AAEON_OVERRIDE
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// GPIO Set 1 Multi-Function Pin Selection Register (Index=25h, Default=00h)
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{IT8625_CONFIG_INDEX, 0x00, 0x25},
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{IT8625_CONFIG_DATA, 0x00, (PIN_25_FUN_SEL << 7) | (PIN_127_FUN_SEL << 6) | (PIN_128_FUN_SEL << 5) | (PIN_28_FUN_SEL << 4) | (PIN_13_FUN_SEL << 3) | (PIN_30_FUN_SEL << 2) | (PIN_31_FUN_SEL << 1) | PIN_81_FUN_SEL},
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// GPIO Set 2 Multi-Function Pin Selection Register (Index=26h, Default=F3h)
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{IT8625_CONFIG_INDEX, 0x00, 0x26},
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{IT8625_CONFIG_DATA, 0x00, (PIN_17_FUN_SEL << 7) | (PIN_18_FUN_SEL << 6) | (PIN_19_FUN_SEL << 5) | (PIN_20_FUN_SEL << 4) | (PIN_21_FUN_SEL << 3) | (PIN_22_FUN_SEL << 2) | (PIN_23_FUN_SEL << 1) | PIN_24_FUN_SEL},
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// GPIO Set 3 Multi-Function Pin Selection Register (Index=27h, Default=00h)
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{IT8625_CONFIG_INDEX, 0x00, 0x27},
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{IT8625_CONFIG_DATA, 0x00, (PIN_8_FUN_SEL << 7) | (PIN_9_FUN_SEL << 6) | (PIN_10_FUN_SEL << 5) | (PIN_11_FUN_SEL << 4) | (PIN_124_FUN_SEL << 3) | (PIN_125_FUN_SEL << 2) | (PIN_126_FUN_SEL << 1) | PIN_16_FUN_SEL},
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// GPIO Set 4 Multi-Function Pin Selection Register (Index=28h, Default=00h)
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{IT8625_CONFIG_INDEX, 0x00, 0x28},
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{IT8625_CONFIG_DATA, 0x40, (PIN_67_FUN_SEL << 7) | (PIN_120_FUN_SEL << 5) | (PIN_53_FUN_SEL << 4) | (PIN_51_FUN_SEL << 3) | (PIN_118_FUN_SEL << 2) | (PIN_122_FUN_SEL << 1) | PIN_76_FUN_SEL},
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// GPIO Set 5 Multi-Function Pin Selection Register (Index=29h, Default=01h)
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{IT8625_CONFIG_INDEX, 0x00, 0x29},
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{IT8625_CONFIG_DATA, 0x00, (PIN_80_79_FUN_SEL << 7) | (PIN_78_77_42_FUN_SEL << 6) | (PIN_82_FUN_SEL << 5) | (PIN_70_FUN_SEL << 4) | (PIN_74_FUN_SEL << 3) | (PIN_6_FUN_SEL << 2) | (PIN_7_FUN_SEL << 1) | PIN_45_FUN_SEL},
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// << AAEON_OVERRIDE
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{IT8625_CONFIG_INDEX, 0x00, 0x2D},
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// >> AAEON_OVERRIDE
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//{IT8625_CONFIG_DATA, 0xF9, (IT8625_PCICLK << 2) | (IT8625_DPLL_RESET << 1)}, //Bit1: DPLL Reset Enable; Bit2: PCICLK select
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{IT8625_CONFIG_DATA, 0x05, (PIN_115_FUN_SEL << 7) | (PIN_116_FUN_SEL << 6) | (PIN_117_FUN_SEL << 5) | (PIN_2_FUN_SEL << 4) | (PIN_3_FUN_SEL << 3) | (!FAN_TAC5 << 1)},
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// << AAEON_OVERRIDE
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// >> AAEON_OVERRIDE
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// Initial GPIO I/O Base Address
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{IT8625_CONFIG_INDEX, 0x00, 0x62},
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{IT8625_CONFIG_DATA, 0x00, (UINT8)(IO1B >> 8)},
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{IT8625_CONFIG_INDEX, 0x00, 0x63},
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{IT8625_CONFIG_DATA, 0x00, (UINT8)(IO1B & 0xFF)},
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// << AAEON_OVERRIDE
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{IT8625_CONFIG_INDEX, 0x00, 0x71},
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{IT8625_CONFIG_DATA, 0xF7, IT8625_CLK_IN_SELECT << 3}, //Bit3: External CLK_IN Select.
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_ENV}, //LDN 04
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{IT8625_CONFIG_INDEX, 0x00, 0xF0},
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{IT8625_CONFIG_DATA, 0x00, 0x00}, //0xF0= 00h
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{IT8625_CONFIG_INDEX, 0x00, 0xF1},
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{IT8625_CONFIG_DATA, 0x00, 0xBF}, //0xF1= BFh
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{IT8625_CONFIG_INDEX, 0x00, 0xF2},
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{IT8625_CONFIG_DATA, 0x00, 0x00}, //0xF2= 00
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{IT8625_CONFIG_INDEX, 0x00, 0xF3},
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{IT8625_CONFIG_DATA, 0x00, 0x00}, //0xF3= 00
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{IT8625_CONFIG_INDEX, 0x00, 0xF4},
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{IT8625_CONFIG_DATA, 0x00, 0x00}, //0xF4= 00
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{IT8625_CONFIG_INDEX, 0x00, 0xF5},
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{IT8625_CONFIG_DATA, 0x3F, 0x00}, //0xF5<7,6>= 0,0b
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{IT8625_CONFIG_INDEX, 0x00, 0xF9},
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{IT8625_CONFIG_DATA, 0x7F, 0x00}, //0xF9<7>=0b (default)
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{IT8625_CONFIG_INDEX, 0x00, 0xFA},
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{IT8625_CONFIG_DATA, 0x00, 0x00}, //0xFA= 00h
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{IT8625_CONFIG_INDEX, 0x00, 0xFB},
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{IT8625_CONFIG_DATA, 0xF3, 0x0C}, //0xFB<3,2> (write "1" clear status)
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_GPIO}, //LDN 07
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{IT8625_CONFIG_INDEX, 0x00, 0x28},
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{IT8625_CONFIG_DATA, 0xBF, 0x00}, //Index28 Bit6=0 (keep default)
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{IT8625_CONFIG_INDEX, 0x00, 0x2A},
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{IT8625_CONFIG_DATA, 0x5F, 0x00}, //0x2A<5>= 0(disable RSTCONIN); don't enable LDN07 2A bit7
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{IT8625_CONFIG_INDEX, 0x00, 0x72},
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{IT8625_CONFIG_DATA, 0xEF, 0x00}, //0x72<4>=0(disable WDT if no use)
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{IT8625_CONFIG_INDEX, 0x00, 0x23},
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{IT8625_CONFIG_DATA, 0xBF, 0x40}, //0x23<6>=1
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// #if (JP4==1)
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{IT8625_CONFIG_INDEX, 0x00, 0x2C},
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{IT8625_CONFIG_DATA, 0xB7, (PWRGD_SRC_BY_VIN3 << 3) | 0x40}, //Index2C Bit6=1
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// #endif
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_ENV},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE1_HI_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, (UINT8)(IT8625_HWM_BASE_ADDRESS >> 8)},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE1_LO_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, (UINT8)(IT8625_HWM_BASE_ADDRESS & 0xFF)},
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// Activate Device
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{IT8625_CONFIG_INDEX, 0x00, IT8625_ACTIVATE_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_ACTIVATE_VALUE},
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{IT8625_CONFIG_INDEX, 0x00, 0x02},
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{IT8625_CONFIG_DATA, 0x00, 0x02},
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{IT8625_HWM_INDEX_PORT, 0x00, 0x0A},
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{IT8625_HWM_DATA_PORT, 0xBF, 0x40}, //Index 0Ah:Bit[6]=1b
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{IT8625_HWM_INDEX_PORT, 0x00, 0x00},
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{IT8625_HWM_DATA_PORT, 0xBE, 0x41}, //Index 00 bit0 set"1" Start monitor; Index00 Bit6=1
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//If Intel PECI
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{IT8625_HWM_INDEX_PORT, 0x00, 0x8E},
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{IT8625_HWM_DATA_PORT, 0x3D, 0xC2}, //Index 8Eh Bit[7,6] =1,1b; Index[8E}=02
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{IT8625_HWM_INDEX_PORT, 0x00, 0x0A},
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{IT8625_HWM_DATA_PORT, 0xC3, 0x24}, //Index 0Ah: Bit[2]=1b;Bit[3]=0b;Bit[5:4]=10b
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//If AMD TSI
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//{IT8625_HWM_INDEX_PORT, 0x00, 0x98},
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//{IT8625_HWM_DATA_PORT, 0x00, 0x40}, //Index 0x98=40
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//------------------------------------------------------------------
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//<<ITE Workaround for early I/O initialization sequence end
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// Enter Configuration Mode.
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//------------------------------------------------------------------
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{IT8625_CONFIG_INDEX, 0x00, 0x87},
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{IT8625_CONFIG_INDEX, 0x00, 0x01},
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{IT8625_CONFIG_INDEX, 0x00, 0x55},
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#if (IT8625_CONFIG_INDEX == 0x2E)
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{IT8625_CONFIG_INDEX, 0x00, 0x55},
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#else
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{IT8625_CONFIG_INDEX, 0x00, 0xAA},
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#endif
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//------------------------------------------------------------------
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// Before init all logical devices, program Global register if needed.
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//------------------------------------------------------------------
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// Select GPIO device
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_GPIO},
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#if (IT8625_SERIAL_PORT2_PRESENT)
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{IT8625_CONFIG_INDEX, 0x00, 0x26}, // clear index 26h bit7~4 bit1~0
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{IT8625_CONFIG_DATA, 0x0C, 0x00},
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#endif // IT8625_SERIAL_PORT2_PRESENT
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//------------------------------------------------------------------
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// Initialize KBC if exist
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//------------------------------------------------------------------
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#if (IT8625_KEYBOARD_PRESENT)
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// Seclect device KEYBOARD
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_PS2K},
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// Program Base Addr
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE1_HI_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, 0x00},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE1_LO_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, 0x60},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE2_HI_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, 0x00},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE2_LO_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, 0x64},
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// Program Interrupt
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{IT8625_CONFIG_INDEX, 0x00, IT8625_IRQ1_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, 0x01},
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// Activate Device
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{IT8625_CONFIG_INDEX, 0x00, IT8625_ACTIVATE_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_ACTIVATE_VALUE},
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#else
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// Deactivate Device
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_PS2K},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_ACTIVATE_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_DEACTIVATE_VALUE},
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#endif //IT8625_KEYBOARD_PRESENT
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//------------------------------------------------------------------
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// Initialize Serial Port and Floppy Controller for Recovery
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//------------------------------------------------------------------
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#if (IT8625_RECOVERY_SUPPORT)
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// Select device
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, RECOVERY_LDN_UART},
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// Program Base Addr
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE1_LO_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, (UINT8)(RECOVERY_COM_PORT_ADDR & 0xFF)},
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{IT8625_CONFIG_INDEX, 0x00, IT8625_BASE1_HI_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, (UINT8)(RECOVERY_COM_PORT_ADDR >> 8)},
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// Activate Device
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{IT8625_CONFIG_INDEX, 0x00, IT8625_ACTIVATE_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_ACTIVATE_VALUE},
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#endif //IT8625_RECOVERY_SUPPORT
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//------------------------------------------------------------------
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// Program and initialize some logical device if needed.
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//------------------------------------------------------------------
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// Seclect device KEYBOARD
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_PS2K},
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// config
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{IT8625_CONFIG_INDEX, 0x00, 0xF0},
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{IT8625_CONFIG_DATA, 0xF7, 0x00 | (IT8625_KBC_CLOCK << 3)},
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// Seclect Environment Controller
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{IT8625_CONFIG_INDEX, 0x00, IT8625_LDN_SEL_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, IT8625_LDN_ENV},
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// Clear Interrupt
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{IT8625_CONFIG_INDEX, 0x00, IT8625_IRQ1_REGISTER},
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{IT8625_CONFIG_DATA, 0x00, 0x00},
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// config
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{IT8625_CONFIG_INDEX, 0x00, 0xF4}, //Auto-swap of KCLK/KDAT and MCLK/MDAT
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{IT8625_CONFIG_DATA, 0x7F, IT8625_PS2_SWAP << 7},
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//------------------------------------------------------------------
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// After init all logical devices, program Global register if needed.
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//------------------------------------------------------------------
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//------------------------------------------------------------------
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// After init all logical devices, Exit Configuration Mode.
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//------------------------------------------------------------------
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{IT8625_CONFIG_INDEX, 0x00, 0x02},
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{IT8625_CONFIG_DATA, 0x00, 0x02},
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// >> AAEON_OVERRIDE Porting from DXE to PEI
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//---------------------------------------------------------------------
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// PEI Init Hardware Monitor.
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//---------------------------------------------------------------------
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#if IT8625_HWM_PRESENT
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#if (IT8625_PECI)
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//Programming PECI
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{IT8625_HWM_INDEX_PORT, 0x00, 0x0A}, // Interface Selection Register
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{IT8625_HWM_DATA_PORT, 0xCF, 0x20}, // 0Ah[5-4]=10
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{IT8625_HWM_INDEX_PORT, 0x00, 0x8E}, // External Temperature Sensor Host Control Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 8Eh=00
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{IT8625_HWM_INDEX_PORT, 0x00, 0x88}, // External Temperature Sensor Host Status Register
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{IT8625_HWM_DATA_PORT, 0x00, 0xFF}, // 88h=FF to clear status
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//TMPIN Source Selection.
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{IT8625_HWM_INDEX_PORT, 0x00, 0x06}, // SMI# Mask Register 3
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{IT8625_HWM_DATA_PORT, 0x9F, 0x40}, // Bank2
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{IT8625_HWM_INDEX_PORT, 0x00, 0x1D}, // TMPIN Source Selection – 1 (TSS1) for TMPIN1 & TMPIN2
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{IT8625_HWM_DATA_PORT, 0x00, 0x00 | (TMPIN2_SRC_SEL << 4) // TMPIN2 Source Selection
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| TMPIN1_SRC_SEL}, // TMPIN1 Source Selection
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{IT8625_HWM_INDEX_PORT, 0x00, 0x1E}, // TMPIN Source Selection – 1 (TSS1) for TMPIN3 & TMPIN4
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{IT8625_HWM_DATA_PORT, 0x00, 0x00 | (TMPIN4_SRC_SEL << 4) // TMPIN4 Source Selection
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| TMPIN3_SRC_SEL}, // TMPIN3 Source Selection
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{IT8625_HWM_INDEX_PORT, 0x00, 0x1F}, // TMPIN Source Selection – 1 (TSS1) for TMPIN5 & TMPIN6
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{IT8625_HWM_DATA_PORT, 0x00, 0x00 | (TMPIN6_SRC_SEL << 4) // TMPIN6 Source Selection
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| TMPIN5_SRC_SEL}, // TMPIN5 Source Selection
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//Thermal Diode Zero Degree Adjust.
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{IT8625_HWM_INDEX_PORT, 0x00, 0x06}, // SMI# Mask Register 3
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{IT8625_HWM_DATA_PORT, 0x9F, 0x00}, // Bank0
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{IT8625_HWM_INDEX_PORT, 0x00, 0x5C}, // Beep Event Enable Register
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{IT8625_HWM_DATA_PORT, 0x7F, 0x80}, // 5Ch[7]=1 for enable access thermal diode zero degree adjust.
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{IT8625_HWM_INDEX_PORT, 0x00, 0x56}, // TMPIN1 Zero Degree Adjust Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 56h(TMPIN1)
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{IT8625_HWM_INDEX_PORT, 0x00, 0x57}, // TMPIN2 Zero Degree Adjust Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 57h(TMPIN2)
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{IT8625_HWM_INDEX_PORT, 0x00, 0x59}, // TMPIN3 Zero Degree Adjust Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 59h(TMPIN3)
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{IT8625_HWM_INDEX_PORT, 0x00, 0x5A}, // TMPIN4 Zero Degree Adjust Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 5Ah(TMPIN4)
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{IT8625_HWM_INDEX_PORT, 0x00, 0x90}, // TMPIN5 Zero Degree Adjust Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 90h(TMPIN5)
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{IT8625_HWM_INDEX_PORT, 0x00, 0x91}, // TMPIN6 Zero Degree Adjust Register
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{IT8625_HWM_DATA_PORT, 0x00, 0x00}, // 91h(TMPIN6)
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{IT8625_HWM_INDEX_PORT, 0x00, 0x5C}, // Beep Event Enable Register
|
||
{IT8625_HWM_DATA_PORT, 0x7F, 0x00}, // 5Ch[7]=0 for disable access thermal diode zero degree adjust.
|
||
#endif // IT8625_PECI
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0x0B}, // General Control Register 1
|
||
{IT8625_HWM_DATA_PORT, 0xF7, 0x00 | (FAN_TAC6 << 3)}, //BIT3: FAN_TAC6 Enable
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0x0C}, // General Control Register 2
|
||
{IT8625_HWM_DATA_PORT, 0xCF, 0x00 | (FAN_TAC5 << 5) | (FAN_TAC4 << 4)}, //BIT5~4: FAN_TAC5-4 Enable
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0x13}, // Fan Controller Main Control Register
|
||
{IT8625_HWM_DATA_PORT, 0x8F, 0x00 | (FAN_TAC3 << 6) // BIT6: FAN_TAC3 Enable
|
||
| (FAN_TAC2 << 5) // BIT5: FAN_TAC2 Enable
|
||
| (FAN_TAC1 << 4)}, // BIT4: FAN_TAC1 Enable
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0x50}, // ADC Voltage Channel Enable Register
|
||
{IT8625_HWM_DATA_PORT, 0x00, 0xFF}, //Enable Vin0 - 7
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0x51}, // ADC Temperature Channel Enable Register
|
||
{IT8625_HWM_DATA_PORT, 0x00, 0x00 | (IT8625_TEMP_RESISTOR_MODE_3_ENABLE << 5) //TMPIN 3-1 Thermal Resistor mode
|
||
| (IT8625_TEMP_RESISTOR_MODE_2_ENABLE << 4)
|
||
| (IT8625_TEMP_RESISTOR_MODE_1_ENABLE << 3)
|
||
| (IT8625_TEMP_DIODE_MODE_3_ENABLE << 2) //TMPIN 3-1 Thermal Diode mode
|
||
| (IT8625_TEMP_DIODE_MODE_2_ENABLE << 1)
|
||
| IT8625_TEMP_DIODE_MODE_1_ENABLE},
|
||
// >> IT8625 Serial Port 1 DCD#1 pin workaround
|
||
#if (IT8625_SERIAL_PORT1_PRESENT)
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0xA3}, // FAN_CTL6 SmartGuardian Automatic Mode Start PWM Register
|
||
{IT8625_HWM_DATA_PORT, 0x00, 0xFF}, // Set 0xFF to prevent DCD#1 pin output 23.xx kHz garbage signal
|
||
#endif // IT8625_SERIAL_PORT1_PRESENT
|
||
// << IT8625 Serial Port 1 DCD#1 pin workaround
|
||
//Hardware Monitor Startup!
|
||
{IT8625_HWM_INDEX_PORT, 0x00, 0x00}, // Configuration Register
|
||
{IT8625_HWM_DATA_PORT, 0xBE, 0x41}, //BIT6: Update VBAT Voltage Reading
|
||
//BIT0: Enable the startup of monitoring operations
|
||
#endif // IT8625_HWM_PRESENT
|
||
// << AAEON_OVERRIDE Porting from DXE to PEI
|
||
|
||
};
|
||
|
||
///---------------------------------------------------------------------
|
||
///The PEI init table count.
|
||
///---------------------------------------------------------------------
|
||
UINT8 IT8625PeiInitTableCount = sizeof(IT8625PeiInitTable)/sizeof(SIO_DEVICE_INIT_DATA);
|
||
|
||
//**********************************************************************
|
||
//**********************************************************************
|
||
//** **
|
||
//** (C)Copyright 1985-2014, American Megatrends, Inc. **
|
||
//** **
|
||
//** All Rights Reserved. **
|
||
//** **
|
||
//** 5555 Oakbrook Parkway, Suite 200, Norcross, GA 30093 **
|
||
//** **
|
||
//** Phone: (770)-246-8600 **
|
||
//** **
|
||
//**********************************************************************
|
||
//**********************************************************************
|