============================ Picasso 117 VBIOS release ======================================== Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.117 09/02/19,02:55AM 1992007@16.2.0.11 ATOMBuild #479078 Major changes: 1. Optimized the logic to avoid the long delay if pwr_on_vary_bl_to_blon in integrated info table is "0". ============================ Picasso 116 VBIOS release ======================================== Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.116 07/18/19,01:14AM 1969498@16.2.0.11 ATOMBuild #472089 Major changes: 1. Optimize the eDP power on timing between VARY_BL(PWM) and BLON ============================ Picasso 115 VBIOS release ======================================== Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.115 04/25/2019,05:49AM 1774250@16.2.0.10 ATOMBuild #457094 Major changes: 1. Revise the logic to select teh supported link rate for eDP V1.4 and up ============================ Picasso 114 VBIOS release ======================================== Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.114 11/05/2018,5:27AM 1702205@16.2.0.10 ATOMBuild #434041 Major changes: 1. fix ulSupportedDPLinkRate in device info is not correct if DPCD_SUPPORTED_LINK_RATE0/7 support in eDP DPCD(1.4) 2. when the OTG timing changed, the DP_MSA_PARAMETERSx should be reprogrammed. 3. fix wrong offset when get edptolvdsrxid and stereopinid setting from integrated system info table. ============================ Picasso 113 VBIOS release ======================================== Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.113 9/12/2018,7:37PM 1605109@16.2.0.7 ATOMBuild #429628 Major changes: 1.PCO Enables ASSR on VBIOS notification fixed the no DP display issue introduced in the 112 PCO Vbios release. ============================ Picasso 112 VBIOS release ======================================== Picasso B1 0x15D8 105-D00100-00A PicassoGenericVbios.112 9/7/2018,6:05PM 1603263@16.2.0.7 ATOMBuild #429232 Major changes: 1.PCO Enables ASSR on VBIOS notification VBIOS to notify PSP FW of ASSR enablement instead,New CMD between VBIOS/PSP FW is defined as 0x05. On reception of VBIOS notification, PSP FW will program DCE registers to enable ASSR and report success.