AmdUefiCpuPkg: Data Structures

AmdUefiCpuPkg AmdUefiCpuPkg_04
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Data Structures
Here are the data structures with brief descriptions:
o C _ACPI_RESET_STRUCTURE
o C _BRANCH_TRACE_RECORD
o C _CPU_MP_DATA
o C _EFI_SM_MONITOR_INIT_PROTOCOL
o C _EFI_SMM_CPU_SERVICE_PROTOCOL
o C _GDT_ENTRIES
o C _GDT_ENTRY
o C _MSR_DS_AREA_STRUCT
o C _MTRR_FIXED_SETTINGS_
o C _MTRR_SETTINGS_
o C _MTRR_VARIABLE_SETTING_
o C _MTRR_VARIABLE_SETTINGS_
o C _PEBS_RECORD
o C _SEC_IDT_TABLE
o C _SMM_SUPERVISOR_PROTOCOL
o C ACPI_CPU_DATA
o C ACPI_CPU_DATA_EX
o C AMD_X64_FORMAT
o C CPU_AP_DATA
o C CPU_EXCHANGE_ROLE_INFO
o C CPU_FEATURES_DATA
o C CPU_FEATURES_ENTRY
o C CPU_FEATURES_INIT_ORDER
o C CPU_HOT_PLUG_DATA
o C CPU_INFO_IN_HOB
o C CPU_MICROCODE_DATE
o C CPU_MICROCODE_EXTENDED_TABLE
o C CPU_MICROCODE_EXTENDED_TABLE_HEADER
o C CPU_MICROCODE_HEADER
o C CPU_MICROCODE_PROCESSOR_SIGNATURE
o C CPU_REGISTER_TABLE
o C CPU_REGISTER_TABLE_ENTRY
o C CPU_SMM_SAVE_STATE_IO_WIDTH
o C CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
o C CPU_SMM_SAVE_STATE_REGISTER_RANGE
o C CPU_STATUS_CODE_TEMPLATE
o C CPU_STATUS_INFORMATION
o C CPU_VOLATILE_REGISTERS
o C CPUID_AMD_EXTENDED_CPU_SIG_EAX
o C CPUID_AMD_EXTENDED_CPU_SIG_EBX
o C CPUID_AMD_EXTENDED_CPU_SIG_ECX
o C CPUID_AMD_EXTENDED_CPU_SIG_EDX
o C CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
o C CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
o C CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
o C CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
o C CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
o C CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
o C CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
o C CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
o C CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
o C CPUID_BRAND_STRING_DATA
o C CPUID_CACHE_INFO_CACHE_TLB
o C CPUID_CACHE_PARAMS_EAX
o C CPUID_CACHE_PARAMS_EBX
o C CPUID_CACHE_PARAMS_EDX
o C CPUID_EXTENDED_CACHE_INFO_ECX
o C CPUID_EXTENDED_CPU_SIG_ECX
o C CPUID_EXTENDED_CPU_SIG_EDX
o C CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
o C CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
o C CPUID_EXTENDED_STATE_SUB_LEAF_EAX
o C CPUID_EXTENDED_STATE_SUB_LEAF_ECX
o C CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
o C CPUID_EXTENDED_TOPOLOGY_EAX
o C CPUID_EXTENDED_TOPOLOGY_EBX
o C CPUID_EXTENDED_TOPOLOGY_ECX
o C CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
o C CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
o C CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
o C CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
o C CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
o C CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
o C CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
o C CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
o C CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
o C CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
o C CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
o C CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
o C CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
o C CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
o C CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
o C CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
o C CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
o C CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
o C CPUID_MEMORY_ENCRYPTION_INFO_EAX
o C CPUID_MEMORY_ENCRYPTION_INFO_EBX
o C CPUID_MEMORY_ENCRYPTION_INFO_ECX
o C CPUID_MEMORY_ENCRYPTION_INFO_EDX
o C CPUID_MONITOR_MWAIT_EAX
o C CPUID_MONITOR_MWAIT_EBX
o C CPUID_MONITOR_MWAIT_ECX
o C CPUID_MONITOR_MWAIT_EDX
o C CPUID_PROCESSOR_FREQUENCY_EAX
o C CPUID_PROCESSOR_FREQUENCY_EBX
o C CPUID_PROCESSOR_FREQUENCY_ECX
o C CPUID_SOC_VENDOR_BRAND_STRING_DATA
o C CPUID_SOC_VENDOR_MAIN_LEAF_EBX
o C CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
o C CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
o C CPUID_THERMAL_POWER_MANAGEMENT_EAX
o C CPUID_THERMAL_POWER_MANAGEMENT_EBX
o C CPUID_THERMAL_POWER_MANAGEMENT_ECX
o C CPUID_VERSION_INFO_EAX
o C CPUID_VERSION_INFO_EBX
o C CPUID_VERSION_INFO_ECX
o C CPUID_VERSION_INFO_EDX
o C CPUID_VIR_PHY_ADDRESS_SIZE_EAX
o C EFI_CONFIGURATION_TABLE64
o C EFI_SMM_COMMUNICATION_CONTEXT
o C EFI_SMM_SYSTEM_TABLE2_64
o C ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC
o C ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION
o C ENTRY_EVT_LOG_INVALID_PARAM
o C ENTRY_EVT_LOG_STARTED
o C ENTRY_EVT_LOG_STOPPED
o C ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED
o C ENTRY_EVT_MLE_RSC_PROT_DENIED
o C ENTRY_EVT_MLE_RSC_PROT_GRANTED
o C ENTRY_EVT_MLE_RSC_UNPROT
o C ENTRY_EVT_MLE_RSC_UNPROT_ERROR
o C EXCEPTION0_STUB_HEADER
o C EXCEPTION_HANDLER_CONTEXT
o C EXCEPTION_HANDLER_DATA
o C EXCEPTION_HANDLER_TEMPLATE_MAP
o C FIXED_MTRR
o C IA32_GDT
o C IA32_VMX_MISC_REGISTER
o C LOCAL_APIC_DCR
o C LOCAL_APIC_ICR_HIGH
o C LOCAL_APIC_ICR_LOW
o C LOCAL_APIC_LVT_LINT
o C LOCAL_APIC_LVT_TIMER
o C LOCAL_APIC_MSI_ADDRESS
o C LOCAL_APIC_MSI_DATA
o C LOCAL_APIC_SVR
o C LOCAL_APIC_VERSION
o C LOG_ENTRY_DATA
o C LOG_ENTRY_HEADER
o C MEMORY_PROTECTION_RANGE
o C MEMORY_RANGE
o C MP_ASSEMBLY_ADDRESS_MAP
o C MP_CPU_EXCHANGE_INFO
o C MSEG_HEADER
o C MSR_ATOM_BBL_CR_CTL3_REGISTER
o C MSR_ATOM_EBL_CR_POWERON_REGISTER
o C MSR_ATOM_FSB_FREQ_REGISTER
o C MSR_ATOM_IA32_MISC_ENABLE_REGISTER
o C MSR_ATOM_PEBS_ENABLE_REGISTER
o C MSR_ATOM_PERF_STATUS_REGISTER
o C MSR_ATOM_PLATFORM_ID_REGISTER
o C MSR_ATOM_THERM2_CTL_REGISTER
o C MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER
o C MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER
o C MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER
o C MSR_CORE2_EBL_CR_POWERON_REGISTER
o C MSR_CORE2_FEATURE_CONTROL_REGISTER
o C MSR_CORE2_FSB_FREQ_REGISTER
o C MSR_CORE2_IA32_MISC_ENABLE_REGISTER
o C MSR_CORE2_PEBS_ENABLE_REGISTER
o C MSR_CORE2_PERF_CAPABILITIES_REGISTER
o C MSR_CORE2_PERF_STATUS_REGISTER
o C MSR_CORE2_PLATFORM_ID_REGISTER
o C MSR_CORE2_SMRR_PHYSBASE_REGISTER
o C MSR_CORE2_SMRR_PHYSMASK_REGISTER
o C MSR_CORE2_THERM2_CTL_REGISTER
o C MSR_CORE_BBL_CR_CTL3_REGISTER
o C MSR_CORE_EBL_CR_POWERON_REGISTER
o C MSR_CORE_FSB_FREQ_REGISTER
o C MSR_CORE_IA32_EFER_REGISTER
o C MSR_CORE_IA32_MISC_ENABLE_REGISTER
o C MSR_CORE_THERM2_CTL_REGISTER
o C MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
o C MSR_GOLDMONT_FEATURE_CONTROL_REGISTER
o C MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER
o C MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER
o C MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER
o C MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
o C MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
o C MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER
o C MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
o C MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
o C MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
o C MSR_GOLDMONT_LBR_SELECT_REGISTER
o C MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER
o C MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
o C MSR_GOLDMONT_PEBS_ENABLE_REGISTER
o C MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
o C MSR_GOLDMONT_PKGC3_IRTL_REGISTER
o C MSR_GOLDMONT_PKGC_IRTL1_REGISTER
o C MSR_GOLDMONT_PKGC_IRTL2_REGISTER
o C MSR_GOLDMONT_PLATFORM_INFO_REGISTER
o C MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
o C MSR_GOLDMONT_POWER_CTL_REGISTER
o C MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER
o C MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER
o C MSR_GOLDMONT_SMM_MCA_CAP_REGISTER
o C MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER
o C MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
o C MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
o C MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
o C MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
o C MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
o C MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
o C MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
o C MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
o C MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
o C MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
o C MSR_HASWELL_E_ERROR_CONTROL_REGISTER
o C MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
o C MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
o C MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
o C MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
o C MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
o C MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
o C MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
o C MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
o C MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
o C MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
o C MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
o C MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
o C MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
o C MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
o C MSR_HASWELL_LBR_SELECT_REGISTER
o C MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
o C MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
o C MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
o C MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_HASWELL_PKGC_IRTL1_REGISTER
o C MSR_HASWELL_PKGC_IRTL2_REGISTER
o C MSR_HASWELL_PLATFORM_INFO_REGISTER
o C MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
o C MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
o C MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
o C MSR_HASWELL_SMM_MCA_CAP_REGISTER
o C MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
o C MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
o C MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
o C MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
o C MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
o C MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
o C MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
o C MSR_IA32_APIC_BASE_REGISTER
o C MSR_IA32_BIOS_SIGN_ID_REGISTER
o C MSR_IA32_BNDCFGS_REGISTER
o C MSR_IA32_CLOCK_MODULATION_REGISTER
o C MSR_IA32_DCA_0_CAP_REGISTER
o C MSR_IA32_DEBUG_INTERFACE_REGISTER
o C MSR_IA32_DEBUGCTL_REGISTER
o C MSR_IA32_EFER_REGISTER
o C MSR_IA32_ENERGY_PERF_BIAS_REGISTER
o C MSR_IA32_FEATURE_CONTROL_REGISTER
o C MSR_IA32_FIXED_CTR_CTRL_REGISTER
o C MSR_IA32_HWP_CAPABILITIES_REGISTER
o C MSR_IA32_HWP_INTERRUPT_REGISTER
o C MSR_IA32_HWP_REQUEST_PKG_REGISTER
o C MSR_IA32_HWP_REQUEST_REGISTER
o C MSR_IA32_HWP_STATUS_REGISTER
o C MSR_IA32_L2_QOS_CFG_REGISTER
o C MSR_IA32_L3_QOS_CFG_REGISTER
o C MSR_IA32_MC_CTL2_REGISTER
o C MSR_IA32_MCG_CAP_REGISTER
o C MSR_IA32_MCG_EXT_CTL_REGISTER
o C MSR_IA32_MCG_STATUS_REGISTER
o C MSR_IA32_MISC_ENABLE_REGISTER
o C MSR_IA32_MTRR_DEF_TYPE_REGISTER
o C MSR_IA32_MTRR_PHYSBASE_REGISTER
o C MSR_IA32_MTRR_PHYSMASK_REGISTER
o C MSR_IA32_MTRRCAP_REGISTER
o C MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
o C MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
o C MSR_IA32_PAT_REGISTER
o C MSR_IA32_PEBS_ENABLE_REGISTER
o C MSR_IA32_PERF_CAPABILITIES_REGISTER
o C MSR_IA32_PERF_CTL_REGISTER
o C MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
o C MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
o C MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
o C MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
o C MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
o C MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
o C MSR_IA32_PERF_STATUS_REGISTER
o C MSR_IA32_PERFEVTSEL_REGISTER
o C MSR_IA32_PKG_HDC_CTL_REGISTER
o C MSR_IA32_PLATFORM_ID_REGISTER
o C MSR_IA32_PM_CTL1_REGISTER
o C MSR_IA32_PM_ENABLE_REGISTER
o C MSR_IA32_PQR_ASSOC_REGISTER
o C MSR_IA32_QM_CTR_REGISTER
o C MSR_IA32_QM_EVTSEL_REGISTER
o C MSR_IA32_RTIT_ADDR_REGISTER
o C MSR_IA32_RTIT_CR3_MATCH_REGISTER
o C MSR_IA32_RTIT_CTL_REGISTER
o C MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
o C MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
o C MSR_IA32_RTIT_STATUS_REGISTER
o C MSR_IA32_SGX_SVN_STATUS_REGISTER
o C MSR_IA32_SMM_MONITOR_CTL_REGISTER
o C MSR_IA32_SMRR_PHYSBASE_REGISTER
o C MSR_IA32_SMRR_PHYSMASK_REGISTER
o C MSR_IA32_SYSENTER_CS_REGISTER
o C MSR_IA32_THERM_INTERRUPT_REGISTER
o C MSR_IA32_THERM_STATUS_REGISTER
o C MSR_IA32_TSC_AUX_REGISTER
o C MSR_IA32_VMX_BASIC_REGISTER
o C MSR_IA32_XSS_REGISTER
o C MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
o C MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
o C MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
o C MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
o C MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER
o C MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
o C MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER
o C MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER
o C MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
o C MSR_IVY_BRIDGE_PPIN_CTL_REGISTER
o C MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER
o C MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
o C MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER
o C MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
o C MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
o C MSR_NEHALEM_LBR_SELECT_REGISTER
o C MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
o C MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
o C MSR_NEHALEM_PEBS_ENABLE_REGISTER
o C MSR_NEHALEM_PEBS_LD_LAT_REGISTER
o C MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
o C MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER
o C MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_NEHALEM_PLATFORM_ID_REGISTER
o C MSR_NEHALEM_PLATFORM_INFO_REGISTER
o C MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
o C MSR_NEHALEM_POWER_CTL_REGISTER
o C MSR_NEHALEM_SMI_COUNT_REGISTER
o C MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
o C MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
o C MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
o C MSR_P6_APIC_BASE_REGISTER
o C MSR_P6_BBL_CR_ADDR_REGISTER
o C MSR_P6_BBL_CR_CTL3_REGISTER
o C MSR_P6_BBL_CR_CTL_REGISTER
o C MSR_P6_DEBUGCTLMSR_REGISTER
o C MSR_P6_EBL_CR_POWERON_REGISTER
o C MSR_P6_IA32_PLATFORM_ID_REGISTER
o C MSR_P6_MC_STATUS_REGISTER
o C MSR_P6_MTRRDEFTYPE_REGISTER
o C MSR_P6_PERFEVTSEL_REGISTER
o C MSR_P6_TEST_CTL_REGISTER
o C MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER
o C MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
o C MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
o C MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
o C MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
o C MSR_PENTIUM_4_MCG_MISC_REGISTER
o C MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
o C MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
o C MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
o C MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
o C MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
o C MSR_PENTIUM_M_THERM2_CTL_REGISTER
o C MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
o C MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
o C MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
o C MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
o C MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
o C MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
o C MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
o C MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
o C MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
o C MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
o C MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
o C MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
o C MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
o C MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
o C MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
o C MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
o C MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
o C MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
o C MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
o C MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
o C MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
o C MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
o C MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
o C MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
o C MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
o C MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
o C MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
o C MSR_SEV_STATUS_REGISTER
o C MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
o C MSR_SILVERMONT_EBL_CR_POWERON_REGISTER
o C MSR_SILVERMONT_FEATURE_CONFIG_REGISTER
o C MSR_SILVERMONT_FSB_FREQ_REGISTER
o C MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER
o C MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER
o C MSR_SILVERMONT_LBR_SELECT_REGISTER
o C MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER
o C MSR_SILVERMONT_PEBS_ENABLE_REGISTER
o C MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
o C MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
o C MSR_SILVERMONT_PLATFORM_ID_REGISTER
o C MSR_SILVERMONT_PLATFORM_INFO_REGISTER
o C MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER
o C MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER
o C MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER
o C MSR_SILVERMONT_SMI_COUNT_REGISTER
o C MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER
o C MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER
o C MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
o C MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
o C MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
o C MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER
o C MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
o C MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER
o C MSR_SKYLAKE_IA32_MCG_CAP_REGISTER
o C MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER
o C MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
o C MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
o C MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER
o C MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER
o C MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER
o C MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
o C MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
o C MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
o C MSR_SKYLAKE_PLATFORM_INFO_REGISTER
o C MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
o C MSR_SKYLAKE_POWER_CTL_REGISTER
o C MSR_SKYLAKE_PPIN_CTL_REGISTER
o C MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
o C MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
o C MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
o C MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER
o C MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
o C MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER
o C MSR_SKYLAKE_SMM_MCA_CAP_REGISTER
o C MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER
o C MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
o C MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
o C MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
o C MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER
o C MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
o C MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
o C MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
o C MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
o C MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER
o C MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
o C MSR_XEON_5600_FEATURE_CONFIG_REGISTER
o C MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
o C MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
o C MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
o C MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
o C MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
o C MSR_XEON_D_IA32_MCG_CAP_REGISTER
o C MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
o C MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
o C MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER
o C MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_XEON_D_PLATFORM_INFO_REGISTER
o C MSR_XEON_D_PPIN_CTL_REGISTER
o C MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
o C MSR_XEON_D_SMM_MCA_CAP_REGISTER
o C MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
o C MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
o C MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
o C MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
o C MSR_XEON_E7_FEATURE_CONFIG_REGISTER
o C MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
o C MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
o C MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
o C MSR_XEON_PHI_LBR_SELECT_REGISTER
o C MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
o C MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
o C MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
o C MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
o C MSR_XEON_PHI_PLATFORM_INFO_REGISTER
o C MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
o C MSR_XEON_PHI_PPIN_CTL_REGISTER
o C MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
o C MSR_XEON_PHI_SMI_COUNT_REGISTER
o C MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
o C MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
o C MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
o C MTRR_CONTEXT
o C MTRR_LIB_ADDRESS
o C MTRR_MEMORY_RANGE
o C PAGE_ATTRIBUTE_TABLE
o C PAGE_MAP_AND_DIRECTORY_POINTER
o C PAGE_TABLE_1G_ENTRY
o C PAGE_TABLE_ENTRY
o C PAGE_TABLE_LIB_PAGING_CONTEXT
o C PAGE_TABLE_LIB_PAGING_CONTEXT_DATA
o C PAGE_TABLE_LIB_PAGING_CONTEXT_IA32
o C PAGE_TABLE_LIB_PAGING_CONTEXT_X64
o C PAGE_TABLE_POOL
o C PROC_TRACE_DATA
o C PROC_TRACE_PROCESSOR_DATA
o C PROC_TRACE_TOPA_TABLE
o C PROCESSOR_SMM_DESCRIPTOR
o C PROGRAM_CPU_REGISTER_FLAGS
o C REGISTER_CPU_FEATURE_INFORMATION
o C RESERVED_VECTORS_DATA
o C RTIT_TOPA_TABLE_ENTRY
o C SMM_COMMUNICATE_HEADER_32
o C SMM_COMMUNICATE_HEADER_64
o C SMM_CPU_DATA_BLOCK
o C SMM_CPU_PRIVATE_DATA
o C SMM_CPU_SEMAPHORE_CPU
o C SMM_CPU_SEMAPHORE_GLOBAL
o C SMM_CPU_SEMAPHORES
o C SMM_DISPATCHER_MP_SYNC_DATA
o C SMM_PROFILE_ENTRY
o C SMM_PROFILE_HEADER
o C SMRAM_SAVE_STATE_IOMISC
o C SMRAM_SAVE_STATE_MAP
o C SMRAM_SAVE_STATE_MAP32
o C SMRAM_SAVE_STATE_MAP64
o C SOFTWARE_STM_HEADER
o C STM_ADDRESS_LOOKUP_DESCRIPTOR
o C STM_EVENT_LOG_MANAGEMENT_REQUEST
o C STM_FEAT
o C STM_HEADER
o C STM_LOG_ENTRY
o C STM_MAP_ADDRESS_RANGE_DESCRIPTOR
o C STM_PCI_DEVICE_PATH_NODE
o C STM_PROTECTION_EXCEPTION_HANDLER
o C STM_PROTECTION_EXCEPTION_STACK_FRAME
o C STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32
o C STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
o C STM_REGISTER_VIOLATION_DESC
o C STM_RSC
o C STM_RSC_ALL_RESOURCES_DESC
o C STM_RSC_DESC_HEADER
o C STM_RSC_END
o C STM_RSC_IO_DESC
o C STM_RSC_MEM_DESC
o C STM_RSC_MMIO_DESC
o C STM_RSC_MSR_DESC
o C STM_RSC_PCI_CFG_DESC
o C STM_RSC_TRAPPED_IO_DESC
o C STM_SMM_ENTRY_STATE
o C STM_SMM_RESUME_STATE
o C STM_SMM_STATE
o C STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR
o C STM_VMCS_DATABASE_REQUEST
o C TXT_PROCESSOR_SMM_DESCRIPTOR
\ C VARIABLE_MTRR
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _ACPI_RESET_STRUCTURE Struct Reference

  • Files
  • Data Structures
  • Data Structure Index
  • Data Fields
Data Fields
_ACPI_RESET_STRUCTURE Struct Reference

Data Fields

UINT64 | Addess
UINT8 | Type
UINT8 | AccessSize
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _BRANCH_TRACE_RECORD Struct Reference

  • Data Fields
Data Fields
_BRANCH_TRACE_RECORD Struct Reference

Data Fields

UINT32 | LastBranchFrom
UINT32 | LastBranchTo
UINT32 | Rsvd0: 4
UINT32 | BranchPredicted: 1
UINT32 | Rsvd1: 27
UINT64 | LastBranchFrom
UINT64 | LastBranchTo
UINT64 | Rsvd0: 4
UINT64 | BranchPredicted: 1
UINT64 | Rsvd1: 59
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _CPU_MP_DATA Struct Reference

Data Fields
_CPU_MP_DATA Struct Reference

Data Fields

UINT64 | CpuInfoInHob
UINT32 | CpuCount
UINT32 | BspNumber
SPIN_LOCK | MpLock
UINTN | Buffer
UINTN | CpuApStackSize
MP_ASSEMBLY_ADDRESS_MAP | AddressMap
UINTN | WakeupBuffer
UINTN | WakeupBufferHigh
UINTN | BackupBuffer
UINTN | BackupBufferSize
volatile UINT32 | FinishedCount
UINT32 | RunningCount
BOOLEAN | SingleThread
EFI_AP_PROCEDURE | Procedure
VOID * | ProcArguments
BOOLEAN * | Finished
UINT64 | ExpectedTime
UINT64 | CurrentTime
UINT64 | TotalTime
EFI_EVENT | WaitEvent
UINTN ** | FailedCpuList
AP_INIT_STATE | InitFlag
BOOLEAN | X2ApicEnable
BOOLEAN | SwitchBspFlag
UINTN | NewBspNumber
CPU_EXCHANGE_ROLE_INFO | BSPInfo
CPU_EXCHANGE_ROLE_INFO | APInfo
MTRR_SETTINGS | MtrrTable
UINT8 | ApLoopMode
UINT8 | ApTargetCState
UINT16 | PmCodeSegment
CPU_AP_DATA * | CpuData
volatile MP_CPU_EXCHANGE_INFO * | MpCpuExchangeInfo
UINT32 | CurrentTimerCount
UINTN | DivideValue
UINT8 | Vector
BOOLEAN | PeriodicMode
BOOLEAN | TimerInterruptState
UINT64 | MicrocodePatchAddress
UINT64 | MicrocodePatchRegionSize
UINT32 | ProcessorSignature
UINT32 | ProcessorFlags
UINT64 | MicrocodeDataAddress
UINT32 | MicrocodeRevision
BOOLEAN | WakeUpByInitSipiSipi
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _EFI_SM_MONITOR_INIT_PROTOCOL Struct Reference

Data Fields
_EFI_SM_MONITOR_INIT_PROTOCOL Struct Reference

Data Fields

EFI_SM_MONITOR_LOAD_MONITOR | LoadMonitor
EFI_SM_MONITOR_ADD_PI_RESOURCE | AddPiResource
EFI_SM_MONITOR_DELETE_PI_RESOURCE | DeletePiResource
EFI_SM_MONITOR_GET_PI_RESOURCE | GetPiResource
EFI_SM_MONITOR_GET_MONITOR_STATE | GetMonitorState
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Protocol/SmMonitorInit.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _EFI_SMM_CPU_SERVICE_PROTOCOL Struct Reference

Data Fields
_EFI_SMM_CPU_SERVICE_PROTOCOL Struct Reference

Data Fields

EFI_SMM_GET_PROCESSOR_INFO | GetProcessorInfo
EFI_SMM_SWITCH_BSP | SwitchBsp
EFI_SMM_ADD_PROCESSOR | AddProcessor
EFI_SMM_REMOVE_PROCESSOR | RemoveProcessor
EFI_SMM_WHOAMI | WhoAmI
EFI_SMM_REGISTER_EXCEPTION_HANDLER | RegisterExceptionHandler
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Protocol/SmmCpuService.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _GDT_ENTRIES Struct Reference

Data Fields
_GDT_ENTRIES Struct Reference

Data Fields

GDT_ENTRY | Null
GDT_ENTRY | Linear
GDT_ENTRY | LinearCode
GDT_ENTRY | SysData
GDT_ENTRY | SysCode
GDT_ENTRY | Spare4
GDT_ENTRY | LinearData64
GDT_ENTRY | LinearCode64
GDT_ENTRY | Spare5
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuGdt.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _GDT_ENTRY Struct Reference

Data Fields
_GDT_ENTRY Struct Reference

Data Fields

UINT16 | Limit15_0
UINT16 | Base15_0
UINT8 | Base23_16
UINT8 | Type
UINT8 | Limit19_16_and_flags
UINT8 | Base31_24
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuGdt.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _MSR_DS_AREA_STRUCT Struct Reference

Data Fields
_MSR_DS_AREA_STRUCT Struct Reference

Data Fields

UINT32 | BTSBufferBase
UINT32 | BTSIndex
UINT32 | BTSAbsoluteMaximum
UINT32 | BTSInterruptThreshold
UINT32 | PEBSBufferBase
UINT32 | PEBSIndex
UINT32 | PEBSAbsoluteMaximum
UINT32 | PEBSInterruptThreshold
UINT32 | PEBSCounterReset [4]
UINT32 | Reserved
UINT64 | BTSBufferBase
UINT64 | BTSIndex
UINT64 | BTSAbsoluteMaximum
UINT64 | BTSInterruptThreshold
UINT64 | PEBSBufferBase
UINT64 | PEBSIndex
UINT64 | PEBSAbsoluteMaximum
UINT64 | PEBSInterruptThreshold
UINT64 | PEBSCounterReset [2]
UINT64 | Reserved
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _MTRR_FIXED_SETTINGS_ Struct Reference

Data Fields
_MTRR_FIXED_SETTINGS_ Struct Reference

Data Fields

UINT64 Mtrr [MTRR_NUMBER_OF_FIXED_MTRR]
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _MTRR_SETTINGS_ Struct Reference

Data Fields
_MTRR_SETTINGS_ Struct Reference

Data Fields

MTRR_FIXED_SETTINGS | Fixed
MTRR_VARIABLE_SETTINGS | Variables
UINT64 | MtrrDefType
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _MTRR_VARIABLE_SETTING_ Struct Reference

Data Fields
_MTRR_VARIABLE_SETTING_ Struct Reference

Data Fields

UINT64 | Base
UINT64 | Mask
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _MTRR_VARIABLE_SETTINGS_ Struct Reference

Data Fields
_MTRR_VARIABLE_SETTINGS_ Struct Reference

Data Fields

MTRR_VARIABLE_SETTING Mtrr [MTRR_NUMBER_OF_VARIABLE_MTRR]
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _PEBS_RECORD Struct Reference

Data Fields
_PEBS_RECORD Struct Reference

Data Fields

UINT32 | Eflags
UINT32 | LinearIP
UINT32 | Eax
UINT32 | Ebx
UINT32 | Ecx
UINT32 | Edx
UINT32 | Esi
UINT32 | Edi
UINT32 | Ebp
UINT32 | Esp
UINT64 | Rflags
UINT64 | LinearIP
UINT64 | Rax
UINT64 | Rbx
UINT64 | Rcx
UINT64 | Rdx
UINT64 | Rsi
UINT64 | Rdi
UINT64 | Rbp
UINT64 | Rsp
UINT64 | R8
UINT64 | R9
UINT64 | R10
UINT64 | R11
UINT64 | R12
UINT64 | R13
UINT64 | R14
UINT64 | R15
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _SEC_IDT_TABLE Struct Reference

Data Fields
_SEC_IDT_TABLE Struct Reference

Data Fields

UINT64 | PeiService
UINT64 | IdtTable [SEC_IDT_ENTRY_COUNT]
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/SecCore/SecMain.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: _SMM_SUPERVISOR_PROTOCOL Struct Reference

Data Fields
_SMM_SUPERVISOR_PROTOCOL Struct Reference

Data Fields

UINT32 | Version
UINT32 | SmiHandlerSize
UINTN | ErrorReportJumpBuffer
SMM_SV_INSTALL_SMI_HANDLER | InstallSmiHandler
UINTN | InstallErrorReporter
UINTN | TurnOnSmmIsoAtSmmReadyToLock
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ACPI_CPU_DATA Struct Reference

Data Fields
ACPI_CPU_DATA Struct Reference

Data Fields

EFI_PHYSICAL_ADDRESS | StartupVector
EFI_PHYSICAL_ADDRESS | GdtrProfile
EFI_PHYSICAL_ADDRESS | IdtrProfile
EFI_PHYSICAL_ADDRESS | StackAddress
UINT32 | StackSize
UINT32 | NumberOfCpus
EFI_PHYSICAL_ADDRESS | MtrrTable
EFI_PHYSICAL_ADDRESS | PreSmmInitRegisterTable
EFI_PHYSICAL_ADDRESS | RegisterTable
EFI_PHYSICAL_ADDRESS | ApMachineCheckHandlerBase
UINT32 | ApMachineCheckHandlerSize
CPU_STATUS_INFORMATION | CpuStatus
EFI_PHYSICAL_ADDRESS | ApLocation
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/AcpiCpuData.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ACPI_CPU_DATA_EX Struct Reference

Data Fields
ACPI_CPU_DATA_EX Struct Reference

Data Fields

ACPI_CPU_DATA | AcpiCpuData
MTRR_SETTINGS | MtrrTable
IA32_DESCRIPTOR | GdtrProfile
IA32_DESCRIPTOR | IdtrProfile
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: AMD_X64_FORMAT Struct Reference

Data Fields
AMD_X64_FORMAT Struct Reference

Data Fields

UINT16 | SaveStateOffset
UINT16 | SaveStateWidth
BOOLEAN | ReadOnly
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_AP_DATA Struct Reference

Data Fields
CPU_AP_DATA Struct Reference

Data Fields

SPIN_LOCK | ApLock
volatile UINT32 * | StartupApSignal
volatile UINTN | ApFunction
volatile UINTN | ApFunctionArgument
BOOLEAN | CpuHealthy
volatile CPU_STATE | State
CPU_VOLATILE_REGISTERS | VolatileRegisters
BOOLEAN | Waiting
BOOLEAN * | Finished
UINT64 | ExpectedTime
UINT64 | CurrentTime
UINT64 | TotalTime
EFI_EVENT | WaitEvent
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_EXCHANGE_ROLE_INFO Struct Reference

Data Fields
CPU_EXCHANGE_ROLE_INFO Struct Reference

Data Fields

UINT8 | State
UINTN | StackPointer
IA32_DESCRIPTOR | Gdtr
IA32_DESCRIPTOR | Idtr
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_FEATURES_DATA Struct Reference

Data Fields
CPU_FEATURES_DATA Struct Reference

Data Fields

UINTN | FeaturesCount
UINT32 | BitMaskSize
LIST_ENTRY | FeatureList
CPU_FEATURES_INIT_ORDER * | InitOrder
UINT8 * | SupportPcd
UINT8 * | CapabilityPcd
UINT8 * | ConfigurationPcd
UINT8 * | SettingPcd
UINT32 | NumberOfCpus
ACPI_CPU_DATA * | AcpiCpuData
CPU_REGISTER_TABLE * | RegisterTable
CPU_REGISTER_TABLE * | PreSmmRegisterTable
UINTN | BspNumber
PROGRAM_CPU_REGISTER_FLAGS | CpuFlags
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_FEATURES_ENTRY Struct Reference

Data Fields
CPU_FEATURES_ENTRY Struct Reference

Data Fields

UINT32 | Signature
LIST_ENTRY | Link
UINT8 * | FeatureMask
CHAR8 * | FeatureName
CPU_FEATURE_GET_CONFIG_DATA | GetConfigDataFunc
CPU_FEATURE_SUPPORT | SupportFunc
CPU_FEATURE_INITIALIZE | InitializeFunc
UINT8 * | BeforeFeatureBitMask
UINT8 * | AfterFeatureBitMask
UINT8 * | CoreBeforeFeatureBitMask
UINT8 * | CoreAfterFeatureBitMask
UINT8 * | PackageBeforeFeatureBitMask
UINT8 * | PackageAfterFeatureBitMask
VOID * | ConfigData
BOOLEAN | BeforeAll
BOOLEAN | AfterAll
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_FEATURES_INIT_ORDER Struct Reference

Data Fields
CPU_FEATURES_INIT_ORDER Struct Reference

Data Fields

REGISTER_CPU_FEATURE_INFORMATION | CpuInfo
UINT8 * | FeaturesSupportedMask
LIST_ENTRY | OrderList
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_HOT_PLUG_DATA Struct Reference

Data Fields
CPU_HOT_PLUG_DATA Struct Reference

Data Fields

UINT32 | Revision
UINT32 | ArrayLength
UINT64 * | ApicId
UINTN * | SmBase
UINT32 | Reserved
UINT32 | SmrrBase
UINT32 | SmrrSize
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/CpuHotPlugData.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_INFO_IN_HOB Struct Reference

Data Fields
CPU_INFO_IN_HOB Struct Reference

Data Fields

UINT32 | InitialApicId
UINT32 | ApicId
UINT32 | Health
UINT64 | ApTopOfStack
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_MICROCODE_DATE Union Reference

Data Fields
CPU_MICROCODE_DATE Union Reference

#include <Microcode.h>

Data Fields

struct {
UINT32 Year:16
UINT32 Day:8
UINT32 Month:8
} Bits
UINT32 Uint32

Detailed Description

CPU Microcode Date in BCD format

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Microcode.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_MICROCODE_EXTENDED_TABLE Struct Reference

Data Fields
CPU_MICROCODE_EXTENDED_TABLE Struct Reference

#include <Microcode.h>

Data Fields

CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature
UINT32 | ProcessorFlag
UINT32 | Checksum

Detailed Description

Extended Signature Table Field Definitions

Field Documentation

UINT32 CPU_MICROCODE_EXTENDED_TABLE::Checksum

Used by utility software to decompose a microcode update into multiple microcode updates where each of the new updates is constructed without the optional Extended Processor Signature Table. To calculate the Checksum, substitute the Primary Processor Signature entry and the Processor Flags entry with the corresponding Extended Patch entry. Delete the Extended Processor Signature Table entries. The Checksum is correct when the summation of all DWORDs that comprise the created Extended Processor Patch results in 00000000H.

UINT32 CPU_MICROCODE_EXTENDED_TABLE::ProcessorFlag

Platform type information is encoded in the lower 8 bits of this 4- byte field. Each bit represents a particular platform type for a given CPUID. The BIOS uses the processor flags field in conjunction with the platform Id bits in MSR (17H) to determine whether or not an update is appropriate to load on a processor. Multiple bits may be set representing support for multiple platform IDs.

CPU_MICROCODE_PROCESSOR_SIGNATURE CPU_MICROCODE_EXTENDED_TABLE::ProcessorSignature

Extended family, extended model, type, family, model, and stepping of processor that requires this particular update revision (e.g., 00000650H). Each microcode update is designed specifically for a given extended family, extended model, type, family, model, and stepping of the processor. The BIOS uses the processor signature field in conjunction with the CPUID instruction to determine whether or not an update is appropriate to load on a processor. The information encoded within this field exactly corresponds to the bit representations returned by the CPUID instruction.

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/Microcode.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_MICROCODE_EXTENDED_TABLE_HEADER Struct Reference

Data Fields
CPU_MICROCODE_EXTENDED_TABLE_HEADER Struct Reference

#include <Microcode.h>

Data Fields

UINT32 | ExtendedSignatureCount
UINT32 | ExtendedChecksum
UINT8 | Reserved [12]

Detailed Description

Extended Signature Table Header Field Definitions

Field Documentation

UINT32 CPU_MICROCODE_EXTENDED_TABLE_HEADER::ExtendedChecksum

Checksum of update extended processor signature table. Used to verify the integrity of the extended processor signature table. Checksum is correct when the summation of the DWORDs that comprise the extended processor signature table results in 00000000H.

UINT32 CPU_MICROCODE_EXTENDED_TABLE_HEADER::ExtendedSignatureCount

Specifies the number of extended signature structures (Processor Signature[n], processor flags[n] and checksum[n]) that exist in this microcode update

UINT8 CPU_MICROCODE_EXTENDED_TABLE_HEADER::Reserved[12]

Reserved fields.

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/Microcode.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_MICROCODE_HEADER Struct Reference

Data Fields
CPU_MICROCODE_HEADER Struct Reference

#include <Microcode.h>

Data Fields

UINT32 | HeaderVersion
UINT32 | UpdateRevision
CPU_MICROCODE_DATE Date
CPU_MICROCODE_PROCESSOR_SIGNATURE ProcessorSignature
UINT32 | Checksum
UINT32 | LoaderRevision
UINT32 | ProcessorFlags
UINT32 | DataSize
UINT32 | TotalSize
UINT8 | Reserved [12]

Detailed Description

Microcode Update Format definition

Field Documentation

UINT32 CPU_MICROCODE_HEADER::Checksum

Checksum of Update Data and Header. Used to verify the integrity of the update header and data. Checksum is correct when the summation of all the DWORDs (including the extended Processor Signature Table) that comprise the microcode update result in 00000000H.

UINT32 CPU_MICROCODE_HEADER::DataSize

Specifies the size of the encrypted data in bytes, and must be a multiple of DWORDs. If this value is 00000000H, then the microcode update encrypted data is 2000 bytes (or 500 DWORDs).

CPU_MICROCODE_DATE CPU_MICROCODE_HEADER::Date

Date of the update creation in binary format: mmddyyyy (e.g. 07/18/98 is 07181998H).

UINT32 CPU_MICROCODE_HEADER::HeaderVersion

Version number of the update header

UINT32 CPU_MICROCODE_HEADER::LoaderRevision

Version number of the loader program needed to correctly load this update. The initial version is 00000001H

UINT32 CPU_MICROCODE_HEADER::ProcessorFlags

Platform type information is encoded in the lower 8 bits of this 4- byte field. Each bit represents a particular platform type for a given CPUID. The BIOS uses the processor flags field in conjunction with the platform Id bits in MSR (17H) to determine whether or not an update is appropriate to load on a processor. Multiple bits may be set representing support for multiple platform IDs.

CPU_MICROCODE_PROCESSOR_SIGNATURE CPU_MICROCODE_HEADER::ProcessorSignature

Extended family, extended model, type, family, model, and stepping of processor that requires this particular update revision (e.g., 00000650H). Each microcode update is designed specifically for a given extended family, extended model, type, family, model, and stepping of the processor. The BIOS uses the processor signature field in conjunction with the CPUID instruction to determine whether or not an update is appropriate to load on a processor. The information encoded within this field exactly corresponds to the bit representations returned by the CPUID instruction.

UINT8 CPU_MICROCODE_HEADER::Reserved[12]

Reserved fields for future expansion.

UINT32 CPU_MICROCODE_HEADER::TotalSize

Specifies the total size of the microcode update in bytes. It is the summation of the header size, the encrypted data size and the size of the optional extended signature table. This value is always a multiple of 1024.

UINT32 CPU_MICROCODE_HEADER::UpdateRevision

Unique version number for the update, the basis for the update signature provided by the processor to indicate the current update functioning within the processor. Used by the BIOS to authenticate the update and verify that the processor loads successfully. The value in this field cannot be used for processor stepping identification alone. This is a signed 32-bit number.

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/Microcode.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_MICROCODE_PROCESSOR_SIGNATURE Union Reference

Data Fields
CPU_MICROCODE_PROCESSOR_SIGNATURE Union Reference

#include <Microcode.h>

Data Fields

struct {
UINT32 Stepping:4
UINT32 Model:4
UINT32 Family:4
UINT32 Type:2
UINT32 Reserved1:2
UINT32 ExtendedModel:4
UINT32 ExtendedFamily:8
UINT32 Reserved2:4
} Bits
UINT32 Uint32

Detailed Description

CPU Microcode Processor Signature format

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Microcode.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_REGISTER_TABLE Struct Reference

Data Fields
CPU_REGISTER_TABLE Struct Reference

Data Fields

UINT32 | TableLength
UINT32 | NumberBeforeReset
UINT32 | AllocatedSize
UINT32 | InitialApicId
EFI_PHYSICAL_ADDRESS | RegisterTableEntry
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/AcpiCpuData.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_REGISTER_TABLE_ENTRY Struct Reference

Data Fields
CPU_REGISTER_TABLE_ENTRY Struct Reference

Data Fields

REGISTER_TYPE | RegisterType
UINT32 | Index
UINT8 | ValidBitStart
UINT8 | ValidBitLength
UINT16 | Reserved
UINT32 | HighIndex
UINT64 | Value
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/AcpiCpuData.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_SMM_SAVE_STATE_IO_WIDTH Struct Reference

Data Fields
CPU_SMM_SAVE_STATE_IO_WIDTH Struct Reference

Data Fields

UINT8 | Width
EFI_SMM_SAVE_STATE_IO_WIDTH | IoWidth

Detailed Description

Structure used to build a lookup table for the IOMisc width information

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_SMM_SAVE_STATE_LOOKUP_ENTRY Struct Reference

Data Fields
CPU_SMM_SAVE_STATE_LOOKUP_ENTRY Struct Reference

Data Fields

UINT8 | Width32
UINT8 | Width64
UINT16 | Offset32
UINT16 | Offset64Lo
UINT16 | Offset64Hi
BOOLEAN | Writeable
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_SMM_SAVE_STATE_REGISTER_RANGE Struct Reference

Data Fields
CPU_SMM_SAVE_STATE_REGISTER_RANGE Struct Reference

Data Fields

EFI_SMM_SAVE_STATE_REGISTER | Start
EFI_SMM_SAVE_STATE_REGISTER | End
UINTN | Length

Detailed Description

Structure used to describe a range of registers

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_STATUS_CODE_TEMPLATE Struct Reference

Data Fields
CPU_STATUS_CODE_TEMPLATE Struct Reference

Data Fields

EFI_STATUS_CODE_DATA | Header
EFI_SYSTEM_CONTEXT_IA32 | SystemContext
EFI_SYSTEM_CONTEXT_X64 | SystemContext
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_STATUS_INFORMATION Struct Reference

Data Fields
CPU_STATUS_INFORMATION Struct Reference

Data Fields

UINT32 | PackageCount
UINT32 | MaxCoreCount
UINT32 | MaxThreadCount
EFI_PHYSICAL_ADDRESS | ValidCoreCountPerPackage
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/AcpiCpuData.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPU_VOLATILE_REGISTERS Struct Reference

Data Fields
CPU_VOLATILE_REGISTERS Struct Reference

Data Fields

UINTN | Cr0
UINTN | Cr3
UINTN | Cr4
UINTN | Dr0
UINTN | Dr1
UINTN | Dr2
UINTN | Dr3
UINTN | Dr6
UINTN | Dr7
IA32_DESCRIPTOR | Gdtr
IA32_DESCRIPTOR | Idtr
UINT16 | Tr
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_EXTENDED_CPU_SIG_EAX Union Reference

Data Fields
CPUID_AMD_EXTENDED_CPU_SIG_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Stepping:4
UINT32 BaseModel:4
UINT32 BaseFamily:4
UINT32 Reserved1:4
UINT32 ExtModel:4
UINT32 ExtFamily:8
UINT32 Reserved2:4
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Processor Signature and Features

Parameters
EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
Return values
EAX | Extended Family, Model, Stepping Identifiers described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
EBX | Brand Identifier described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
ECX | Extended Feature Identifiers described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
EDX | Extended Feature Identifiers described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX. CPUID Extended Processor Signature and Features EAX for CPUID leaf #CPUID_EXTENDED_CPU_SIG.

Field Documentation

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::BaseFamily

[Bits 11:8] Base Family.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::BaseModel

[Bits 7:4] Base Model.

struct { ... } CPUID_AMD_EXTENDED_CPU_SIG_EAX::Bits

Individual bit fields

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::ExtFamily

[Bits 27:20] Extended Family.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::ExtModel

[Bits 19:16] Extended Model.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::Reserved1

[Bit 15:12] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::Reserved2

[Bit 31:28] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::Stepping

[Bits 3:0] Stepping.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_EXTENDED_CPU_SIG_EBX Union Reference

Data Fields
CPUID_AMD_EXTENDED_CPU_SIG_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved:28
UINT32 PkgType:4
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Processor Signature and Features EBX for CPUID leaf #CPUID_EXTENDED_CPU_SIG.

Field Documentation

struct { ... } CPUID_AMD_EXTENDED_CPU_SIG_EBX::Bits

Individual bit fields

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EBX::PkgType

[Bit 31:28] Package Type.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EBX::Reserved

[Bits 27:0] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_EXTENDED_CPU_SIG_ECX Union Reference

Data Fields
CPUID_AMD_EXTENDED_CPU_SIG_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 LAHF_SAHF:1
UINT32 CmpLegacy:1
UINT32 SVM:1
UINT32 ExtApicSpace:1
UINT32 AltMovCr8:1
UINT32 LZCNT:1
UINT32 SSE4A:1
UINT32 MisAlignSse:1
UINT32 PREFETCHW:1
UINT32 OSVW:1
UINT32 IBS:1
UINT32 XOP:1
UINT32 SKINIT:1
UINT32 WDT:1
UINT32 Reserved1:1
UINT32 LWP:1
UINT32 FMA4:1
UINT32 TCE:1
UINT32 Reserved2:4
UINT32 TopologyExtensions:1
UINT32 PerfCtrExtCore:1
UINT32 Reserved3:2
UINT32 DataBreakpointExtension:1
UINT32 PerfTsc:1
UINT32 PerfCtrExtL3:1
UINT32 MwaitExtended:1
UINT32 Reserved4:2
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Processor Signature and Features ECX for CPUID leaf #CPUID_EXTENDED_CPU_SIG.

Field Documentation

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::AltMovCr8

[Bit 4] LOCK MOV CR0 means MOV CR8.

struct { ... } CPUID_AMD_EXTENDED_CPU_SIG_ECX::Bits

Individual bit fields

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::CmpLegacy

[Bit 1] Core multi-processing legacy mode.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::DataBreakpointExtension

[Bit 26] Data Breakpoint Extension.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::ExtApicSpace

[Bit 3] Extended APIC register space.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::FMA4

[Bit 16] 4-Operand FMA instruction support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::IBS

[Bit 10] Instruction Based Sampling.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::LAHF_SAHF

[Bit 0] LAHF/SAHF available in 64-bit mode.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::LWP

[Bit 15] Lightweight Profiling support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::LZCNT

[Bit 5] LZCNT instruction support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::MisAlignSse

[Bit 7] Misaligned SSE Mode.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::MwaitExtended

[Bit 29] MWAITX and MONITORX capability.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::OSVW

[Bit 9] OS Visible Work-around support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::PerfCtrExtCore

[Bit 23] Core Performance Counter Extensions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::PerfCtrExtL3

[Bit 28] L3 Performance Counter Extensions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::PerfTsc

[Bit 27] Performance Time-Stamp Counter.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::PREFETCHW

[Bit 8] ThreeDNow Prefetch instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::Reserved1

[Bit 14] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::Reserved2

[Bit 21:18] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::Reserved3

[Bit 25:24] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::Reserved4

[Bit 31:30] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::SKINIT

[Bit 12] SKINIT and STGI support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::SSE4A

[Bit 6] SSE4A instruction support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::SVM

[Bit 2] Secure Virtual Mode feature.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::TCE

[Bit 17] Translation Cache Extension.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::TopologyExtensions

[Bit 22] Topology Extensions support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::WDT

[Bit 13] Watchdog Timer support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_ECX::XOP

[Bit 11] Extended Operation Support.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_EXTENDED_CPU_SIG_EDX Union Reference

Data Fields
CPUID_AMD_EXTENDED_CPU_SIG_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 FPU:1
UINT32 VME:1
UINT32 DE:1
UINT32 PSE:1
UINT32 TSC:1
UINT32 MSR:1
UINT32 PAE:1
UINT32 MCE:1
UINT32 CMPXCHG8B:1
UINT32 APIC:1
UINT32 Reserved1:1
UINT32 SYSCALL_SYSRET:1
UINT32 MTRR:1
UINT32 PGE:1
UINT32 MCA:1
UINT32 CMOV:1
UINT32 PAT:1
UINT32 PSE36: 1
UINT32 Reserved2:2
UINT32 NX:1
UINT32 Reserved3:1
UINT32 MmxExt:1
UINT32 MMX:1
UINT32 FFSR:1
UINT32 FFXSR:1
UINT32 Page1GB:1
UINT32 RDTSCP:1
UINT32 Reserved4:1
UINT32 LM:1
UINT32 ThreeDNow:1
UINT32 ThreeDNowExt:1
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Processor Signature and Features EDX for CPUID leaf #CPUID_EXTENDED_CPU_SIG.

Field Documentation

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::APIC

[Bit 9] APIC exists and is enabled.

struct { ... } CPUID_AMD_EXTENDED_CPU_SIG_EDX::Bits

Individual bit fields

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::CMOV

[Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::CMPXCHG8B

[Bit 8] CMPXCHG8B instruction.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::DE

[Bit 2] Debugging extensions, IO breakpoints, CR4.DE.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::FFSR

[Bit 24] FXSAVE and FXRSTOR instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::FFXSR

[Bit 25] FXSAVE and FXRSTOR instruction optimizations.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::FPU

[Bit 0] x87 floating point unit on-chip.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::LM

[Bit 29] Long Mode.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::MCA

[Bit 14] Machine check architecture, MCG_CAP.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::MCE

[Bit 7] Machine check exception, CR4.MCE.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::MMX

[Bit 23] MMX instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::MmxExt

[Bit 22] AMD Extensions to MMX instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::MSR

[Bit 5] MSRs, with RDMSR and WRMSR instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::MTRR

[Bit 12] Memory-type range registers.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::NX

[Bit 20] No-execute page protection.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::PAE

[Bit 6] Physical-address extensions (PAE).

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::Page1GB

[Bit 26] 1-GByte large page support.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::PAT

[Bit 16] Page attribute table.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::PGE

[Bit 13] Page global extension, CR4.PGE.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::PSE

[Bit 3] Page-size extensions (4 MB pages).

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::PSE36

[Bit 17] Page-size extensions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::RDTSCP

[Bit 27] RDTSCP intructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::Reserved1

[Bit 10] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::Reserved2

[Bit 19:18] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::Reserved3

[Bit 21] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::Reserved4

[Bit 28] Reserved.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::SYSCALL_SYSRET

[Bit 11] SYSCALL and SYSRET instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::ThreeDNow

[Bit 30] 3DNow! instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::ThreeDNowExt

[Bit 31] AMD Extensions to 3DNow! instructions.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::TSC

[Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_AMD_EXTENDED_CPU_SIG_EDX::VME

[Bit 1] Virtual-mode enhancements.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_PROCESSOR_TOPOLOGY_EAX Union Reference

Data Fields
CPUID_AMD_PROCESSOR_TOPOLOGY_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 ExtendedApicId
} Bits
UINT32 Uint32

Detailed Description

CPUID AMD Processor Topology EAX for CPUID leaf #CPUID_AMD_PROCESSOR_TOPOLOGY.

Field Documentation

struct { ... } CPUID_AMD_PROCESSOR_TOPOLOGY_EAX::Bits

Individual bit fields

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX::ExtendedApicId

[Bit 31:0] Extended APIC Id.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_PROCESSOR_TOPOLOGY_EBX Union Reference

Data Fields
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CoreId:8
UINT32 ThreadsPerCore:8
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID AMD Processor Topology EBX for CPUID leaf #CPUID_AMD_PROCESSOR_TOPOLOGY.

Field Documentation

struct { ... } CPUID_AMD_PROCESSOR_TOPOLOGY_EBX::Bits

Individual bit fields

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX::CoreId

[Bits 7:0] Core Id.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX::Reserved

[Bit 31:16] Reserved.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX::ThreadsPerCore

[Bits 15:8] Threads per core.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_PROCESSOR_TOPOLOGY_ECX Union Reference

Data Fields
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 NodeId:8
UINT32 NodesPerProcessor:3
UINT32 Reserved:21
} Bits
UINT32 Uint32

Detailed Description

CPUID AMD Processor Topology ECX for CPUID leaf #CPUID_AMD_PROCESSOR_TOPOLOGY.

Field Documentation

struct { ... } CPUID_AMD_PROCESSOR_TOPOLOGY_ECX::Bits

Individual bit fields

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX::NodeId

[Bits 7:0] Node Id.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX::NodesPerProcessor

[Bits 10:8] Nodes per processor.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX::Reserved

[Bit 31:11] Reserved.

UINT32 CPUID_AMD_PROCESSOR_TOPOLOGY_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX Union Reference

Data Fields
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 PhysicalAddressBits:8
UINT32 LinearAddressBits:8
UINT32 GuestPhysAddrSize:8
UINT32 Reserved:8
} Bits
UINT32 Uint32

Detailed Description

CPUID Linear Physical Address Size

Parameters
EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
Return values
EAX | Linear/Physical Address Size described by the type CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
EBX | Linear/Physical Address Size described by the type CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
ECX | Linear/Physical Address Size described by the type CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
EDX | Reserved. CPUID Linear Physical Address Size EAX for CPUID leaf #CPUID_VIR_PHY_ADDRESS_SIZE.

Field Documentation

struct { ... } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX::Bits

Individual bit fields

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX::GuestPhysAddrSize

[Bits 23:16] Maximum guest physical byte address size in bits.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX::LinearAddressBits

[Bits 15:8] Maximum linear byte address size in bits.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX::PhysicalAddressBits

[Bits 7:0] Maximum physical byte address size in bits.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX::Reserved

[Bit 31:24] Reserved.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX Union Reference

Data Fields
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CLZERO:1
UINT32 IRPerf:1
UINT32 XSaveErPtr:1
UINT32 Reserved:29
} Bits
UINT32 Uint32

Detailed Description

CPUID Linear Physical Address Size EBX for CPUID leaf #CPUID_VIR_PHY_ADDRESS_SIZE.

Field Documentation

struct { ... } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX::Bits

Individual bit fields

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX::CLZERO

[Bits 0] Clear Zero Instruction.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX::IRPerf

[Bits 1] Instructions retired count support.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX::Reserved

[Bit 31:3] Reserved.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX::XSaveErPtr

[Bits 2] Restore error pointers for XSave instructions.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX Union Reference

Data Fields
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 NC:8
UINT32 Reserved1:4
UINT32 ApicIdCoreIdSize:4
UINT32 PerfTscSize:2
UINT32 Reserved2:14
} Bits
UINT32 Uint32

Detailed Description

CPUID Linear Physical Address Size ECX for CPUID leaf #CPUID_VIR_PHY_ADDRESS_SIZE.

Field Documentation

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::ApicIdCoreIdSize

[Bits 15:12] APIC ID size.

struct { ... } CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::Bits

Individual bit fields

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::NC

[Bits 7:0] Number of threads - 1.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::PerfTscSize

[Bits 17:16] Performance time-stamp counter size.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::Reserved1

[Bit 11:8] Reserved.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::Reserved2

[Bit 31:18] Reserved.

UINT32 CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Union Reference

Data Fields
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 ArchPerfMonVerID:8
UINT32 PerformanceMonitorCounters:8
UINT32 PerformanceMonitorCounterWidth:8
UINT32 EbxBitVectorLength:8
} Bits
UINT32 Uint32

Detailed Description

CPUID Architectural Performance Monitoring EAX for CPUID leaf #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.

Field Documentation

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX::ArchPerfMonVerID

[Bit 7:0] Version ID of architectural performance monitoring.

struct { ... } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX::Bits

Individual bit fields

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX::EbxBitVectorLength

[Bits 31:24] Length of EBX bit vector to enumerate architectural performance monitoring events.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX::PerformanceMonitorCounters

[Bits 15:8] Number of general-purpose performance monitoring counter per logical processor.

IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous block of MSR address space. Each performance event select register is paired with a corresponding performance counter in the 0C1H address block.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX::PerformanceMonitorCounterWidth

[Bits 23:16] Bit width of general-purpose, performance monitoring counter.

The bit width of an IA32_PMCx MSR. This the number of valid bits for read operation. On write operations, the lower-order 32 bits of the MSR may be written with any value, and the high-order bits are sign-extended from the value of bit 31.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Union Reference

Data Fields
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 UnhaltedCoreCycles:1
UINT32 InstructionsRetired:1
UINT32 UnhaltedReferenceCycles:1
UINT32 LastLevelCacheReferences:1
UINT32 LastLevelCacheMisses:1
UINT32 BranchInstructionsRetired:1
UINT32 AllBranchMispredictRetired:1
UINT32 Reserved:25
} Bits
UINT32 Uint32

Detailed Description

CPUID Architectural Performance Monitoring EBX for CPUID leaf #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.

Field Documentation

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::AllBranchMispredictRetired

[Bit 6] Branch mispredict retired event not available if 1.

struct { ... } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::Bits

Individual bit fields

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::BranchInstructionsRetired

[Bit 5] Branch instruction retired event not available if 1.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::InstructionsRetired

[Bit 1] Instruction retired event not available if 1.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::LastLevelCacheMisses

[Bit 4] Last-level cache misses event not available if 1.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::LastLevelCacheReferences

[Bit 3] Last-level cache reference event not available if 1.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::UnhaltedCoreCycles

[Bit 0] Core cycle event not available if 1.

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX::UnhaltedReferenceCycles

[Bit 2] Reference cycles event not available if 1.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Union Reference

Data Fields
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 FixedFunctionPerformanceCounters:5
UINT32 FixedFunctionPerformanceCounterWidth:8
UINT32 Reserved:19
} Bits
UINT32 Uint32

Detailed Description

CPUID Architectural Performance Monitoring EDX for CPUID leaf #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.

Field Documentation

struct { ... } CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX::Bits

Individual bit fields

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX::FixedFunctionPerformanceCounters

[Bits 4:0] Number of fixed-function performance counters (if Version ID > 1).

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX::FixedFunctionPerformanceCounterWidth

[Bits 12:5] Bit width of fixed-function performance counters (if Version ID > 1).

UINT32 CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_BRAND_STRING_DATA Union Reference

Data Fields
CPUID_BRAND_STRING_DATA Union Reference

#include <Cpuid.h>

Data Fields

CHAR8 | BrandString [4]
UINT32 | Uint32

Detailed Description

CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1, #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.

Field Documentation

CHAR8 CPUID_BRAND_STRING_DATA::BrandString[4]

4 ASCII characters of Processor Brand String

UINT32 CPUID_BRAND_STRING_DATA::Uint32

All fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_CACHE_INFO_CACHE_TLB Union Reference

Data Fields
CPUID_CACHE_INFO_CACHE_TLB Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved:31
UINT32 NotValid:1
} Bits
UINT8 | CacheDescriptor [4]
UINT32 | Uint32

Detailed Description

CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID leaf #CPUID_CACHE_INFO.

Field Documentation

struct { ... } CPUID_CACHE_INFO_CACHE_TLB::Bits

Individual bit fields

UINT8 CPUID_CACHE_INFO_CACHE_TLB::CacheDescriptor[4]

Array of Cache and TLB descriptor bytes

UINT32 CPUID_CACHE_INFO_CACHE_TLB::NotValid

[Bit 31] If 0, then the cache descriptor bytes in the register are valid. if 1, then none of the cache descriptor bytes in the register are valid.

UINT32 CPUID_CACHE_INFO_CACHE_TLB::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_CACHE_PARAMS_EAX Union Reference

Data Fields
CPUID_CACHE_PARAMS_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CacheType:5
UINT32 CacheLevel:3
UINT32 SelfInitializingCache:1
UINT32 FullyAssociativeCache:1
UINT32 Reserved:4
UINT32 MaximumAddressableIdsForLogicalProcessors:12
UINT32 MaximumAddressableIdsForProcessorCores:6
} Bits
UINT32 Uint32

Detailed Description

CPUID Cache Parameters Information returned in EAX for CPUID leaf #CPUID_CACHE_PARAMS.

Field Documentation

struct { ... } CPUID_CACHE_PARAMS_EAX::Bits

Individual bit fields

UINT32 CPUID_CACHE_PARAMS_EAX::CacheLevel

[Bits 7:5] Cache level (Starts at 1).

UINT32 CPUID_CACHE_PARAMS_EAX::CacheType

[Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL, then there is no information for the requested cache level.

UINT32 CPUID_CACHE_PARAMS_EAX::FullyAssociativeCache

[Bit 9] Fully Associative cache.

UINT32 CPUID_CACHE_PARAMS_EAX::MaximumAddressableIdsForLogicalProcessors

[Bits 25:14] Maximum number of addressable IDs for logical processors sharing this cache.

Add one to the return value to get the result. The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14]) is the number of unique initial APIC IDs reserved for addressing different logical processors sharing this cache.

UINT32 CPUID_CACHE_PARAMS_EAX::MaximumAddressableIdsForProcessorCores

[Bits 31:26] Maximum number of addressable IDs for processor cores in the physical package.

The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26]) is the number of unique Core_IDs reserved for addressing different processor cores in a physical package. Core ID is a subset of bits of the initial APIC ID. The returned value is constant for valid initial values in ECX. Valid ECX values start from 0.

UINT32 CPUID_CACHE_PARAMS_EAX::Reserved

[Bits 13:10] Reserved.

UINT32 CPUID_CACHE_PARAMS_EAX::SelfInitializingCache

[Bit 8] Self Initializing cache level (does not need SW initialization).

UINT32 CPUID_CACHE_PARAMS_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_CACHE_PARAMS_EBX Union Reference

Data Fields
CPUID_CACHE_PARAMS_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 LineSize:12
UINT32 LinePartitions:10
UINT32 Ways:10
} Bits
UINT32 Uint32

Detailed Description

CPUID Cache Parameters Information returned in EBX for CPUID leaf #CPUID_CACHE_PARAMS.

Field Documentation

struct { ... } CPUID_CACHE_PARAMS_EBX::Bits

Individual bit fields

UINT32 CPUID_CACHE_PARAMS_EBX::LinePartitions

[Bits 21:12] Physical Line Partitions. Add one to the return value to get the result.

UINT32 CPUID_CACHE_PARAMS_EBX::LineSize

[Bits 11:0] System Coherency Line Size. Add one to the return value to get the result.

UINT32 CPUID_CACHE_PARAMS_EBX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_CACHE_PARAMS_EBX::Ways

[Bits 31:22] Ways of associativity. Add one to the return value to get the result.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_CACHE_PARAMS_EDX Union Reference

Data Fields
CPUID_CACHE_PARAMS_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Invalidate:1
UINT32 CacheInclusiveness:1
UINT32 ComplexCacheIndexing:1
UINT32 Reserved:29
} Bits
UINT32 Uint32

Detailed Description

CPUID Cache Parameters Information returned in EDX for CPUID leaf #CPUID_CACHE_PARAMS.

Field Documentation

struct { ... } CPUID_CACHE_PARAMS_EDX::Bits

Individual bit fields

UINT32 CPUID_CACHE_PARAMS_EDX::CacheInclusiveness

[Bit 1] Cache Inclusiveness. 0 = Cache is not inclusive of lower cache levels. 1 = Cache is inclusive of lower cache levels.

UINT32 CPUID_CACHE_PARAMS_EDX::ComplexCacheIndexing

[Bit 2] Complex Cache Indexing. 0 = Direct mapped cache. 1 = A complex function is used to index the cache, potentially using all address bits.

UINT32 CPUID_CACHE_PARAMS_EDX::Invalidate

[Bit 0] Write-Back Invalidate/Invalidate. 0 = WBINVD/INVD from threads sharing this cache acts upon lower level caches for threads sharing this cache. 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of non-originating threads sharing this cache.

UINT32 CPUID_CACHE_PARAMS_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_CACHE_INFO_ECX Union Reference

Data Fields
CPUID_EXTENDED_CACHE_INFO_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CacheLineSize:8
UINT32 Reserved:4
UINT32 L2Associativity:4
UINT32 CacheSize:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.

Field Documentation

struct { ... } CPUID_EXTENDED_CACHE_INFO_ECX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_CACHE_INFO_ECX::CacheLineSize

[Bits 7:0] Cache line size in bytes.

UINT32 CPUID_EXTENDED_CACHE_INFO_ECX::CacheSize

[Bits 31:16] Cache size in 1K units.

UINT32 CPUID_EXTENDED_CACHE_INFO_ECX::L2Associativity

[Bits 15:12] L2 Associativity field. Supported values are in the range #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL

UINT32 CPUID_EXTENDED_CACHE_INFO_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_CPU_SIG_ECX Union Reference

Data Fields
CPUID_EXTENDED_CPU_SIG_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 LAHF_SAHF:1
UINT32 Reserved1:4
UINT32 LZCNT:1
UINT32 Reserved2:2
UINT32 PREFETCHW:1
UINT32 Reserved3:23
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf #CPUID_EXTENDED_CPU_SIG.

Field Documentation

struct { ... } CPUID_EXTENDED_CPU_SIG_ECX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_CPU_SIG_ECX::LAHF_SAHF

[Bit 0] LAHF/SAHF available in 64-bit mode.

UINT32 CPUID_EXTENDED_CPU_SIG_ECX::LZCNT

[Bit 5] LZCNT.

UINT32 CPUID_EXTENDED_CPU_SIG_ECX::PREFETCHW

[Bit 8] PREFETCHW.

UINT32 CPUID_EXTENDED_CPU_SIG_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_CPU_SIG_EDX Union Reference

Data Fields
CPUID_EXTENDED_CPU_SIG_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved1:11
UINT32 SYSCALL_SYSRET:1
UINT32 Reserved2:8
UINT32 NX:1
UINT32 Reserved3:5
UINT32 Page1GB:1
UINT32 RDTSCP:1
UINT32 Reserved4:1
UINT32 LM:1
UINT32 Reserved5:2
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf #CPUID_EXTENDED_CPU_SIG.

Field Documentation

struct { ... } CPUID_EXTENDED_CPU_SIG_EDX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_CPU_SIG_EDX::LM

[Bit 29] Intel(R) 64 Architecture available if 1.

UINT32 CPUID_EXTENDED_CPU_SIG_EDX::NX

[Bit 20] Execute Disable Bit available.

UINT32 CPUID_EXTENDED_CPU_SIG_EDX::Page1GB

[Bit 26] 1-GByte pages are available if 1.

UINT32 CPUID_EXTENDED_CPU_SIG_EDX::RDTSCP

[Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.

UINT32 CPUID_EXTENDED_CPU_SIG_EDX::SYSCALL_SYSRET

[Bit 11] SYSCALL/SYSRET available in 64-bit mode.

UINT32 CPUID_EXTENDED_CPU_SIG_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Union Reference

Data Fields
CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 x87:1
UINT32 SSE:1
UINT32 AVX:1
UINT32 MPX:2
UINT32 AVX_512:3
UINT32 IA32_XSS:1
UINT32 PKRU:1
UINT32 Reserved:22
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.

Field Documentation

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::AVX

[Bit 2] AVX state.

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::AVX_512

[Bits 7:5] AVX-512 state.

struct { ... } CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::IA32_XSS

[Bit 8] Used for IA32_XSS.

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::MPX

[Bits 4:3] MPX state.

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::PKRU

[Bit 9] PKRU state.

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::SSE

[Bit 1] SSE state.

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_EXTENDED_STATE_MAIN_LEAF_EAX::x87

[Bit 0] x87 state.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Union Reference

Data Fields
CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 XSS:1
UINT32 Compacted:1
UINT32 Reserved:30
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.

Field Documentation

struct { ... } CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX::Compacted

[Bit 1] is set if, when the compacted format of an XSAVE area is used, this extended state component located on the next 64-byte boundary following the preceding state component (otherwise, it is located immediately following the preceding state component).

UINT32 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX::XSS

[Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is supported in the IA32_XSS MSR; it is clear if bit n is instead supported in XCR0.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_STATE_SUB_LEAF_EAX Union Reference

Data Fields
CPUID_EXTENDED_STATE_SUB_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 XSAVEOPT:1
UINT32 XSAVEC:1
UINT32 XGETBV:1
UINT32 XSAVES:1
UINT32 Reserved:28
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE, sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_EXTENDED_STATE_SUB_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_EAX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_EAX::XGETBV

[Bit 2] Supports XGETBV with ECX = 1 if set.

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_EAX::XSAVEC

[Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_EAX::XSAVEOPT

[Bit 0] XSAVEOPT is available.

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_EAX::XSAVES

[Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_STATE_SUB_LEAF_ECX Union Reference

Data Fields
CPUID_EXTENDED_STATE_SUB_LEAF_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 XCR0:1
UINT32 PT:1
UINT32 XCR0_1:1
UINT32 Reserved:22
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE, sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_EXTENDED_STATE_SUB_LEAF_ECX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_ECX::PT

[Bit 8] PT STate.

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_ECX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_ECX::XCR0

[Bits 7:0] Used for XCR0.

UINT32 CPUID_EXTENDED_STATE_SUB_LEAF_ECX::XCR0_1

[Bit 9] Used for XCR0.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Union Reference

Data Fields
CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 InvariantTsc:1
UINT32 Reserved2:23
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Time Stamp Counter information EDX for CPUID leaf #CPUID_EXTENDED_TIME_STAMP_COUNTER.

Field Documentation

struct { ... } CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX::InvariantTsc

[Bit 8] Invariant TSC available if 1.

UINT32 CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_TOPOLOGY_EAX Union Reference

Data Fields
CPUID_EXTENDED_TOPOLOGY_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 ApicIdShift:5
UINT32 Reserved:27
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.

Field Documentation

UINT32 CPUID_EXTENDED_TOPOLOGY_EAX::ApicIdShift

[Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type. All logical processors with the same next level ID share current level.

Note
Software should use this field (EAX[4:0]) to enumerate processor topology of the system.
struct { ... } CPUID_EXTENDED_TOPOLOGY_EAX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_TOPOLOGY_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_TOPOLOGY_EBX Union Reference

Data Fields
CPUID_EXTENDED_TOPOLOGY_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 LogicalProcessors:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.

Field Documentation

struct { ... } CPUID_EXTENDED_TOPOLOGY_EBX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_TOPOLOGY_EBX::LogicalProcessors

[Bits 15:0] Number of logical processors at this level type. The number reflects configuration as shipped by Intel.

Note
Software must not use EBX[15:0] to enumerate processor topology of the system. This value in this field (EBX[15:0]) is only intended for display/diagnostic purposes. The actual number of logical processors available to BIOS/OS/Applications may be different from the value of EBX[15:0], depending on software and platform hardware configurations.
UINT32 CPUID_EXTENDED_TOPOLOGY_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_EXTENDED_TOPOLOGY_ECX Union Reference

Data Fields
CPUID_EXTENDED_TOPOLOGY_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 LevelNumber:8
UINT32 LevelType:8
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.

Field Documentation

struct { ... } CPUID_EXTENDED_TOPOLOGY_ECX::Bits

Individual bit fields

UINT32 CPUID_EXTENDED_TOPOLOGY_ECX::LevelNumber

[Bits 7:0] Level number. Same value in ECX input.

UINT32 CPUID_EXTENDED_TOPOLOGY_ECX::LevelType

[Bits 15:8] Level type.

Note
The value of the "level type" field is not related to level numbers in any way, higher "level type" values do not mean higher levels.
UINT32 CPUID_EXTENDED_TOPOLOGY_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Union Reference

Data Fields
CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Cr3Filter:1
UINT32 ConfigurablePsb:1
UINT32 IpTraceStopFiltering:1
UINT32 Mtc:1
UINT32 PTWrite:1
UINT32 PowerEventTrace:1
UINT32 Reserved:26
} Bits
UINT32 Uint32

Detailed Description

CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::Bits

Individual bit fields

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::ConfigurablePsb

[Bit 1] If 1, indicates support of Configurable PSB and Cycle-Accurate Mode.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::Cr3Filter

[Bit 0] If 1, indicates that IA32_RTIT_CTL.CR3Filter can be set to 1, and that IA32_RTIT_CR3_MATCH MSR can be accessed.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::IpTraceStopFiltering

[Bit 2] If 1, indicates support of IP Filtering, TraceStop filtering, and preservation of Intel PT MSRs across warm reset.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::Mtc

[Bit 3] If 1, indicates support of MTC timing packet and suppression of COFI-based packets.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::PowerEventTrace

[Bit 5] If 1, indicates support of Power Event Trace. Writes can set IA32_RTIT_CTL[4] (PwrEvtEn), enabling Power Event Trace packet generation.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::PTWrite

[Bit 4] If 1, indicates support of PTWRITE. Writes can set IA32_RTIT_CTL[12] (PTWEn) and IA32_RTIT_CTL[5] (FUPonPTW), and PTWRITE can generate packets.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Union Reference

Data Fields
CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 RTIT:1
UINT32 ToPA:1
UINT32 SingleRangeOutput:1
UINT32 TraceTransportSubsystem:1
UINT32 Reserved:27
UINT32 LIP:1
} Bits
UINT32 Uint32

Detailed Description

CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::Bits

Individual bit fields

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::LIP

[Bit 31] If 1, generated packets which contain IP payloads have LIP values, which include the CS base component.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::RTIT

[Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::SingleRangeOutput

[Bit 2] If 1, indicates support of Single-Range Output scheme.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::ToPA

[Bit 1] If 1, ToPA tables can hold any number of output entries, up to the maximum allowed by the MaskOrTableOffset field of IA32_RTIT_OUTPUT_MASK_PTRS.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::TraceTransportSubsystem

[Bit 3] If 1, indicates support of output to Trace Transport subsystem.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Union Reference

Data Fields
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 ConfigurableAddressRanges:3
UINT32 Reserved:13
UINT32 MtcPeriodEncodings:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX::ConfigurableAddressRanges

[Bits 2:0] Number of configurable Address Ranges for filtering.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX::MtcPeriodEncodings

[Bits 31:16] Bitmap of supported MTC period encodings

UINT32 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Union Reference

Data Fields
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CycleThresholdEncodings:16
UINT32 PsbFrequencyEncodings:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE, sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX::Bits

Individual bit fields

UINT32 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX::CycleThresholdEncodings

[Bits 15:0] Bitmap of supported Cycle Threshold value encodings.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX::PsbFrequencyEncodings

[Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.

UINT32 CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Union Reference

Data Fields
CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 L3CacheAllocation:1
UINT32 L2CacheAllocation:1
UINT32 Reserved2:29
} Bits
UINT32 Uint32

Detailed Description

CPUID L3 and L2 Cache Allocation Support Information EBX for CPUID leaf #CPUID_INTEL_RDT_ALLOCATION, sub-leaf #CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX::L2CacheAllocation

[Bit 2] Supports L2 Cache Allocation Technology if 1.

UINT32 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX::L3CacheAllocation

[Bit 1] Supports L3 Cache Allocation Technology if 1.

UINT32 CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Union Reference

Data Fields
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CapacityLength:5
UINT32 Reserved:27
} Bits
UINT32 Uint32

Detailed Description

CPUID L2 Cache Allocation Technology Information EAX for CPUID leaf #CPUID_INTEL_RDT_ALLOCATION, sub-leaf #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX::CapacityLength

[Bits 4:0] Length of the capacity bit mask for the corresponding ResID using minus-one notation.

UINT32 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Union Reference

Data Fields
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 HighestCosNumber:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID L2 Cache Allocation Technology Information EDX for CPUID leaf #CPUID_INTEL_RDT_ALLOCATION, sub-leaf #CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX::HighestCosNumber

[Bits 15:0] Highest COS number supported for this ResID.

UINT32 CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Union Reference

Data Fields
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 CapacityLength:5
UINT32 Reserved:27
} Bits
UINT32 Uint32

Detailed Description

CPUID L3 Cache Allocation Technology Information EAX for CPUID leaf #CPUID_INTEL_RDT_ALLOCATION, sub-leaf #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX::CapacityLength

[Bits 4:0] Length of the capacity bit mask for the corresponding ResID using minus-one notation.

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Union Reference

Data Fields
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 CosUpdatesInfrequent:1
UINT32 CodeDataPrioritization:1
UINT32 Reserved2:29
} Bits
UINT32 Uint32

Detailed Description

CPUID L3 Cache Allocation Technology Information ECX for CPUID leaf #CPUID_INTEL_RDT_ALLOCATION, sub-leaf #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX::CodeDataPrioritization

[Bit 2] Code and Data Prioritization Technology supported if 1.

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX::CosUpdatesInfrequent

[Bit 1] Updates of COS should be infrequent if 1.

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Union Reference

Data Fields
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 HighestCosNumber:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID L3 Cache Allocation Technology Information EDX for CPUID leaf #CPUID_INTEL_RDT_ALLOCATION, sub-leaf #CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX::HighestCosNumber

[Bits 15:0] Highest COS number supported for this ResID.

UINT32 CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Union Reference

Data Fields
CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 L3CacheRDT_M:1
UINT32 Reserved2:30
} Bits
UINT32 Uint32

Detailed Description

CPUID Intel RDT Monitoring Information EDX for CPUID leaf #CPUID_INTEL_RDT_MONITORING, sub-leaf #CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX::L3CacheRDT_M

[Bit 1] Supports L3 Cache Intel RDT Monitoring if 1.

UINT32 CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Union Reference

Data Fields
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 L3CacheOccupancyMonitoring:1
UINT32 L3CacheTotalBandwidthMonitoring:1
UINT32 L3CacheLocalBandwidthMonitoring:1
UINT32 Reserved:29
} Bits
UINT32 Uint32

Detailed Description

CPUID L3 Cache Intel RDT Monitoring Capability Information EDX for CPUID leaf #CPUID_INTEL_RDT_MONITORING, sub-leaf #CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX::Bits

Individual bit fields

UINT32 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX::L3CacheLocalBandwidthMonitoring

[Bit 2] Supports L3 Local Bandwidth monitoring if 1.

UINT32 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX::L3CacheOccupancyMonitoring

[Bit 0] Supports L3 occupancy monitoring if 1.

UINT32 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX::L3CacheTotalBandwidthMonitoring

[Bit 1] Supports L3 Total Bandwidth monitoring if 1.

UINT32 CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Union Reference

Data Fields
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SGX1:1
UINT32 SGX2:1
UINT32 Reserved:30
} Bits
UINT32 Uint32

Detailed Description

Sub-Leaf 0 Enumeration of Intel SGX Capabilities EAX for CPUID leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX::SGX1

[Bit 0] If 1, indicates leaf functions of SGX1 instruction are supported.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX::SGX2

[Bit 1] If 1, indicates leaf functions of SGX2 instruction are supported.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Union Reference

Data Fields
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 MaxEnclaveSize_Not64:8
UINT32 MaxEnclaveSize_64:8
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

Sub-Leaf 0 Enumeration of Intel SGX Capabilities EDX for CPUID leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX::Bits

Individual bit fields

UINT32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX::MaxEnclaveSize_64

[Bit 15:8] The maximum supported enclave size is 2^(EDX[15:8]) bytes when operating in 64-bit mode.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX::MaxEnclaveSize_Not64

[Bit 7:0] The maximum supported enclave size is 2^(EDX[7:0]) bytes when not in 64-bit mode.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Union Reference

Data Fields
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SubLeafType:4
UINT32 Reserved:8
UINT32 LowAddressOfEpcSection:20
} Bits
UINT32 Uint32

Detailed Description

Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EAX for CPUID leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX::Bits

Individual bit fields

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX::LowAddressOfEpcSection

[Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the physical address of the base of the EPC section.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX::SubLeafType

[Bit 3:0] Sub-leaf-type encoding. 0000b: This sub-leaf is invalid, EBX:EAX and EDX:ECX report 0. 0001b: This sub-leaf provides information on the Enclave Page Cache (EPC) in EBX:EAX and EDX:ECX. All other encoding are reserved.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Union Reference

Data Fields
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 HighAddressOfEpcSection:20
UINT32 Reserved:12
} Bits
UINT32 Uint32

Detailed Description

Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EBX for CPUID leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX::Bits

Individual bit fields

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX::HighAddressOfEpcSection

[Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the physical address of the base of the EPC section.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Union Reference

Data Fields
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 EpcSection:4
UINT32 Reserved:8
UINT32 LowSizeOfEpcSection:20
} Bits
UINT32 Uint32

Detailed Description

Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources ECX for CPUID leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX::Bits

Individual bit fields

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX::EpcSection

[Bit 3:0] The EPC section encoding. 0000b: Not valid. 0001b: The EPC section is confidentiality, integrity and replay protected. All other encoding are reserved.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX::LowSizeOfEpcSection

[Bit 31:12] If EAX[3:0] = 0001b, these are bits 31:12 of the size of the corresponding EPC section within the Processor Reserved Memory.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Union Reference

Data Fields
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 HighSizeOfEpcSection:20
UINT32 Reserved:12
} Bits
UINT32 Uint32

Detailed Description

Sub-Leaf Index 2 or Higher Enumeration of Intel SGX Resources EDX for CPUID leaf #CPUID_INTEL_SGX, sub-leaf #CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF.

Field Documentation

struct { ... } CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX::Bits

Individual bit fields

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX::HighSizeOfEpcSection

[Bit 19:0] If EAX[3:0] = 0001b, these are bits 51:32 of the size of the corresponding EPC section within the Processor Reserved Memory.

UINT32 CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MEMORY_ENCRYPTION_INFO_EAX Union Reference

Data Fields
CPUID_MEMORY_ENCRYPTION_INFO_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SmeBit:1
UINT32 SevBit:1
UINT32 PageFlushMsrBit:1
UINT32 SevEsBit:1
UINT32 ReservedBits:28
} Bits
UINT32 Uint32

Detailed Description

CPUID Memory Encryption support information EAX for CPUID leaf #CPUID_MEMORY_ENCRYPTION_INFO.

Field Documentation

struct { ... } CPUID_MEMORY_ENCRYPTION_INFO_EAX::Bits

Individual bit fields

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EAX::PageFlushMsrBit

[Bit 2] Page flush MSR support

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EAX::ReservedBits

[Bit 31:4] Reserved

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EAX::SevBit

[Bit 1] Secure Encrypted Virtualization (Sev) Support

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EAX::SevEsBit

[Bit 3] Encrypted state support

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EAX::SmeBit

[Bit 0] Secure Memory Encryption (Sme) Support

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MEMORY_ENCRYPTION_INFO_EBX Union Reference

Data Fields
CPUID_MEMORY_ENCRYPTION_INFO_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 PtePosBits:6
UINT32 ReducedPhysBits:5
UINT32 ReservedBits:21
} Bits
UINT32 Uint32

Detailed Description

CPUID Memory Encryption support information EBX for CPUID leaf #CPUID_MEMORY_ENCRYPTION_INFO.

Field Documentation

struct { ... } CPUID_MEMORY_ENCRYPTION_INFO_EBX::Bits

Individual bit fields

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EBX::PtePosBits

[Bit 5:0] Page table bit number used to enable memory encryption

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EBX::ReducedPhysBits

[Bit 11:6] Reduction of system physical address space bits when memory encryption is enabled

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EBX::ReservedBits

[Bit 31:12] Reserved

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MEMORY_ENCRYPTION_INFO_ECX Union Reference

Data Fields
CPUID_MEMORY_ENCRYPTION_INFO_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 NumGuests
} Bits
UINT32 Uint32

Detailed Description

CPUID Memory Encryption support information ECX for CPUID leaf #CPUID_MEMORY_ENCRYPTION_INFO.

Field Documentation

struct { ... } CPUID_MEMORY_ENCRYPTION_INFO_ECX::Bits

Individual bit fields

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_ECX::NumGuests

[Bit 31:0] Number of encrypted guest supported simultaneously

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MEMORY_ENCRYPTION_INFO_EDX Union Reference

Data Fields
CPUID_MEMORY_ENCRYPTION_INFO_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 MinAsid
} Bits
UINT32 Uint32

Detailed Description

CPUID Memory Encryption support information EDX for CPUID leaf #CPUID_MEMORY_ENCRYPTION_INFO.

Field Documentation

struct { ... } CPUID_MEMORY_ENCRYPTION_INFO_EDX::Bits

Individual bit fields

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EDX::MinAsid

[Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID

UINT32 CPUID_MEMORY_ENCRYPTION_INFO_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MONITOR_MWAIT_EAX Union Reference

Data Fields
CPUID_MONITOR_MWAIT_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SmallestMonitorLineSize:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf #CPUID_MONITOR_MWAIT.

Field Documentation

struct { ... } CPUID_MONITOR_MWAIT_EAX::Bits

Individual bit fields

UINT32 CPUID_MONITOR_MWAIT_EAX::SmallestMonitorLineSize

[Bits 15:0] Smallest monitor-line size in bytes (default is processor's monitor granularity).

UINT32 CPUID_MONITOR_MWAIT_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MONITOR_MWAIT_EBX Union Reference

Data Fields
CPUID_MONITOR_MWAIT_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 LargestMonitorLineSize:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf #CPUID_MONITOR_MWAIT.

Field Documentation

struct { ... } CPUID_MONITOR_MWAIT_EBX::Bits

Individual bit fields

UINT32 CPUID_MONITOR_MWAIT_EBX::LargestMonitorLineSize

[Bits 15:0] Largest monitor-line size in bytes (default is processor's monitor granularity).

UINT32 CPUID_MONITOR_MWAIT_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MONITOR_MWAIT_ECX Union Reference

Data Fields
CPUID_MONITOR_MWAIT_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 ExtensionsSupported:1
UINT32 InterruptAsBreak:1
UINT32 Reserved:30
} Bits
UINT32 Uint32

Detailed Description

CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf #CPUID_MONITOR_MWAIT.

Field Documentation

struct { ... } CPUID_MONITOR_MWAIT_ECX::Bits

Individual bit fields

UINT32 CPUID_MONITOR_MWAIT_ECX::ExtensionsSupported

[Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX, and EDX are valid.

UINT32 CPUID_MONITOR_MWAIT_ECX::InterruptAsBreak

[Bit 1] Supports treating interrupts as break-event for MWAIT, even when interrupts disabled.

UINT32 CPUID_MONITOR_MWAIT_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_MONITOR_MWAIT_EDX Union Reference

Data Fields
CPUID_MONITOR_MWAIT_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 C0States:4
UINT32 C1States:4
UINT32 C2States:4
UINT32 C3States:4
UINT32 C4States:4
UINT32 C5States:4
UINT32 C6States:4
UINT32 C7States:4
} Bits
UINT32 Uint32

Detailed Description

CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf #CPUID_MONITOR_MWAIT.

Note
The definition of C0 through C7 states for MWAIT extension are processor-specific C-states, not ACPI C-states.

Field Documentation

struct { ... } CPUID_MONITOR_MWAIT_EDX::Bits

Individual bit fields

UINT32 CPUID_MONITOR_MWAIT_EDX::C0States

[Bits 3:0] Number of C0 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C1States

[Bits 7:4] Number of C1 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C2States

[Bits 11:8] Number of C2 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C3States

[Bits 15:12] Number of C3 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C4States

[Bits 19:16] Number of C4 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C5States

[Bits 23:20] Number of C5 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C6States

[Bits 27:24] Number of C6 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::C7States

[Bits 31:28] Number of C7 sub C-states supported using MWAIT.

UINT32 CPUID_MONITOR_MWAIT_EDX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_PROCESSOR_FREQUENCY_EAX Union Reference

Data Fields
CPUID_PROCESSOR_FREQUENCY_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 ProcessorBaseFrequency:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Processor Frequency Information EAX for CPUID leaf #CPUID_PROCESSOR_FREQUENCY.

Field Documentation

struct { ... } CPUID_PROCESSOR_FREQUENCY_EAX::Bits

Individual bit fields

UINT32 CPUID_PROCESSOR_FREQUENCY_EAX::ProcessorBaseFrequency

[Bits 15:0] Processor Base Frequency (in MHz).

UINT32 CPUID_PROCESSOR_FREQUENCY_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_PROCESSOR_FREQUENCY_EBX Union Reference

Data Fields
CPUID_PROCESSOR_FREQUENCY_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 MaximumFrequency:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Processor Frequency Information EBX for CPUID leaf #CPUID_PROCESSOR_FREQUENCY.

Field Documentation

struct { ... } CPUID_PROCESSOR_FREQUENCY_EBX::Bits

Individual bit fields

UINT32 CPUID_PROCESSOR_FREQUENCY_EBX::MaximumFrequency

[Bits 15:0] Maximum Frequency (in MHz).

UINT32 CPUID_PROCESSOR_FREQUENCY_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_PROCESSOR_FREQUENCY_ECX Union Reference

Data Fields
CPUID_PROCESSOR_FREQUENCY_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 BusFrequency:16
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Processor Frequency Information ECX for CPUID leaf #CPUID_PROCESSOR_FREQUENCY.

Field Documentation

struct { ... } CPUID_PROCESSOR_FREQUENCY_ECX::Bits

Individual bit fields

UINT32 CPUID_PROCESSOR_FREQUENCY_ECX::BusFrequency

[Bits 15:0] Bus (Reference) Frequency (in MHz).

UINT32 CPUID_PROCESSOR_FREQUENCY_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_SOC_VENDOR_BRAND_STRING_DATA Union Reference

Data Fields
CPUID_SOC_VENDOR_BRAND_STRING_DATA Union Reference

#include <Cpuid.h>

Data Fields

CHAR8 | BrandString [4]
UINT32 | Uint32

Detailed Description

CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1, #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.

Field Documentation

CHAR8 CPUID_SOC_VENDOR_BRAND_STRING_DATA::BrandString[4]

4 UTF-8 characters of Soc Vendor Brand String

UINT32 CPUID_SOC_VENDOR_BRAND_STRING_DATA::Uint32

All fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_SOC_VENDOR_MAIN_LEAF_EBX Union Reference

Data Fields
CPUID_SOC_VENDOR_MAIN_LEAF_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SocVendorId:16
UINT32 IsVendorScheme:1
UINT32 Reserved:15
} Bits
UINT32 Uint32

Detailed Description

CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf #CPUID_SOC_VENDOR_MAIN_LEAF.

Field Documentation

struct { ... } CPUID_SOC_VENDOR_MAIN_LEAF_EBX::Bits

Individual bit fields

UINT32 CPUID_SOC_VENDOR_MAIN_LEAF_EBX::IsVendorScheme

[Bit 16] If 1, the SOC Vendor ID field is assigned via an industry standard enumeration scheme. Otherwise, the SOC Vendor ID field is assigned by Intel.

UINT32 CPUID_SOC_VENDOR_MAIN_LEAF_EBX::SocVendorId

[Bits 15:0] SOC Vendor ID.

UINT32 CPUID_SOC_VENDOR_MAIN_LEAF_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Union Reference

Data Fields
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 FSGSBASE:1
UINT32 IA32_TSC_ADJUST:1
UINT32 SGX:1
UINT32 BMI1:1
UINT32 HLE:1
UINT32 AVX2:1
UINT32 FDP_EXCPTN_ONLY:1
UINT32 SMEP:1
UINT32 BMI2:1
UINT32 EnhancedRepMovsbStosb:1
UINT32 INVPCID:1
UINT32 RTM:1
UINT32 RDT_M:1
UINT32 DeprecateFpuCsDs:1
UINT32 MPX:1
UINT32 RDT_A:1
UINT32 Reserved2:2
UINT32 RDSEED:1
UINT32 ADX:1
UINT32 SMAP:1
UINT32 Reserved3:2
UINT32 CLFLUSHOPT:1
UINT32 CLWB:1
UINT32 IntelProcessorTrace:1
UINT32 Reserved4:3
UINT32 SHA:1
UINT32 Reserved5:2
} Bits
UINT32 Uint32

Detailed Description

CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.

Field Documentation

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::ADX

[Bit 19] If 1 indicates the processor supports the ADCX and ADOX instructions.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::AVX2

[Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.

struct { ... } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::Bits

Individual bit fields

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::BMI1

[Bit 3] If 1 indicates the processor supports the first group of advanced bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::BMI2

[Bit 8] If 1 indicates the processor supports the second group of advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX, SARX, SHLX, SHRX)

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::CLFLUSHOPT

[Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::CLWB

[Bit 24] If 1 indicates the processor supports the CLWB instruction.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::DeprecateFpuCsDs

[Bit 13] Deprecates FPU CS and FPU DS values if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::EnhancedRepMovsbStosb

[Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::FDP_EXCPTN_ONLY

[Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::FSGSBASE

[Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::HLE

[Bit 4] Hardware Lock Elision

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::IA32_TSC_ADJUST

[Bit 1] IA32_TSC_ADJUST MSR is supported if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::IntelProcessorTrace

[Bit 25] If 1 indicates the processor supports the Intel Processor Trace extensions.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::INVPCID

[Bit 10] If 1, supports INVPCID instruction for system software that manages process-context identifiers.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::MPX

[Bit 14] Supports Intel(R) Memory Protection Extensions if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::RDSEED

[Bit 18] If 1 indicates the processor supports the RDSEED instruction.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::RDT_A

[Bit 15] Supports Intel(R) Resource Director Technology (Intel(R) RDT) Allocation capability if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::RDT_M

[Bit 12] Supports Intel(R) Resource Director Technology (Intel(R) RDT) Monitoring capability if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::RTM

[Bit 11] Restricted Transactional Memory

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::SGX

[Bit 2] Intel SGX is supported if 1. See section 37.7 "DISCOVERING SUPPORT FOR INTEL(R) SGX AND ENABLING ENCLAVE INSTRUCTIONS".

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::SHA

[Bit 29] Supports Intel(R) Secure Hash Algorithm Extensions (Intel(R) SHA Extensions) if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::SMAP

[Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC instructions) if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::SMEP

[Bit 7] Supports Supervisor-Mode Execution Prevention if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Union Reference

Data Fields
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 PREFETCHWT1:1
UINT32 Reserved1:1
UINT32 UMIP:1
UINT32 PKU:1
UINT32 OSPKE:1
UINT32 Reserved2:12
UINT32 MAWAU:5
UINT32 RDPID:1
UINT32 Reserved3:7
UINT32 SGX_LC:1
UINT32 Reserved4:1
} Bits
UINT32 Uint32

Detailed Description

CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.

Field Documentation

struct { ... } CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::Bits

Individual bit fields

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::MAWAU

[Bits 21:17] The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::OSPKE

[Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the RDPKRU/WRPKRU instructions).

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::PKU

[Bit 3] Supports protection keys for user-mode pages if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::PREFETCHWT1

[Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::RDPID

[Bit 22] Supports Read Processor ID if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::SGX_LC

[Bit 30] Supports SGX Launch Configuration if 1.

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX::UMIP

[Bit 2] Supports user-mode instruction prevention if 1.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_THERMAL_POWER_MANAGEMENT_EAX Union Reference

Data Fields
CPUID_THERMAL_POWER_MANAGEMENT_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 DigitalTemperatureSensor:1
UINT32 TurboBoostTechnology:1
UINT32 ARAT:1
UINT32 Reserved1:1
UINT32 PLN:1
UINT32 ECMD:1
UINT32 PTM:1
UINT32 HWP:1
UINT32 HWP_Notification:1
UINT32 HWP_Activity_Window:1
UINT32 HWP_Energy_Performance_Preference:1
UINT32 HWP_Package_Level_Request:1
UINT32 Reserved2:1
UINT32 HDC:1
UINT32 Reserved3:18
} Bits
UINT32 Uint32

Detailed Description

CPUID Thermal and Power Management Information returned in EAX for CPUID leaf #CPUID_THERMAL_POWER_MANAGEMENT.

Field Documentation

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::ARAT

[Bit 2] APIC-Timer-always-running feature is supported if set.

struct { ... } CPUID_THERMAL_POWER_MANAGEMENT_EAX::Bits

Individual bit fields

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::DigitalTemperatureSensor

[Bit 0] Digital temperature sensor is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::ECMD

[Bit 5] Clock modulation duty cycle extension is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::HDC

[Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1, IA32_THREAD_STALL MSRs are supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::HWP

[Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES, IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::HWP_Activity_Window

[Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::HWP_Energy_Performance_Preference

[Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::HWP_Notification

[Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::HWP_Package_Level_Request

[Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::PLN

[Bit 4] Power limit notification controls are supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::PTM

[Bit 6] Package thermal management is supported if set.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::TurboBoostTechnology

[Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_THERMAL_POWER_MANAGEMENT_EBX Union Reference

Data Fields
CPUID_THERMAL_POWER_MANAGEMENT_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 InterruptThresholds:4
UINT32 Reserved:28
} Bits
UINT32 Uint32

Detailed Description

CPUID Thermal and Power Management Information returned in EBX for CPUID leaf #CPUID_THERMAL_POWER_MANAGEMENT.

Field Documentation

struct { ... } CPUID_THERMAL_POWER_MANAGEMENT_EBX::Bits

Individual bit fields

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EBX::InterruptThresholds

{Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_THERMAL_POWER_MANAGEMENT_ECX Union Reference

Data Fields
CPUID_THERMAL_POWER_MANAGEMENT_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 HardwareCoordinationFeedback:1
UINT32 Reserved1:2
UINT32 PerformanceEnergyBias:1
UINT32 Reserved2:28
} Bits
UINT32 Uint32

Detailed Description

CPUID Thermal and Power Management Information returned in ECX for CPUID leaf #CPUID_THERMAL_POWER_MANAGEMENT.

Field Documentation

struct { ... } CPUID_THERMAL_POWER_MANAGEMENT_ECX::Bits

Individual bit fields

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_ECX::HardwareCoordinationFeedback

[Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF and IA32_APERF). The capability to provide a measure of delivered processor performance (since last reset of the counters), as a percentage of the expected processor performance when running at the TSC frequency.

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_ECX::PerformanceEnergyBias

[Bit 3] If this bit is set, then the processor supports performance-energy bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS (1B0H).

UINT32 CPUID_THERMAL_POWER_MANAGEMENT_ECX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_VERSION_INFO_EAX Union Reference

Data Fields
CPUID_VERSION_INFO_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SteppingId:4
[Bits 3:0] Stepping ID
UINT32 Model:4
[Bits 7:4] Model
UINT32 FamilyId:4
[Bits 11:8] Family
UINT32 ProcessorType:2
[Bits 13:12] Processor Type
UINT32 Reserved1:2
[Bits 15:14] Reserved
UINT32 ExtendedModelId:4
[Bits 19:16] Extended Model ID
UINT32 ExtendedFamilyId:8
[Bits 27:20] Extended Family ID
UINT32 Reserved2:4
Reserved.
} Bits
UINT32 Uint32

Detailed Description

CPUID Version Information returned in EAX for CPUID leaf #CPUID_VERSION_INFO.

Field Documentation

struct { ... } CPUID_VERSION_INFO_EAX::Bits

Individual bit fields

UINT32 CPUID_VERSION_INFO_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_VERSION_INFO_EBX Union Reference

Data Fields
CPUID_VERSION_INFO_EBX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 BrandIndex:8
UINT32 CacheLineSize:8
UINT32 MaximumAddressableIdsForLogicalProcessors:8
UINT32 InitialLocalApicId:8
} Bits
UINT32 Uint32

Detailed Description

CPUID Version Information returned in EBX for CPUID leaf #CPUID_VERSION_INFO.

Field Documentation

struct { ... } CPUID_VERSION_INFO_EBX::Bits

Individual bit fields

UINT32 CPUID_VERSION_INFO_EBX::BrandIndex

[Bits 7:0] Provides an entry into a brand string table that contains brand strings for IA-32 processors.

UINT32 CPUID_VERSION_INFO_EBX::CacheLineSize

[Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH and CLFLUSHOPT instructions in 8-byte increments. This field was introduced in the Pentium 4 processor.

UINT32 CPUID_VERSION_INFO_EBX::InitialLocalApicId

[Bits 31:24] The 8-bit ID that is assigned to the local APIC on the processor during power up. This field was introduced in the Pentium 4 processor.

UINT32 CPUID_VERSION_INFO_EBX::MaximumAddressableIdsForLogicalProcessors

[Bits 23:16] Maximum number of addressable IDs for logical processors in this physical package.

Note
The nearest power-of-2 integer that is not smaller than EBX[23:16] is the number of unique initial APICIDs reserved for addressing different logical processors in a physical package. This field is only valid if CPUID.1.EDX.HTT[bit 28]= 1.
UINT32 CPUID_VERSION_INFO_EBX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_VERSION_INFO_ECX Union Reference

Data Fields
CPUID_VERSION_INFO_ECX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 SSE3:1
UINT32 PCLMULQDQ:1
UINT32 DTES64:1
UINT32 MONITOR:1
UINT32 DS_CPL:1
UINT32 VMX:1
UINT32 SMX:1
UINT32 EIST:1
UINT32 TM2:1
UINT32 SSSE3:1
UINT32 CNXT_ID:1
UINT32 SDBG:1
UINT32 FMA:1
UINT32 CMPXCHG16B:1
UINT32 xTPR_Update_Control:1
UINT32 PDCM:1
UINT32 Reserved:1
UINT32 PCID:1
UINT32 DCA:1
UINT32 SSE4_1:1
UINT32 SSE4_2:1
UINT32 x2APIC:1
UINT32 MOVBE:1
UINT32 POPCNT:1
UINT32 TSC_Deadline:1
UINT32 AESNI:1
UINT32 XSAVE:1
UINT32 OSXSAVE:1
UINT32 AVX:1
UINT32 F16C:1
UINT32 RDRAND:1
UINT32 NotUsed:1
} Bits
UINT32 Uint32

Detailed Description

CPUID Version Information returned in ECX for CPUID leaf #CPUID_VERSION_INFO.

Field Documentation

UINT32 CPUID_VERSION_INFO_ECX::AESNI

[Bit 25] A value of 1 indicates that the processor supports the AESNI instruction extensions.

UINT32 CPUID_VERSION_INFO_ECX::AVX

[Bit 28] A value of 1 indicates the processor supports the AVX instruction extensions.

struct { ... } CPUID_VERSION_INFO_ECX::Bits

Individual bit fields

UINT32 CPUID_VERSION_INFO_ECX::CMPXCHG16B

[Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature is available.

UINT32 CPUID_VERSION_INFO_ECX::CNXT_ID

[Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode can be set to either adaptive mode or shared mode. A value of 0 indicates this feature is not supported. See definition of the IA32_MISC_ENABLE MSR Bit 24 (L1 Data Cache Context Mode) for details

UINT32 CPUID_VERSION_INFO_ECX::DCA

[Bit 18] A value of 1 indicates the processor supports the ability to prefetch data from a memory mapped device. Direct Cache Access.

UINT32 CPUID_VERSION_INFO_ECX::DS_CPL

[Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor supports the extensions to the Debug Store feature to allow for branch message storage qualified by CPL

UINT32 CPUID_VERSION_INFO_ECX::DTES64

[Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports DS area using 64-bit layout.

UINT32 CPUID_VERSION_INFO_ECX::EIST

[Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates that the processor supports this technology

UINT32 CPUID_VERSION_INFO_ECX::F16C

[Bit 29] A value of 1 indicates that processor supports 16-bit floating-point conversion instructions.

UINT32 CPUID_VERSION_INFO_ECX::FMA

[Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple Add) extensions using YMM state.

UINT32 CPUID_VERSION_INFO_ECX::MONITOR

[Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports this feature.

UINT32 CPUID_VERSION_INFO_ECX::MOVBE

[Bit 22] A value of 1 indicates that the processor supports MOVBE instruction.

UINT32 CPUID_VERSION_INFO_ECX::NotUsed

[Bit 31] Always returns 0.

UINT32 CPUID_VERSION_INFO_ECX::OSXSAVE

[Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18] to enable XSETBV/XGETBV instructions to access XCR0 and to support processor extended state management using XSAVE/XRSTOR.

UINT32 CPUID_VERSION_INFO_ECX::PCID

[Bit 17] Process-context identifiers. A value of 1 indicates that the processor supports PCIDs and that software may set CR4.PCIDE to 1.

UINT32 CPUID_VERSION_INFO_ECX::PCLMULQDQ

[Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ instruction. Carryless Multiplication

UINT32 CPUID_VERSION_INFO_ECX::PDCM

[Bit 15] Perfmon and Debug Capability: A value of 1 indicates the processor supports the performance and debug feature indication MSR IA32_PERF_CAPABILITIES.

UINT32 CPUID_VERSION_INFO_ECX::POPCNT

[Bit 23] A value of 1 indicates that the processor supports the POPCNT instruction.

UINT32 CPUID_VERSION_INFO_ECX::RDRAND

[Bit 30] A value of 1 indicates that processor supports RDRAND instruction.

UINT32 CPUID_VERSION_INFO_ECX::SDBG

[Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE MSR for silicon debug

UINT32 CPUID_VERSION_INFO_ECX::SMX

[Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor supports this technology

UINT32 CPUID_VERSION_INFO_ECX::SSE3

[Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the processor supports this technology

UINT32 CPUID_VERSION_INFO_ECX::SSE4_1

[Bit 19] A value of 1 indicates that the processor supports SSE4.1.

UINT32 CPUID_VERSION_INFO_ECX::SSE4_2

[Bit 20] A value of 1 indicates that the processor supports SSE4.2.

UINT32 CPUID_VERSION_INFO_ECX::SSSE3

[Bit 9] A value of 1 indicates the presence of the Supplemental Streaming SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction extensions are not present in the processor.

UINT32 CPUID_VERSION_INFO_ECX::TM2

[Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor supports this technology

UINT32 CPUID_VERSION_INFO_ECX::TSC_Deadline

[Bit 24] A value of 1 indicates that the processor's local APIC timer supports one-shot operation using a TSC deadline value.

UINT32 CPUID_VERSION_INFO_ECX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_VERSION_INFO_ECX::VMX

[Bit 5] Virtual Machine Extensions. A value of 1 indicates that the processor supports this technology.

UINT32 CPUID_VERSION_INFO_ECX::x2APIC

[Bit 21] A value of 1 indicates that the processor supports x2APIC feature.

UINT32 CPUID_VERSION_INFO_ECX::XSAVE

[Bit 26] A value of 1 indicates that the processor supports the XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV instructions, and XCR0.

UINT32 CPUID_VERSION_INFO_ECX::xTPR_Update_Control

[Bit 14] xTPR Update Control. A value of 1 indicates that the processor supports changing IA32_MISC_ENABLE[Bit 23].

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_VERSION_INFO_EDX Union Reference

Data Fields
CPUID_VERSION_INFO_EDX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 FPU:1
UINT32 VME:1
UINT32 DE:1
UINT32 PSE:1
UINT32 TSC:1
UINT32 MSR:1
UINT32 PAE:1
UINT32 MCE:1
UINT32 CX8:1
UINT32 APIC:1
UINT32 Reserved1:1
UINT32 SEP:1
UINT32 MTRR:1
UINT32 PGE:1
UINT32 MCA:1
UINT32 CMOV:1
UINT32 PAT:1
UINT32 PSE_36:1
UINT32 PSN:1
UINT32 CLFSH:1
UINT32 Reserved2:1
UINT32 DS:1
UINT32 ACPI:1
UINT32 MMX:1
UINT32 FXSR:1
UINT32 SSE:1
UINT32 SSE2:1
UINT32 SS:1
UINT32 HTT:1
UINT32 TM:1
UINT32 Reserved3:1
UINT32 PBE:1
} Bits
UINT32 Uint32

Detailed Description

CPUID Version Information returned in EDX for CPUID leaf #CPUID_VERSION_INFO.

Field Documentation

UINT32 CPUID_VERSION_INFO_EDX::ACPI

[Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The processor implements internal MSRs that allow processor temperature to be monitored and processor performance to be modulated in predefined duty cycles under software control.

UINT32 CPUID_VERSION_INFO_EDX::APIC

[Bit 9] APIC On-Chip. The processor contains an Advanced Programmable Interrupt Controller (APIC), responding to memory mapped commands in the physical address range FFFE0000H to FFFE0FFFH (by default - some processors permit the APIC to be relocated).

struct { ... } CPUID_VERSION_INFO_EDX::Bits

Individual bit fields

UINT32 CPUID_VERSION_INFO_EDX::CLFSH

[Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.

UINT32 CPUID_VERSION_INFO_EDX::CMOV

[Bit 15] Conditional Move Instructions. The conditional move instruction CMOV is supported. In addition, if x87 FPU is present as indicated by the CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.

UINT32 CPUID_VERSION_INFO_EDX::CX8

[Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits) instruction is supported (implicitly locked and atomic).

UINT32 CPUID_VERSION_INFO_EDX::DE

[Bit 2] Debugging Extensions. Support for I/O breakpoints, including CR4.DE for controlling the feature, and optional trapping of accesses to DR4 and DR5.

UINT32 CPUID_VERSION_INFO_EDX::DS

[Bit 21] Debug Store. The processor supports the ability to write debug information into a memory resident buffer. This feature is used by the branch trace store (BTS) and precise event-based sampling (PEBS) facilities.

UINT32 CPUID_VERSION_INFO_EDX::FPU

[Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.

UINT32 CPUID_VERSION_INFO_EDX::FXSR

[Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR instructions are supported for fast save and restore of the floating point context. Presence of this bit also indicates that CR4.OSFXSR is available for an operating system to indicate that it supports the FXSAVE and FXRSTOR instructions.

UINT32 CPUID_VERSION_INFO_EDX::HTT

[Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT indicates there is only a single logical processor in the package and software should assume only a single APIC ID is reserved. A value of 1 for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of addressable IDs for logical processors in this package) is valid for the package.

UINT32 CPUID_VERSION_INFO_EDX::MCA

[Bit 14] Machine Check Architecture. A value of 1 indicates the Machine Check Architecture of reporting machine errors is supported. The MCG_CAP MSR contains feature bits describing how many banks of error reporting MSRs are supported.

UINT32 CPUID_VERSION_INFO_EDX::MCE

[Bit 7] Machine Check Exception. Exception 18 is defined for Machine Checks, including CR4.MCE for controlling the feature. This feature does not define the model-specific implementations of machine-check error logging, reporting, and processor shutdowns. Machine Check exception handlers may have to depend on processor version to do model specific processing of the exception, or test for the presence of the Machine Check feature.

UINT32 CPUID_VERSION_INFO_EDX::MMX

[Bit 23] Intel MMX Technology. The processor supports the Intel MMX technology.

UINT32 CPUID_VERSION_INFO_EDX::MSR

[Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The RDMSR and WRMSR instructions are supported. Some of the MSRs are implementation dependent.

UINT32 CPUID_VERSION_INFO_EDX::MTRR

[Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap MSR contains feature bits that describe what memory types are supported, how many variable MTRRs are supported, and whether fixed MTRRs are supported.

UINT32 CPUID_VERSION_INFO_EDX::PAE

[Bit 6] Physical Address Extension. Physical addresses greater than 32 bits are supported: extended page table entry formats, an extra level in the page translation tables is defined, 2-MByte pages are supported instead of 4 Mbyte pages if PAE bit is 1.

UINT32 CPUID_VERSION_INFO_EDX::PAT

[Bit 16] Page Attribute Table. Page Attribute Table is supported. This feature augments the Memory Type Range Registers (MTRRs), allowing an operating system to specify attributes of memory accessed through a linear address on a 4KB granularity.

UINT32 CPUID_VERSION_INFO_EDX::PBE

[Bit 31] Pending Break Enable. The processor supports the use of the FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is asserted) to signal the processor that an interrupt is pending and that the processor should return to normal operation to handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.

UINT32 CPUID_VERSION_INFO_EDX::PGE

[Bit 13] Page Global Bit. The global bit is supported in paging-structure entries that map a page, indicating TLB entries that are common to different processes and need not be flushed. The CR4.PGE bit controls this feature.

UINT32 CPUID_VERSION_INFO_EDX::PSE

[Bit 3] Page Size Extension. Large pages of size 4 MByte are supported, including CR4.PSE for controlling the feature, the defined dirty bit in PDE (Page Directory Entries), optional reserved bit trapping in CR3, PDEs, and PTEs.

UINT32 CPUID_VERSION_INFO_EDX::PSE_36

[Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical memory beyond 4 GBytes are supported with 32-bit paging. This feature indicates that upper bits of the physical address of a 4-MByte page are encoded in bits 20:13 of the page-directory entry. Such physical addresses are limited by MAXPHYADDR and may be up to 40 bits in size.

UINT32 CPUID_VERSION_INFO_EDX::PSN

[Bit 18] Processor Serial Number. The processor supports the 96-bit processor identification number feature and the feature is enabled.

UINT32 CPUID_VERSION_INFO_EDX::SEP

[Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT and associated MSRs are supported.

UINT32 CPUID_VERSION_INFO_EDX::SS

[Bit 27] Self Snoop. The processor supports the management of conflicting memory types by performing a snoop of its own cache structure for transactions issued to the bus.

UINT32 CPUID_VERSION_INFO_EDX::SSE

[Bit 25] SSE. The processor supports the SSE extensions.

UINT32 CPUID_VERSION_INFO_EDX::SSE2

[Bit 26] SSE2. The processor supports the SSE2 extensions.

UINT32 CPUID_VERSION_INFO_EDX::TM

[Bit 29] Thermal Monitor. The processor implements the thermal monitor automatic thermal control circuitry (TCC).

UINT32 CPUID_VERSION_INFO_EDX::TSC

[Bit 4] Time Stamp Counter. The RDTSC instruction is supported, including CR4.TSD for controlling privilege.

UINT32 CPUID_VERSION_INFO_EDX::Uint32

All bit fields as a 32-bit value

UINT32 CPUID_VERSION_INFO_EDX::VME

[Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements, including CR4.VME for controlling the feature, CR4.PVI for protected mode virtual interrupts, software interrupt indirection, expansion of the TSS with the software indirection bitmap, and EFLAGS.VIF and EFLAGS.VIP flags.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: CPUID_VIR_PHY_ADDRESS_SIZE_EAX Union Reference

Data Fields
CPUID_VIR_PHY_ADDRESS_SIZE_EAX Union Reference

#include <Cpuid.h>

Data Fields

struct {
UINT32 PhysicalAddressBits:8
UINT32 LinearAddressBits:8
UINT32 Reserved:16
} Bits
UINT32 Uint32

Detailed Description

CPUID Linear Physical Address Size EAX for CPUID leaf #CPUID_VIR_PHY_ADDRESS_SIZE.

Field Documentation

struct { ... } CPUID_VIR_PHY_ADDRESS_SIZE_EAX::Bits

Individual bit fields

UINT32 CPUID_VIR_PHY_ADDRESS_SIZE_EAX::LinearAddressBits

[Bits 15:8] Number of linear address bits.

UINT32 CPUID_VIR_PHY_ADDRESS_SIZE_EAX::PhysicalAddressBits

[Bits 7:0] Number of physical address bits.

Note
If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address number supported should come from this field.
UINT32 CPUID_VIR_PHY_ADDRESS_SIZE_EAX::Uint32

All bit fields as a 32-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Cpuid.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EFI_CONFIGURATION_TABLE64 Struct Reference

Data Fields
EFI_CONFIGURATION_TABLE64 Struct Reference

Data Fields

EFI_GUID | VendorGuid
UINT64 | VendorTable
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EFI_SMM_COMMUNICATION_CONTEXT Struct Reference

Data Fields
EFI_SMM_COMMUNICATION_CONTEXT Struct Reference

Data Fields

UINT32 | Signature
UINT32 | SwSmiNumber
EFI_PHYSICAL_ADDRESS | BufferPtrAddress
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EFI_SMM_SYSTEM_TABLE2_64 Struct Reference

Data Fields
EFI_SMM_SYSTEM_TABLE2_64 Struct Reference

Data Fields

EFI_TABLE_HEADER | Hdr
UINT64 | SmmFirmwareVendor
UINT64 | SmmFirmwareRevision
UINT64 | SmmInstallConfigurationTable
UINT64 | SmmIoMemRead
UINT64 | SmmIoMemWrite
UINT64 | SmmIoIoRead
UINT64 | SmmIoIoWrite
UINT64 | SmmAllocatePool
UINT64 | SmmFreePool
UINT64 | SmmAllocatePages
UINT64 | SmmFreePages
UINT64 | SmmStartupThisAp
UINT64 | CurrentlyExecutingCpu
UINT64 | NumberOfCpus
UINT64 | CpuSaveStateSize
UINT64 | CpuSaveState
UINT64 | NumberOfTableEntries
UINT64 | SmmConfigurationTable

Detailed Description

the whole picture is below:

+----------------------------——+ | | | Get Tseg Base MSR_C001_0112 | | Open SMRAM |— +----------------------------——+ | | +----------------------------——+<– | SMM_S3_RESUME_STATE | | Signature | <- SMRAM | Smst |— +----------------------------——+ | | +----------------------------——+<– | EFI_SMM_SYSTEM_TABLE2 | | NumberOfTableEntries | <- SMRAM | SmmConfigurationTable |— +----------------------------——+ | | +----------------------------——+<– | EFI_SMM_COMMUNICATION_CONTEXT | | SwSmiNumber | <- SMRAM | BufferPtrAddress |— +----------------------------——+ | | +----------------------------——+<– | Communication Buffer Pointer | <- AcpiNvs +----------------------------——+— | +----------------------------——+<– | EFI_SMM_COMMUNICATE_HEADER | | HeaderGuid | <- DRAM | MessageLength | +----------------------------——+ the whole picture is below:

+-------------------------------—+ | ACPI_VARIABLE_HOB | | SmramDescriptor | <- DRAM | CpuStart |— +-------------------------------—+ | | +-------------------------------—+<– | SMM_S3_RESUME_STATE | | Signature | <- SMRAM | Smst |— +-------------------------------—+ | | +-------------------------------—+<– | EFI_SMM_SYSTEM_TABLE2 | | NumberOfTableEntries | <- SMRAM | SmmConfigurationTable |— +-------------------------------—+ | | +-------------------------------—+<– | EFI_SMM_COMMUNICATION_CONTEXT | | SwSmiNumber | <- SMRAM | BufferPtrAddress |-------------— +-------------------------------—+ | | +-------------------------------—+ | | EFI_SMM_COMMUNICATION_ACPI_TABLE | | | SwSmiNumber | <- AcpiTable | | BufferPtrAddress |— | +-------------------------------—+ | | | | +-------------------------------—+<------------— | Communication Buffer Pointer | <- AcpiNvs +-------------------------------—+— | +-------------------------------—+<– | EFI_SMM_COMMUNICATE_HEADER | | HeaderGuid | <- DRAM | MessageLength | +-------------------------------—+

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC Struct Reference

Data Fields
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC Struct Reference

Data Fields

STM_RSC Resource
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION Struct Reference

Data Fields
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION Struct Reference

Data Fields

STM_RSC Resource
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_LOG_INVALID_PARAM Struct Reference

Data Fields
ENTRY_EVT_LOG_INVALID_PARAM Struct Reference

Data Fields

UINT32 VmcallApiNumber
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_LOG_STARTED Struct Reference

Data Fields
ENTRY_EVT_LOG_STARTED Struct Reference

Data Fields

UINT32 Reserved
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_LOG_STOPPED Struct Reference

Data Fields
ENTRY_EVT_LOG_STOPPED Struct Reference

Data Fields

UINT32 Reserved
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED Struct Reference

Data Fields
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED Struct Reference

Data Fields

UINT64 | VmcsPhysPointer
UINT8 | ExpectedDomainType
UINT8 | DegradedDomainType
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_MLE_RSC_PROT_DENIED Struct Reference

Data Fields
ENTRY_EVT_MLE_RSC_PROT_DENIED Struct Reference

Data Fields

STM_RSC Resource
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_MLE_RSC_PROT_GRANTED Struct Reference

Data Fields
ENTRY_EVT_MLE_RSC_PROT_GRANTED Struct Reference

Data Fields

STM_RSC Resource
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_MLE_RSC_UNPROT Struct Reference

Data Fields
ENTRY_EVT_MLE_RSC_UNPROT Struct Reference

Data Fields

STM_RSC Resource
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: ENTRY_EVT_MLE_RSC_UNPROT_ERROR Struct Reference

Data Fields
ENTRY_EVT_MLE_RSC_UNPROT_ERROR Struct Reference

Data Fields

STM_RSC Resource
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EXCEPTION0_STUB_HEADER Struct Reference

Data Fields
EXCEPTION0_STUB_HEADER Struct Reference

Data Fields

UINT8 | ExceptionStubHeader [HOOKAFTER_STUB_SIZE]
EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EXCEPTION_HANDLER_CONTEXT Struct Reference

Data Fields
EXCEPTION_HANDLER_CONTEXT Struct Reference

Data Fields

EFI_SYSTEM_CONTEXT_IA32 | SystemContext
BOOLEAN | ExceptionDataFlag
UINTN | OldIdtHandler
EFI_SYSTEM_CONTEXT_X64 | SystemContext
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EXCEPTION_HANDLER_DATA Struct Reference

Data Fields
EXCEPTION_HANDLER_DATA Struct Reference

Data Fields

UINTN | IdtEntryCount
SPIN_LOCK | DisplayMessageSpinLock
RESERVED_VECTORS_DATA * | ReservedVectors
EFI_CPU_INTERRUPT_HANDLER * | ExternalInterruptHandler
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: EXCEPTION_HANDLER_TEMPLATE_MAP Struct Reference

Data Fields
EXCEPTION_HANDLER_TEMPLATE_MAP Struct Reference

Data Fields

UINTN | ExceptionStart
UINTN | ExceptionStubHeaderSize
UINTN | HookAfterStubHeaderStart
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: FIXED_MTRR Struct Reference

Data Fields
FIXED_MTRR Struct Reference

Data Fields

UINT32 | Msr
UINT32 | BaseAddress
UINT32 | Length
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: IA32_GDT Union Reference

Data Fields
IA32_GDT Union Reference

Data Fields

struct {
UINT32 LimitLow: 16
UINT32 BaseLow: 16
UINT32 BaseMid: 8
UINT32 Type: 4
UINT32 System: 1
UINT32 Dpl: 2
UINT32 Present: 1
UINT32 LimitHigh: 4
UINT32 Software: 1
UINT32 Reserved: 1
UINT32 DefaultSize: 1
UINT32 Granularity: 1
UINT32 BaseHigh: 8
} Bits
UINT64 Uint64
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: IA32_VMX_MISC_REGISTER Union Reference

Data Fields
IA32_VMX_MISC_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 VmxTimerRatio:5
UINT32 VmExitEferLma:1
UINT32 HltActivityStateSupported:1
UINT32 ShutdownActivityStateSupported:1
UINT32 WaitForSipiActivityStateSupported:1
UINT32 Reserved1:5
UINT32 ProcessorTraceSupported:1
UINT32 SmBaseMsrSupported:1
UINT32 NumberOfCr3TargetValues:9
UINT32 MsrStoreListMaximum:3
UINT32 BlockSmiSupported:1
UINT32 VmWriteSupported:1
UINT32 VmInjectSupported:1
UINT32 Reserved2:1
UINT32 MsegRevisionIdentifier:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #IA32_VMX_MISC

Field Documentation

struct { ... } IA32_VMX_MISC_REGISTER::Bits

Individual bit fields

UINT32 IA32_VMX_MISC_REGISTER::BlockSmiSupported

[Bit 28] If read as 1, bit 2 of the IA32_SMM_MONITOR_CTL can be set to 1. VMXOFF unblocks SMIs unless IA32_SMM_MONITOR_CTL[bit 2] is 1 (see Section 34.14.4).

UINT32 IA32_VMX_MISC_REGISTER::HltActivityStateSupported

[Bit 6] reports (if set) the support for activity state 1 (HLT).

UINT32 IA32_VMX_MISC_REGISTER::MsegRevisionIdentifier

[Bits 63:32] Reports the 32-bit MSEG revision identifier used by the processor.

UINT32 IA32_VMX_MISC_REGISTER::MsrStoreListMaximum

[Bit 27:25] Bits 27:25 is used to compute the recommended maximum number of MSRs that should appear in the VM-exit MSR-store list, the VM-exit MSR-load list, or the VM-entry MSR-load list. Specifically, if the value bits 27:25 of IA32_VMX_MISC is N, then 512 * (N + 1) is the recommended maximum number of MSRs to be included in each list. If the limit is exceeded, undefined processor behavior may result (including a machine check during the VMX transition).

UINT32 IA32_VMX_MISC_REGISTER::NumberOfCr3TargetValues

[Bits 24:16] Indicate the number of CR3-target values supported by the processor. This number is a value between 0 and 256, inclusive (bit 24 is set if and only if bits 23:16 are clear).

UINT32 IA32_VMX_MISC_REGISTER::ProcessorTraceSupported

[Bit 14] If read as 1, Intel(R) Processor Trace (Intel PT) can be used in VMX operation. If the processor supports Intel PT but does not allow it to be used in VMX operation, execution of VMXON clears IA32_RTIT_CTL.TraceEn (see "VMXON-Enter VMX Operation" in Chapter 30); any attempt to set that bit while in VMX operation (including VMX root operation) using the WRMSR instruction causes a general-protection exception.

UINT32 IA32_VMX_MISC_REGISTER::ShutdownActivityStateSupported

[Bit 7] reports (if set) the support for activity state 2 (shutdown).

UINT32 IA32_VMX_MISC_REGISTER::SmBaseMsrSupported

[Bit 15] If read as 1, the RDMSR instruction can be used in system- management mode (SMM) to read the IA32_SMBASE MSR (MSR address 9EH). See Section 34.15.6.3.

UINT64 IA32_VMX_MISC_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 IA32_VMX_MISC_REGISTER::VmExitEferLma

[Bit 5] If bit 5 is read as 1, VM exits store the value of IA32_EFER.LMA into the "IA-32e mode guest" VM-entry control;see Section 27.2 for more details. This bit is read as 1 on any logical processor that supports the 1-setting of the "unrestricted guest" VM-execution control.

UINT32 IA32_VMX_MISC_REGISTER::VmInjectSupported

[Bit 30] If read as 1, VM entry allows injection of a software interrupt, software exception, or privileged software exception with an instruction length of 0.

UINT32 IA32_VMX_MISC_REGISTER::VmWriteSupported

[Bit 29] read as 1, software can use VMWRITE to write to any supported field in the VMCS; otherwise, VMWRITE cannot be used to modify VM-exit information fields.

UINT32 IA32_VMX_MISC_REGISTER::VmxTimerRatio

[Bits 4:0] Reports a value X that specifies the relationship between the rate of the VMX-preemption timer and that of the timestamp counter (TSC). Specifically, the VMX-preemption timer (if it is active) counts down by 1 every time bit X in the TSC changes due to a TSC increment.

UINT32 IA32_VMX_MISC_REGISTER::WaitForSipiActivityStateSupported

[Bit 8] reports (if set) the support for activity state 3 (wait-for-SIPI).

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_DCR Union Reference

Data Fields
LOCAL_APIC_DCR Union Reference

Data Fields

struct {
UINT32 DivideValue1:2
Low 2 bits of the divide value.
UINT32 Reserved0:1
Always 0.
UINT32 DivideValue2:1
Highest 1 bit of the divide value.
UINT32 Reserved1:28
Reserved.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_ICR_HIGH Union Reference

Data Fields
LOCAL_APIC_ICR_HIGH Union Reference

Data Fields

struct {
UINT32 Reserved0:24
Reserved.
UINT32 Destination:8
Specifies the target processor or processors in xAPIC mode.
} Bits
UINT32 Uint32
Destination field expanded to 32-bit in x2APIC mode.
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_ICR_LOW Union Reference

Data Fields
LOCAL_APIC_ICR_LOW Union Reference

Data Fields

struct {
UINT32 Vector:8
The vector number of the interrupt being sent.
UINT32 DeliveryMode:3
Specifies the type of IPI to be sent.
UINT32 DestinationMode:1
0: physical destination mode, 1: logical destination mode.
UINT32 DeliveryStatus:1
Indicates the IPI delivery status. This field is reserved in x2APIC mode.
UINT32 Reserved0:1
Reserved.
UINT32 Level:1
0 for the INIT level de-assert delivery mode. Otherwise 1.
UINT32 TriggerMode:1
0: edge, 1: level when using the INIT level de-assert delivery mode.
UINT32 Reserved1:2
Reserved.
UINT32 DestinationShorthand:2
A shorthand notation to specify the destination of the interrupt.
UINT32 Reserved2:12
Reserved.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_LVT_LINT Union Reference

Data Fields
LOCAL_APIC_LVT_LINT Union Reference

Data Fields

struct {
UINT32 Vector:8
The vector number of the interrupt being sent.
UINT32 DeliveryMode:3
Specifies the type of interrupt to be sent.
UINT32 Reserved0:1
Reserved.
UINT32 DeliveryStatus:1
0: Idle, 1: send pending.
UINT32 InputPinPolarity:1
Interrupt Input Pin Polarity.
UINT32 RemoteIrr:1
RO. Set when the local APIC accepts the interrupt and reset when an EOI is received.
UINT32 TriggerMode:1
0:edge, 1:level.
UINT32 Mask:1
0: Not masked, 1: Masked.
UINT32 Reserved1:15
Reserved.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_LVT_TIMER Union Reference

Data Fields
LOCAL_APIC_LVT_TIMER Union Reference

Data Fields

struct {
UINT32 Vector:8
The vector number of the interrupt being sent.
UINT32 Reserved0:4
Reserved.
UINT32 DeliveryStatus:1
0: Idle, 1: send pending.
UINT32 Reserved1:3
Reserved.
UINT32 Mask:1
0: Not masked, 1: Masked.
UINT32 TimerMode:1
0: One-shot, 1: Periodic.
UINT32 Reserved2:14
Reserved.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_MSI_ADDRESS Union Reference

Data Fields
LOCAL_APIC_MSI_ADDRESS Union Reference

Data Fields

struct {
UINT32 Reserved0:2
Reserved.
UINT32 DestinationMode:1
Specifies the Destination Mode.
UINT32 RedirectionHint:1
Specifies the Redirection Hint.
UINT32 Reserved1:8
Reserved.
UINT32 DestinationId:8
Specifies the Destination ID.
UINT32 BaseAddress:12
Must be 0FEEH.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_MSI_DATA Union Reference

Data Fields
LOCAL_APIC_MSI_DATA Union Reference

Data Fields

struct {
UINT32 Vector:8
Interrupt vector in range 010h..0FEH.
UINT32 DeliveryMode:3
Specifies the type of interrupt to be sent.
UINT32 Reserved0:3
Reserved.
UINT32 Level:1
0:Deassert, 1:Assert. Ignored for Edge triggered interrupts.
UINT32 TriggerMode:1
0:Edge, 1:Level.
UINT32 Reserved1:16
Reserved.
UINT32 Reserved2:32
Reserved.
} Bits
UINT64 Uint64
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_SVR Union Reference

Data Fields
LOCAL_APIC_SVR Union Reference

Data Fields

struct {
UINT32 SpuriousVector:8
Spurious Vector.
UINT32 SoftwareEnable:1
APIC Software Enable/Disable.
UINT32 FocusProcessorChecking:1
Focus Processor Checking.
UINT32 Reserved0:2
Reserved.
UINT32 EoiBroadcastSuppression:1
EOI-Broadcast Suppression.
UINT32 Reserved1:19
Reserved.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOCAL_APIC_VERSION Union Reference

Data Fields
LOCAL_APIC_VERSION Union Reference

Data Fields

struct {
UINT32 Version:8
The version numbers of the local APIC.
UINT32 Reserved0:8
Reserved.
UINT32 MaxLvtEntry:8
Number of LVT entries minus 1.
UINT32 EoiBroadcastSuppression:1
1 if EOI-broadcast suppression supported.
UINT32 Reserved1:7
Reserved.
} Bits
UINT32 Uint32
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/LocalApic.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOG_ENTRY_DATA Union Reference

Data Fields
LOG_ENTRY_DATA Union Reference

Data Fields

ENTRY_EVT_LOG_STARTED | Started
ENTRY_EVT_LOG_STOPPED | Stopped
ENTRY_EVT_LOG_INVALID_PARAM | InvalidParam
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION | HandledProtectionException
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC | BiosUnclaimedRsc
ENTRY_EVT_MLE_RSC_PROT_GRANTED | MleRscProtGranted
ENTRY_EVT_MLE_RSC_PROT_DENIED | MleRscProtDenied
ENTRY_EVT_MLE_RSC_UNPROT | MleRscUnprot
ENTRY_EVT_MLE_RSC_UNPROT_ERROR | MleRscUnprotError
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED | MleDomainTypeDegraded
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: LOG_ENTRY_HEADER Struct Reference

Data Fields
LOG_ENTRY_HEADER Struct Reference

#include <StmApi.h>

Data Fields

UINT32 | EventSerialNumber
UINT16 | Type
UINT16 | Lock:1
UINT16 | Valid:1
UINT16 | ReadByMle:1
UINT16 | Wrapped:1
UINT16 | Reserved:12

Detailed Description

Log Entry Header

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MEMORY_PROTECTION_RANGE Struct Reference

Data Fields
MEMORY_PROTECTION_RANGE Struct Reference

Data Fields

MEMORY_RANGE | Range
BOOLEAN | Present
BOOLEAN | Nx
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MEMORY_RANGE Struct Reference

Data Fields
MEMORY_RANGE Struct Reference

Data Fields

EFI_PHYSICAL_ADDRESS | Base
EFI_PHYSICAL_ADDRESS | Top
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MP_ASSEMBLY_ADDRESS_MAP Struct Reference

Data Fields
MP_ASSEMBLY_ADDRESS_MAP Struct Reference

Data Fields

UINT8 * | RendezvousFunnelAddress
UINTN | ModeEntryOffset
UINTN | RendezvousFunnelSize
UINT8 * | RelocateApLoopFuncAddress
UINTN | RelocateApLoopFuncSize
UINTN | ModeTransitionOffset
UINTN | PModeEntryOffset
UINTN | FlatJumpOffset
UINTN | Size
UINTN | LModeEntryOffset
UINTN | LongJumpOffset
The documentation for this struct was generated from the following files:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
  • UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MP_CPU_EXCHANGE_INFO Struct Reference

Data Fields
MP_CPU_EXCHANGE_INFO Struct Reference

Data Fields

UINTN | Lock
UINTN | StackStart
UINTN | StackSize
UINTN | CFunction
IA32_DESCRIPTOR | GdtrProfile
IA32_DESCRIPTOR | IdtrProfile
UINTN | BufferStart
UINTN | ModeOffset
UINTN | ApIndex
UINTN | CodeSegment
UINTN | DataSegment
UINTN | EnableExecuteDisable
UINTN | Cr3
UINTN | InitFlag
CPU_INFO_IN_HOB * | CpuInfo
UINTN | NumApsExecuting
CPU_MP_DATA * | CpuMpData
UINTN | InitializeFloatingPointUnitsAddress
UINT32 | ModeTransitionMemory
UINT16 | ModeTransitionSegment
UINT32 | ModeHighMemory
UINT16 | ModeHighSegment
VOID * | StackStart
VOID * | ApFunction
UINT32 | BufferStart
UINT32 | Cr3
The documentation for this struct was generated from the following files:
  • UefiCpuPkg/Library/MpInitLib/MpLib.h
  • UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSEG_HEADER Struct Reference

Data Fields
MSEG_HEADER Struct Reference

#include <ArchitecturalMsr.h>

Data Fields

UINT32 | MsegHeaderRevision
UINT32 | MonitorFeatures
UINT32 | GdtrLimit
UINT32 | GdtrBaseOffset
UINT32 | CsSelector
UINT32 | EipOffset
UINT32 | EspOffset
UINT32 | Cr3Offset
UINT8 | Reserved [SIZE_2KB-8 *sizeof(UINT32)]

Detailed Description

MSEG header that is located at the physical address specified by the MsegBase field of MSR_IA32_SMM_MONITOR_CTL_REGISTER.

Field Documentation

UINT32 MSEG_HEADER::MonitorFeatures

Bits 31:1 of this field are reserved and must be zero. Bit 0 of the field is the IA-32e mode SMM feature bit. It indicates whether the logical processor will be in IA-32e mode after the STM is activated.

UINT32 MSEG_HEADER::MsegHeaderRevision

Different processors may use different MSEG revision identifiers. These identifiers enable software to avoid using an MSEG header formatted for one processor on a processor that uses a different format. Software can discover the MSEG revision identifier that a processor uses by reading the VMX capability MSR IA32_VMX_MISC.

UINT8 MSEG_HEADER::Reserved[SIZE_2KB-8 *sizeof(UINT32)]

Pad header so total size is 2KB

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_BBL_CR_CTL3_REGISTER Union Reference

Data Fields
MSR_ATOM_BBL_CR_CTL3_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 L2HardwareEnabled:1
UINT32 Reserved1:7
UINT32 L2Enabled:1
UINT32 Reserved2:14
UINT32 L2NotPresent:1
UINT32 Reserved3:8
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_BBL_CR_CTL3

Field Documentation

struct { ... } MSR_ATOM_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input.

UINT32 MSR_ATOM_BBL_CR_CTL3_REGISTER::L2HardwareEnabled

[Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = Indicates if the L2 is hardware-disabled.

UINT32 MSR_ATOM_BBL_CR_CTL3_REGISTER::L2NotPresent

[Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.

UINT32 MSR_ATOM_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_ATOM_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
MSR_ATOM_EBL_CR_POWERON_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 DataErrorCheckingEnable:1
UINT32 ResponseErrorCheckingEnable:1
UINT32 AERR_DriveEnable:1
UINT32 BERR_Enable:1
UINT32 Reserved2:1
UINT32 Reserved3:1
UINT32 BINIT_DriverEnable:1
UINT32 Reserved4:1
UINT32 ExecuteBIST:1
UINT32 AERR_ObservationEnabled:1
UINT32 Reserved5:1
UINT32 BINIT_ObservationEnabled:1
UINT32 Reserved6:1
UINT32 ResetVector:1
UINT32 Reserved7:1
UINT32 APICClusterID:2
UINT32 Reserved8:2
UINT32 SymmetricArbitrationID:2
UINT32 IntegerBusFrequencyRatio:5
UINT32 Reserved9:5
UINT32 Reserved10:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_EBL_CR_POWERON

Field Documentation

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::AERR_DriveEnable

[Bit 3] AERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::AERR_ObservationEnabled

[Bit 10] AERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R/O) Always 00B.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::BERR_Enable

[Bit 4] BERR# Enable for initiator bus requests (R/W) 1 = Enabled; 0 = Disabled Always 0.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0.

struct { ... } MSR_ATOM_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::IntegerBusFrequencyRatio

[Bits 26:22] Integer Bus Frequency Ratio (R/O).

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Always 0.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B.

UINT32 MSR_ATOM_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_ATOM_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_FSB_FREQ_REGISTER Union Reference

Data Fields
MSR_ATOM_FSB_FREQ_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 ScalableBusSpeed:3
UINT32 Reserved1:29
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_FSB_FREQ

Field Documentation

struct { ... } MSR_ATOM_FSB_FREQ_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_FSB_FREQ_REGISTER::ScalableBusSpeed

[Bits 2:0] - Scalable Bus Speed

Atom Processor Family

111B: 083 MHz (FSB 333) 101B: 100 MHz (FSB 400) 001B: 133 MHz (FSB 533) 011B: 167 MHz (FSB 667)

133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B.

UINT32 MSR_ATOM_FSB_FREQ_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_ATOM_FSB_FREQ_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_ATOM_IA32_MISC_ENABLE_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:1
UINT32 Reserved4:1
UINT32 FERR:1
UINT32 BTS:1
UINT32 PEBS:1
UINT32 TM2:1
UINT32 Reserved5:2
UINT32 EIST:1
UINT32 Reserved6:1
UINT32 MONITOR:1
UINT32 Reserved7:1
UINT32 EISTLock:1
UINT32 Reserved8:1
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved9:8
UINT32 Reserved10:2
UINT32 XD:1
UINT32 Reserved11:29
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 0.

struct { ... } MSR_ATOM_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::EISTLock

[Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock (R/WO) When set, this bit causes the following bits to become read-only: - Enhanced Intel SpeedStep Technology Select Lock (this bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must be set before an Enhanced Intel SpeedStep Technology transition is requested. This bit is cleared on reset.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::FERR

[Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Unique. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::TM2

[Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermally managed state. The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this feature is not supported and BIOS must not alter the contents of the TM2 bit location. The processor is operating out of specification if both this bit and the TM1 bit are set to 0.

UINT64 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_ATOM_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_ATOM_PEBS_ENABLE_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_PEBS_ENABLE

Field Documentation

struct { ... } MSR_ATOM_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_PEBS_ENABLE_REGISTER::Enable

[Bit 0] Enable PEBS on IA32_PMC0. (R/W).

UINT32 MSR_ATOM_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_ATOM_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_PERF_STATUS_REGISTER Union Reference

Data Fields
MSR_ATOM_PERF_STATUS_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 CurrentPerformanceStateValue:16
UINT32 Reserved1:16
UINT32 Reserved2:8
UINT32 MaximumBusRatio:5
UINT32 Reserved3:19
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_PERF_STATUS

Field Documentation

struct { ... } MSR_ATOM_PERF_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_PERF_STATUS_REGISTER::CurrentPerformanceStateValue

[Bits 15:0] Current Performance State Value.

UINT32 MSR_ATOM_PERF_STATUS_REGISTER::MaximumBusRatio

[Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio configured for the processor.

UINT64 MSR_ATOM_PERF_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_PLATFORM_ID_REGISTER Union Reference

Data Fields
MSR_ATOM_PLATFORM_ID_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumQualifiedRatio:5
UINT32 Reserved2:19
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_PLATFORM_ID

Field Documentation

struct { ... } MSR_ATOM_PLATFORM_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_PLATFORM_ID_REGISTER::MaximumQualifiedRatio

[Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.

UINT32 MSR_ATOM_PLATFORM_ID_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_ATOM_PLATFORM_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_ATOM_THERM2_CTL_REGISTER Union Reference

Data Fields
MSR_ATOM_THERM2_CTL_REGISTER Union Reference

#include <AtomMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TM_SELECT:1
UINT32 Reserved2:15
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_ATOM_THERM2_CTL

Field Documentation

struct { ... } MSR_ATOM_THERM2_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_ATOM_THERM2_CTL_REGISTER::TM_SELECT

[Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.

UINT32 MSR_ATOM_THERM2_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_ATOM_THERM2_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/AtomMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <BroadwellMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Reserved1:28
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:5
UINT32 Ovf_Uncore:1
UINT32 OvfBuf:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS

Field Documentation

struct { ... } MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::CondChgd

[Bit 63] CondChgd.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr0

[Bit 32] Ovf_FixedCtr0.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr1

[Bit 33] Ovf_FixedCtr1.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr2

[Bit 34] Ovf_FixedCtr2.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC0

[Bit 0] Ovf_PMC0.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC1

[Bit 1] Ovf_PMC1.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC2

[Bit 2] Ovf_PMC2.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC3

[Bit 3] Ovf_PMC3.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_Uncore

[Bit 61] Ovf_Uncore.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::OvfBuf

[Bit 62] Ovf_BufDSSAVE.

UINT32 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Trace_ToPA_PMI

[Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical Addresses (ToPA).".

UINT64 MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

#include <BroadwellMsr.h>

Data Fields

struct {
UINT32 MAX_RATIO:7
UINT32 Reserved2:1
UINT32 MIN_RATIO:7
UINT32 Reserved3:17
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT

Field Documentation

struct { ... } MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER::MAX_RATIO

[Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the LLC/Ring.

UINT32 MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER::MIN_RATIO

[Bits 14:8] MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring.

UINT32 MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <BroadwellMsr.h>

Data Fields

struct {
UINT32 Limit:4
UINT32 Reserved1:6
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:9
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 CStateAutoDemotion:1
UINT32 CStateUndemotion:1
UINT32 Reserved4:1
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 State Auto Demotion Enable (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 Undemotion (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 State Auto Demotion Enable (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 Undemotion (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::CStateAutoDemotion

[Bit 29] Enable Package C-State Auto-demotion (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::CStateUndemotion

[Bit 30] Enable Package C-State Undemotion (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W).

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 3:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 0000b: C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.

UINT32 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <BroadwellMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Maximum5C:8
UINT32 Maximum6C:8
UINT32 Reserved:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5core active.

UINT32 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6core active.

UINT64 MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
MSR_CORE2_EBL_CR_POWERON_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 DataErrorCheckingEnable:1
UINT32 ResponseErrorCheckingEnable:1
UINT32 MCERR_DriveEnable:1
UINT32 AddressParityEnable:1
UINT32 Reserved2:1
UINT32 Reserved3:1
UINT32 BINIT_DriverEnable:1
UINT32 OutputTriStateEnable:1
UINT32 ExecuteBIST:1
UINT32 MCERR_ObservationEnabled:1
UINT32 IntelTXTCapableChipset:1
UINT32 BINIT_ObservationEnabled:1
UINT32 Reserved4:1
UINT32 ResetVector:1
UINT32 Reserved5:1
UINT32 APICClusterID:2
UINT32 NonIntegerBusRatio:1
UINT32 Reserved6:1
UINT32 SymmetricArbitrationID:2
UINT32 IntegerBusFrequencyRatio:5
UINT32 Reserved7:5
UINT32 Reserved8:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON

Field Documentation

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::AddressParityEnable

[Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R/O).

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.

struct { ... } MSR_CORE2_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::IntegerBusFrequencyRatio

[Bits 26:22] Integer Bus Frequency Ratio (R/O).

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::IntelTXTCapableChipset

[Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::MCERR_DriveEnable

[Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::MCERR_ObservationEnabled

[Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::NonIntegerBusRatio

[Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 = Non-integer ratio.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::OutputTriStateEnable

[Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R/O).

UINT32 MSR_CORE2_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_CORE2_FEATURE_CONTROL_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Reserved1:3
UINT32 SMRREnable:1
UINT32 Reserved2:28
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_CORE2_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_FEATURE_CONTROL_REGISTER::SMRREnable

[Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read visible and writeable while in SMM.

UINT32 MSR_CORE2_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_FSB_FREQ_REGISTER Union Reference

Data Fields
MSR_CORE2_FSB_FREQ_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 ScalableBusSpeed:3
UINT32 Reserved1:29
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_FSB_FREQ

Field Documentation

struct { ... } MSR_CORE2_FSB_FREQ_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_FSB_FREQ_REGISTER::ScalableBusSpeed

[Bits 2:0] - Scalable Bus Speed 101B: 100 MHz (FSB 400) 001B: 133 MHz (FSB 533) 011B: 167 MHz (FSB 667) 010B: 200 MHz (FSB 800) 000B: 267 MHz (FSB 1067) 100B: 333 MHz (FSB 1333)

133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B. 266.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 000B. 333.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 100B.

UINT32 MSR_CORE2_FSB_FREQ_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_FSB_FREQ_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_CORE2_IA32_MISC_ENABLE_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:1
UINT32 HardwarePrefetcherDisable:1
UINT32 FERR:1
UINT32 BTS:1
UINT32 PEBS:1
UINT32 TM2:1
UINT32 Reserved4:2
UINT32 EIST:1
UINT32 Reserved5:1
UINT32 MONITOR:1
UINT32 AdjacentCacheLinePrefetchDisable:1
UINT32 EISTLock:1
UINT32 Reserved6:1
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:2
UINT32 XD:1
UINT32 Reserved9:2
UINT32 DCUPrefetcherDisable:1
UINT32 IDADisable:1
UINT32 IPPrefetcherDisable:1
UINT32 Reserved10:24
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::AdjacentCacheLinePrefetchDisable

[Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set to 1, the processor fetches the cache line that contains data currently required by the processor. When set to 0, the processor fetches cache lines that comprise a cache line pair (128 bytes). Single processor platforms should not set this bit. Server platforms should set or clear this bit based on platform performance observed in validation and testing. BIOS may contain a setup option that controls the setting of this bit.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2.

struct { ... } MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::DCUPrefetcherDisable

[Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU L1 data cache prefetcher is disabled. The default value after reset is 0. BIOS may write '1' to disable this feature. The DCU prefetcher is an L1 data cache prefetcher. When the DCU prefetcher detects multiple loads from the same line done within a time limit, the DCU prefetcher assumes the next line will be required. The next line is prefetched in to the L1 data cache from memory or L2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::EISTLock

[Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock (R/WO) When set, this bit causes the following bits to become read-only: - Enhanced Intel SpeedStep Technology Select Lock (this bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must be set before an Enhanced Intel SpeedStep Technology transition is requested. This bit is cleared on reset.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::FERR

[Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::HardwarePrefetcherDisable

[Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the hardware prefetcher operation on streams of data. When clear (default), enables the prefetch queue. Disabling of the hardware prefetcher may impact processor performance.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::IDADisable

[Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of IDA is enabled. Note: the power-on default value is used by BIOS to detect hardware support of IDA. If power-on default value is 1, IDA is available in the processor. If power-on default value is 0, IDA is not available.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::IPPrefetcherDisable

[Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP prefetcher is disabled. The default value after reset is 0. BIOS may write '1' to disable this feature. The IP prefetcher is an L1 data cache prefetcher. The IP prefetcher looks for sequential load history to determine whether to prefetch the next expected data into the L1 cache from memory or L2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Shared. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::TM2

[Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermally managed state. The BIOS must enable this feature if the TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is not set, this feature is not supported and BIOS must not alter the contents of the TM2 bit location. The processor is operating out of specification if both this bit and the TM1 bit are set to 0.

UINT64 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_CORE2_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_CORE2_PEBS_ENABLE_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE

Field Documentation

struct { ... } MSR_CORE2_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_PEBS_ENABLE_REGISTER::Enable

[Bit 0] Enable PEBS on IA32_PMC0. (R/W).

UINT32 MSR_CORE2_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_PERF_CAPABILITIES_REGISTER Union Reference

Data Fields
MSR_CORE2_PERF_CAPABILITIES_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 LBR_FMT:6
UINT32 PEBS_FMT:1
UINT32 PEBS_ARCH_REG:1
UINT32 Reserved1:24
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES

Field Documentation

struct { ... } MSR_CORE2_PERF_CAPABILITIES_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_PERF_CAPABILITIES_REGISTER::LBR_FMT

[Bits 5:0] LBR Format. See Table 2-2.

UINT32 MSR_CORE2_PERF_CAPABILITIES_REGISTER::PEBS_ARCH_REG

[Bit 7] PEBSSaveArchRegs. See Table 2-2.

UINT32 MSR_CORE2_PERF_CAPABILITIES_REGISTER::PEBS_FMT

[Bit 6] PEBS Record Format.

UINT32 MSR_CORE2_PERF_CAPABILITIES_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_PERF_CAPABILITIES_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_PERF_STATUS_REGISTER Union Reference

Data Fields
MSR_CORE2_PERF_STATUS_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 CurrentPerformanceStateValue:16
UINT32 Reserved1:15
UINT32 XEOperation:1
UINT32 Reserved2:8
UINT32 MaximumBusRatio:5
UINT32 Reserved3:1
UINT32 NonIntegerBusRatio:1
UINT32 Reserved4:17
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_PERF_STATUS

Field Documentation

struct { ... } MSR_CORE2_PERF_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_PERF_STATUS_REGISTER::CurrentPerformanceStateValue

[Bits 15:0] Current Performance State Value.

UINT32 MSR_CORE2_PERF_STATUS_REGISTER::MaximumBusRatio

[Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio configured for the processor.

UINT32 MSR_CORE2_PERF_STATUS_REGISTER::NonIntegerBusRatio

[Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio is enabled. Applies processors based on Enhanced Intel Core microarchitecture.

UINT64 MSR_CORE2_PERF_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_CORE2_PERF_STATUS_REGISTER::XEOperation

[Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default is cleared.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_PLATFORM_ID_REGISTER Union Reference

Data Fields
MSR_CORE2_PLATFORM_ID_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumQualifiedRatio:5
UINT32 Reserved2:19
UINT32 Reserved3:18
UINT32 PlatformId:3
UINT32 Reserved4:11
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID

Field Documentation

struct { ... } MSR_CORE2_PLATFORM_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_PLATFORM_ID_REGISTER::MaximumQualifiedRatio

[Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.

UINT32 MSR_CORE2_PLATFORM_ID_REGISTER::PlatformId

[Bits 52:50] See Table 2-2.

UINT64 MSR_CORE2_PLATFORM_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_SMRR_PHYSBASE_REGISTER Union Reference

Data Fields
MSR_CORE2_SMRR_PHYSBASE_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Reserved1:12
UINT32 PhysBase:20
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE

Field Documentation

struct { ... } MSR_CORE2_SMRR_PHYSBASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_SMRR_PHYSBASE_REGISTER::PhysBase

[Bits 31:12] PhysBase. SMRR physical Base Address.

UINT32 MSR_CORE2_SMRR_PHYSBASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_SMRR_PHYSBASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_SMRR_PHYSMASK_REGISTER Union Reference

Data Fields
MSR_CORE2_SMRR_PHYSMASK_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Reserved1:11
UINT32 Valid:1
UINT32 PhysMask:20
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK

Field Documentation

struct { ... } MSR_CORE2_SMRR_PHYSMASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_SMRR_PHYSMASK_REGISTER::PhysMask

[Bits 31:12] PhysMask. SMRR physical address range mask.

UINT32 MSR_CORE2_SMRR_PHYSMASK_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_SMRR_PHYSMASK_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_CORE2_SMRR_PHYSMASK_REGISTER::Valid

[Bit 11] Valid. Physical address base and range mask are valid.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE2_THERM2_CTL_REGISTER Union Reference

Data Fields
MSR_CORE2_THERM2_CTL_REGISTER Union Reference

#include <Core2Msr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TM_SELECT:1
UINT32 Reserved2:15
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE2_THERM2_CTL

Field Documentation

struct { ... } MSR_CORE2_THERM2_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE2_THERM2_CTL_REGISTER::TM_SELECT

[Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.

UINT32 MSR_CORE2_THERM2_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE2_THERM2_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Core2Msr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE_BBL_CR_CTL3_REGISTER Union Reference

Data Fields
MSR_CORE_BBL_CR_CTL3_REGISTER Union Reference

#include <CoreMsr.h>

Data Fields

struct {
UINT32 L2HardwareEnabled:1
UINT32 Reserved1:7
UINT32 L2Enabled:1
UINT32 Reserved2:14
UINT32 L2NotPresent:1
UINT32 Reserved3:8
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE_BBL_CR_CTL3

Field Documentation

struct { ... } MSR_CORE_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input.

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::L2HardwareEnabled

[Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = Indicates if the L2 is hardware-disabled.

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::L2NotPresent

[Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.

UINT32 MSR_CORE_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/CoreMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
MSR_CORE_EBL_CR_POWERON_REGISTER Union Reference

#include <CoreMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 DataErrorCheckingEnable:1
UINT32 ResponseErrorCheckingEnable:1
UINT32 MCERR_DriveEnable:1
UINT32 AddressParityEnable:1
UINT32 Reserved2:2
UINT32 BINIT_DriverEnable:1
UINT32 OutputTriStateEnable:1
UINT32 ExecuteBIST:1
UINT32 MCERR_ObservationEnabled:1
UINT32 Reserved3:1
UINT32 BINIT_ObservationEnabled:1
UINT32 Reserved4:1
UINT32 ResetVector:1
UINT32 Reserved5:1
UINT32 APICClusterID:2
UINT32 SystemBusFrequency:1
UINT32 Reserved6:1
UINT32 SymmetricArbitrationID:2
UINT32 ClockFrequencyRatio:5
UINT32 Reserved7:5
UINT32 Reserved8:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE_EBL_CR_POWERON

Field Documentation

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::AddressParityEnable

[Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R/O).

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.

struct { ... } MSR_CORE_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio

[Bits 26:22] Clock Frequency Ratio (R/O).

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::MCERR_DriveEnable

[Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::MCERR_ObservationEnabled

[Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::OutputTriStateEnable

[Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not all processor implements R/W.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R/O).

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::SystemBusFrequency

[Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved.

UINT32 MSR_CORE_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/CoreMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE_FSB_FREQ_REGISTER Union Reference

Data Fields
MSR_CORE_FSB_FREQ_REGISTER Union Reference

#include <CoreMsr.h>

Data Fields

struct {
UINT32 ScalableBusSpeed:3
UINT32 Reserved1:29
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE_FSB_FREQ

Field Documentation

struct { ... } MSR_CORE_FSB_FREQ_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_FSB_FREQ_REGISTER::ScalableBusSpeed

[Bits 2:0] - Scalable Bus Speed 101B: 100 MHz (FSB 400) 001B: 133 MHz (FSB 533) 011B: 167 MHz (FSB 667)

133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 101B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B.

UINT32 MSR_CORE_FSB_FREQ_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE_FSB_FREQ_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/CoreMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE_IA32_EFER_REGISTER Union Reference

Data Fields
MSR_CORE_IA32_EFER_REGISTER Union Reference

#include <CoreMsr.h>

Data Fields

struct {
UINT32 Reserved1:11
UINT32 NXE:1
UINT32 Reserved2:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE_IA32_EFER

Field Documentation

struct { ... } MSR_CORE_IA32_EFER_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_IA32_EFER_REGISTER::NXE

[Bit 11] Execute Disable Bit Enable.

UINT32 MSR_CORE_IA32_EFER_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE_IA32_EFER_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/CoreMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_CORE_IA32_MISC_ENABLE_REGISTER Union Reference

#include <CoreMsr.h>

Data Fields

struct {
UINT32 Reserved1:3
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:2
UINT32 FERR:1
UINT32 BTS:1
UINT32 Reserved4:1
UINT32 TM2:1
UINT32 Reserved5:2
UINT32 EIST:1
UINT32 Reserved6:1
UINT32 MONITOR:1
UINT32 Reserved7:1
UINT32 Reserved8:2
UINT32 LimitCpuidMaxval:1
UINT32 Reserved9:9
UINT32 Reserved10:2
UINT32 XD:1
UINT32 Reserved11:29
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2.

struct { ... } MSR_CORE_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) 1 = Enhanced Intel SpeedStep Technology enabled.

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::FERR

[Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage.

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 2-2. Setting this bit may cause behavior in software that depends on the availability of CPUID leaves greater than 2.

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Shared. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::TM2

[Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the pre-determined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermal managed state. If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then this feature is not supported and BIOS must not alter the contents of this bit location. The processor is operating out of spec if both this bit and the TM1 bit are set to disabled states.

UINT64 MSR_CORE_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_CORE_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Shared. XD Bit Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/CoreMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_CORE_THERM2_CTL_REGISTER Union Reference

Data Fields
MSR_CORE_THERM2_CTL_REGISTER Union Reference

#include <CoreMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TM_SELECT:1
UINT32 Reserved2:15
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_CORE_THERM2_CTL

Field Documentation

struct { ... } MSR_CORE_THERM2_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_CORE_THERM2_CTL_REGISTER::TM_SELECT

[Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.

UINT32 MSR_CORE_THERM2_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_CORE_THERM2_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/CoreMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 PROCHOTStatus:1
UINT32 ThermalStatus:1
UINT32 PL1Status:1
UINT32 PL2Status:1
UINT32 Reserved1:5
UINT32 PowerLimitingStatus:1
UINT32 VRThermAlertStatus:1
UINT32 MaxTurboLimitStatus:1
UINT32 ElectricalDesignPointStatus:1
UINT32 TurboTransitionAttenuationStatus:1
UINT32 MaximumEfficiencyFrequencyStatus:1
UINT32 Reserved2:1
UINT32 PROCHOT:1
UINT32 ThermalLog:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 Reserved3:5
UINT32 CorePowerLimitingLog:1
UINT32 VRThermAlertLog:1
UINT32 MaxTurboLimitLog:1
UINT32 ElectricalDesignPointLog:1
UINT32 TurboTransitionAttenuationLog:1
UINT32 MaximumEfficiencyFrequencyLog:1
UINT32 Reserved4:1
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS

Field Documentation

struct { ... } MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::CorePowerLimitingLog

[Bit 25] Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog

[Bit 28] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 12] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaximumEfficiencyFrequencyLog

[Bit 30] Maximum Efficiency Frequency Log When set, indicates that the Maximum Efficiency Frequency Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaximumEfficiencyFrequencyStatus

[Bit 14] Maximum Efficiency Frequency Status (R0) When set, frequency is reduced below the maximum efficiency frequency.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitLog

[Bit 27] Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitStatus

[Bit 11] Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 18] Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Status

[Bit 2] Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 19] Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 3] Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PowerLimitingStatus

[Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOTStatus

[Bit 0] PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationLog

[Bit 29] Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationStatus

[Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 26] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 10] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_FEATURE_CONTROL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Lock:1
UINT32 EnableVmxInsideSmx:1
UINT32 EnableVmxOutsideSmx:1
UINT32 Reserved1:5
UINT32 SenterLocalFunctionEnables:7
UINT32 SenterGlobalEnable:1
UINT32 Reserved2:2
UINT32 SgxEnable:1
UINT32 Reserved3:13
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::EnableVmxInsideSmx

[Bit 1] Enable VMX inside SMX operation (R/WL)

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::EnableVmxOutsideSmx

[Bit 2] Enable VMX outside SMX operation (R/WL)

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::Lock

[Bit 0] Lock bit (R/WL)

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::SenterGlobalEnable

[Bit 15] SENTER global functions enable (R/WL)

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::SenterLocalFunctionEnables

[Bits 14:8] SENTER local function enables (R/WL)

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::SgxEnable

[Bit 18] SGX global functions enable (R/WL)

UINT32 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 CBM:20
UINT32 Reserved1:12
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_IA32_L2_QOS_MASK_3.

Field Documentation

struct { ... } MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER::CBM

[Bits 19:0] CBM: Bit vector of available L2 ways for COS 0 enforcement

UINT32 MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 CBM:8
UINT32 Reserved1:24
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_GOLDMONT_IA32_L2_QOS_MASK_0 to #MSR_GOLDMONT_IA32_L2_QOS_MASK_2.

Field Documentation

struct { ... } MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER::CBM

[Bits 7:0] CBM: Bit vector of available L2 ways for COS 0 enforcement

UINT32 MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:3
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved4:3
UINT32 EIST:1
UINT32 Reserved5:1
UINT32 MONITOR:1
UINT32 Reserved6:3
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:2
UINT32 XD:1
UINT32 Reserved9:3
UINT32 TurboModeDisable:1
UINT32 Reserved10:25
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Package. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 1.

struct { ... } MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Core. Fast-Strings Enable See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

UINT64 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Package. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Reserved1:28
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET

Field Documentation

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI

[Bit 60] Set 1 to clear ASCI.

struct { ... } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd

[Bit 63] Set 1 to clear CondChgd.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz

[Bit 59] Set 1 to clear CTR_Frz.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz

[Bit 58] Set 1 to clear LBR_Frz.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_BufDSSAVE

[Bit 62] Set 1 to clear Ovf_BufDSSAVE.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr0

[Bit 32] Set 1 to clear Ovf_FixedCtr0.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr1

[Bit 33] Set 1 to clear Ovf_FixedCtr1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr2

[Bit 34] Set 1 to clear Ovf_FixedCtr2.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC0

[Bit 0] Set 1 to clear Ovf_PMC0.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC1

[Bit 1] Set 1 to clear Ovf_PMC1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC2

[Bit 2] Set 1 to clear Ovf_PMC2.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC3

[Bit 3] Set 1 to clear Ovf_PMC3.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to clear Ovf_Uncore.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to clear Trace_ToPA_PMI.

UINT64 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Reserved1:28
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 Reserved4:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET

Field Documentation

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::ASCI

[Bit 60] Set 1 to cause ASCI = 1.

struct { ... } MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::CTR_Frz

[Bit 59] Set 1 to cause CTR_Frz = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::LBR_Frz

[Bit 58] Set 1 to cause LBR_Frz = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_BufDSSAVE

[Bit 62] Set 1 to cause Ovf_BufDSSAVE.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr0

[Bit 32] Set 1 to cause Ovf_FixedCtr0 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr1

[Bit 33] Set 1 to cause Ovf_FixedCtr1 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr2

[Bit 34] Set 1 to cause Ovf_FixedCtr2 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC0

[Bit 0] Set 1 to cause Ovf_PMC0 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC1

[Bit 1] Set 1 to cause Ovf_PMC1 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC2

[Bit 2] Set 1 to cause Ovf_PMC2 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC3

[Bit 3] Set 1 to cause Ovf_PMC3 = 1.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to cause Ovf_Uncore.

UINT32 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to cause Trace_ToPA_PMI = 1.

UINT64 MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 COS:2
UINT32 Reserved2:30
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_IA32_PQR_ASSOC

Field Documentation

struct { ... } MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER::COS

[Bits 33:32] COS (R/W).

UINT64 MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 TraceEn:1
UINT32 CYCEn:1
UINT32 OS:1
UINT32 User:1
UINT32 Reserved1:3
UINT32 CR3:1
UINT32 ToPA:1
UINT32 MTCEn:1
UINT32 TSCEn:1
UINT32 DisRETC:1
UINT32 Reserved2:1
UINT32 BranchEn:1
UINT32 MTCFreq:4
UINT32 Reserved3:1
UINT32 CYCThresh:4
UINT32 Reserved4:1
UINT32 PSBFreq:4
UINT32 Reserved5:4
UINT32 ADDR0_CFG:4
UINT32 ADDR1_CFG:4
UINT32 Reserved6:24
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_RTIT_CTL

Field Documentation

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::ADDR0_CFG

[Bits 35:32] ADDR0_CFG.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::ADDR1_CFG

[Bits 39:36] ADDR1_CFG.

struct { ... } MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::BranchEn

[Bit 13] BranchEn.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::CR3

[Bit 7] CR3 filter.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::CYCEn

[Bit 1] CYCEn.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::CYCThresh

[Bits 22:19] CYCThresh.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::DisRETC

[Bit 11] DisRETC.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::MTCEn

[Bit 9] MTCEn.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::MTCFreq

[Bits 17:14] MTCFreq.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::OS

[Bit 2] OS.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::PSBFreq

[Bits 27:24] PSBFreq.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::ToPA

[Bit 8] ToPA. Writing 0 will #GP if also setting TraceEn.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::TraceEn

[Bit 0] TraceEn.

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::TSCEn

[Bit 10] TSCEn.

UINT64 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER::User

[Bit 3] User.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 FromLinearAddress:32
UINT32 FromLinearAddressHi:16
UINT32 SignedExtension:15
UINT32 Mispred:1
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_FROM_IP to #MSR_GOLDMONT_LASTBRANCH_31_FROM_IP.

Field Documentation

struct { ... } MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::FromLinearAddress

[Bit 31:0] From Linear Address (R/W).

UINT32 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::FromLinearAddressHi

[Bit 47:32] From Linear Address (R/W).

UINT32 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::Mispred

[Bit 63] Mispred.

UINT32 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::SignedExtension

[Bits 62:48] Signed extension of bits 47:0.

UINT32 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 TargetLinearAddress:32
UINT32 TargetLinearAddressHi:16
UINT32 ElapsedCycles:16
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_GOLDMONT_LASTBRANCH_0_TO_IP to #MSR_GOLDMONT_LASTBRANCH_31_TO_IP.

Field Documentation

struct { ... } MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER::ElapsedCycles

[Bits 63:48] Elapsed cycles from last update to the LBR.

UINT32 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER::TargetLinearAddress

[Bit 31:0] Target Linear Address (R/W).

UINT32 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER::TargetLinearAddressHi

[Bit 47:32] Target Linear Address (R/W).

UINT32 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_LBR_SELECT_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_LBR_SELECT_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 CPL_EQ_0:1
UINT32 CPL_NEQ_0:1
UINT32 JCC:1
UINT32 NEAR_REL_CALL:1
UINT32 NEAR_IND_CALL:1
UINT32 NEAR_RET:1
UINT32 NEAR_IND_JMP:1
UINT32 NEAR_REL_JMP:1
UINT32 FAR_BRANCH:1
UINT32 EN_CALL_STACK:1
UINT32 Reserved1:22
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_LBR_SELECT

Field Documentation

struct { ... } MSR_GOLDMONT_LBR_SELECT_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::CPL_EQ_0

[Bit 0] CPL_EQ_0.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::CPL_NEQ_0

[Bit 1] CPL_NEQ_0.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::EN_CALL_STACK

[Bit 9] EN_CALL_STACK.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::FAR_BRANCH

[Bit 8] FAR_BRANCH.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::JCC

[Bit 2] JCC.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::NEAR_IND_CALL

[Bit 4] NEAR_IND_CALL.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::NEAR_IND_JMP

[Bit 6] NEAR_IND_JMP.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::NEAR_REL_CALL

[Bit 3] NEAR_REL_CALL.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::NEAR_REL_JMP

[Bit 7] NEAR_REL_JMP.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::NEAR_RET

[Bit 5] NEAR_RET.

UINT32 MSR_GOLDMONT_LBR_SELECT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_LBR_SELECT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 L2HardwarePrefetcherDisable:1
UINT32 Reserved1:1
UINT32 DCUHardwarePrefetcherDisable:1
UINT32 Reserved2:29
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_MISC_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache.

UINT32 MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache.

UINT32 MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 EISTHardwareCoordinationDisable:1
UINT32 Reserved1:21
UINT32 ThermalInterruptCoordinationEnable:1
UINT32 Reserved2:9
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_MISC_PWR_MGMT

Field Documentation

struct { ... } MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER::EISTHardwareCoordinationDisable

[Bit 0] EIST Hardware Coordination Disable (R/W) When 0, enables hardware coordination of Enhanced Intel Speedstep Technology request from processor cores; When 1, disables hardware coordination of Enhanced Intel Speedstep Technology requests.

UINT32 MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER::ThermalInterruptCoordinationEnable

[Bit 22] Thermal Interrupt Coordination Enable (R/W) If set, then thermal interrupt on one core is routed to all cores.

UINT32 MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PEBS_ENABLE_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PEBS_ENABLE

Field Documentation

struct { ... } MSR_GOLDMONT_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PEBS_ENABLE_REGISTER::Enable

[Bit 0] Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC0. (R/W).

UINT32 MSR_GOLDMONT_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Limit:4
UINT32 Reserved1:6
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:16
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register until next reset.

UINT32 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

UINT32 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 3:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power). for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 0000b: No limit 0001b: C1 0010b: C3 0011b: C6 0100b: C7 0101b: C7S 0110b: C8 0111b: C9 1000b: C10.

UINT32 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PKG_POWER_INFO_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 ThermalSpecPower:15
UINT32 Reserved1:1
UINT32 MinimumPower:15
UINT32 Reserved2:1
UINT32 MaximumPower:15
UINT32 Reserved3:1
UINT32 MaximumTimeWindow:7
UINT32 Reserved4:9
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PKG_POWER_INFO

Field Documentation

struct { ... } MSR_GOLDMONT_PKG_POWER_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER::MaximumPower

[Bits 46:32] Maximum Power (R/W) See Section 14.9.3, "Package RAPL Domain.".

UINT32 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER::MaximumTimeWindow

[Bits 54:48] Maximum Time Window (R/W) Specified by 2^Y * (1.0 + Z/4.0) * Time_Unit, where "Y" is the unsigned integer value represented. by bits 52:48, "Z" is an unsigned integer represented by bits 54:53. "Time_Unit" is specified by the "Time Units" field of MSR_RAPL_POWER_UNIT.

UINT32 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER::MinimumPower

[Bits 30:16] Minimum Power (R/W) See Section 14.9.3, "Package RAPL Domain.".

UINT32 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER::ThermalSpecPower

[Bits 14:0] Thermal Spec Power (R/W) See Section 14.9.3, "Package RAPL Domain.".

UINT64 MSR_GOLDMONT_PKG_POWER_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PKGC3_IRTL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PKGC3_IRTL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 InterruptResponseTimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PKGC3_IRTL

Field Documentation

struct { ... } MSR_GOLDMONT_PKGC3_IRTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PKGC3_IRTL_REGISTER::InterruptResponseTimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C3 state.

UINT32 MSR_GOLDMONT_PKGC3_IRTL_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-19 for supported time unit encodings.

UINT32 MSR_GOLDMONT_PKGC3_IRTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_PKGC3_IRTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_GOLDMONT_PKGC3_IRTL_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PKGC_IRTL1_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PKGC_IRTL1_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 InterruptResponseTimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL1

Field Documentation

struct { ... } MSR_GOLDMONT_PKGC_IRTL1_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PKGC_IRTL1_REGISTER::InterruptResponseTimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 or C7S state.

UINT32 MSR_GOLDMONT_PKGC_IRTL1_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-19 for supported time unit encodings.

UINT32 MSR_GOLDMONT_PKGC_IRTL1_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_PKGC_IRTL1_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_GOLDMONT_PKGC_IRTL1_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PKGC_IRTL2_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PKGC_IRTL2_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 InterruptResponseTimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PKGC_IRTL2

Field Documentation

struct { ... } MSR_GOLDMONT_PKGC_IRTL2_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PKGC_IRTL2_REGISTER::InterruptResponseTimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C7 state.

UINT32 MSR_GOLDMONT_PKGC_IRTL2_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-19 for supported time unit encodings.

UINT32 MSR_GOLDMONT_PKGC_IRTL2_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_PKGC_IRTL2_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_GOLDMONT_PKGC_IRTL2_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PLATFORM_INFO_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:12
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 TJOFFSET:1
UINT32 Reserved3:1
UINT32 Reserved4:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved5:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PLATFORM_INFO

Field Documentation

struct { ... } MSR_GOLDMONT_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_GOLDMONT_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_GOLDMONT_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_GOLDMONT_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT32 MSR_GOLDMONT_PLATFORM_INFO_REGISTER::TJOFFSET

[Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to specify an temperature offset.

UINT64 MSR_GOLDMONT_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER Union Reference

#include <GoldmontPlusMsr.h>

Data Fields

struct {
UINT32 Fix_Me_1:1
UINT32 Fix_Me_2:1
UINT32 Fix_Me_3:1
UINT32 Fix_Me_4:1
UINT32 Reserved1:28
UINT32 Fix_Me_5:1
UINT32 Fix_Me_6:1
UINT32 Fix_Me_7:1
UINT32 Reserved2:29
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_PLUS_PEBS_ENABLE

Field Documentation

struct { ... } MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_1

[Bit 0] Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC0.

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_2

[Bit 1] Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC1.

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_3

[Bit 2] Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC2.

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_4

[Bit 3] Enable PEBS trigger and recording for the programmed event (precise or otherwise) on IA32_PMC3.

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_5

[Bit 32] Enable PEBS trigger and recording for IA32_FIXED_CTR0.

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_6

[Bit 33] Enable PEBS trigger and recording for IA32_FIXED_CTR1.

UINT32 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Fix_Me_7

[Bit 34] Enable PEBS trigger and recording for IA32_FIXED_CTR2.

UINT64 MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_POWER_CTL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_POWER_CTL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 C1EEnable:1
UINT32 Reserved2:30
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_POWER_CTL

Field Documentation

struct { ... } MSR_GOLDMONT_POWER_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_POWER_CTL_REGISTER::C1EEnable

[Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1).

UINT32 MSR_GOLDMONT_POWER_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_POWER_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnit:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Energy Status Units. Energy related information (in Joules) is in unit of, 1Joule/ (2^ESU); where ESU is an unsigned integer represented by bits 12:8. Default value is 01110b, indicating energy unit is in 61 microJoules.

UINT32 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Power Units. Power related information (in Watts) is in unit of, 1W/2^PU; where PU is an unsigned integer represented by bits 3:0. Default value is 1000b, indicating power unit is in 3.9 milliWatts increment.

UINT32 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER::TimeUnit

[Bits 19:16] Time Unit. Time related information (in seconds) is in unit of, 1S/2^TU; where TU is an unsigned integer represented by bits 19:16. Default value is 1010b, indicating power unit is in 0.977 millisecond.

UINT32 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Lock:1
UINT32 Reserved1:1
UINT32 SMM_Code_Chk_En:1
UINT32 Reserved2:29
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_SMM_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER::Lock

[Bit 0] Lock (SMM-RWO) When set to '1' locks this register from further changes.

UINT32 MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER::SMM_Code_Chk_En

[Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the logical processors are prevented from executing SMM code outside the ranges defined by the SMRR. When set to '1' any logical processor in the package that attempts to execute SMM code not within the ranges defined by the SMRR will assert an unrecoverable MCE.

UINT32 MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_SMM_MCA_CAP_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:26
UINT32 SMM_Code_Access_Chk:1
UINT32 Long_Flow_Indication:1
UINT32 Reserved3:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_SMM_MCA_CAP

Field Documentation

struct { ... } MSR_GOLDMONT_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and the MSR_SMM_DELAYED is supported.

UINT32 MSR_GOLDMONT_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and the MSR_SMM_FEATURE_CONTROL is supported.

UINT64 MSR_GOLDMONT_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 MAX_NON_TURBO_RATIO:8
UINT32 Reserved1:23
UINT32 TURBO_ACTIVATION_RATIO_Lock:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_TURBO_ACTIVATION_RATIO

Field Documentation

struct { ... } MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER::MAX_NON_TURBO_RATIO

[Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this field.

UINT32 MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER::TURBO_ACTIVATION_RATIO_Lock

[Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the content of this register is locked until a reset.

UINT32 MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 CoreCountThresholdGroup0:8
UINT32 CoreCountThresholdGroup1:8
UINT32 CoreCountThresholdGroup2:8
UINT32 CoreCountThresholdGroup3:8
UINT32 CoreCountThresholdGroup4:8
UINT32 CoreCountThresholdGroup5:8
UINT32 CoreCountThresholdGroup6:8
UINT32 CoreCountThresholdGroup7:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_TURBO_GROUP_CORECNT

Field Documentation

struct { ... } MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup0

[Bits 7:0] Package. Group 0 Core Count Threshold Maximum number of active cores to operate under Group 0 Max Turbo Ratio limit.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup1

[Bits 15:8] Package. Group 1 Core Count Threshold Maximum number of active cores to operate under Group 1 Max Turbo Ratio limit. Must be greater than Group 0 Core Count.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup2

[Bits 23:16] Package. Group 2 Core Count Threshold Maximum number of active cores to operate under Group 2 Max Turbo Ratio limit. Must be greater than Group 1 Core Count.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup3

[Bits 31:24] Package. Group 3 Core Count Threshold Maximum number of active cores to operate under Group 3 Max Turbo Ratio limit. Must be greater than Group 2 Core Count.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup4

[Bits 39:32] Package. Group 4 Core Count Threshold Maximum number of active cores to operate under Group 4 Max Turbo Ratio limit. Must be greater than Group 3 Core Count.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup5

[Bits 47:40] Package. Group 5 Core Count Threshold Maximum number of active cores to operate under Group 5 Max Turbo Ratio limit. Must be greater than Group 4 Core Count.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup6

[Bits 55:48] Package. Group 6 Core Count Threshold Maximum number of active cores to operate under Group 6 Max Turbo Ratio limit. Must be greater than Group 5 Core Count.

UINT32 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::CoreCountThresholdGroup7

[Bits 63:56] Package. Group 7 Core Count Threshold Maximum number of active cores to operate under Group 7 Max Turbo Ratio limit. Must be greater than Group 6 Core Count and not less than the total number of processor cores in the package. E.g. specify 255.

UINT64 MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <GoldmontMsr.h>

Data Fields

struct {
UINT32 MaxRatioLimitGroup0:8
UINT32 MaxRatioLimitGroup1:8
UINT32 MaxRatioLimitGroup2:8
UINT32 MaxRatioLimitGroup3:8
UINT32 MaxRatioLimitGroup4:8
UINT32 MaxRatioLimitGroup5:8
UINT32 MaxRatioLimitGroup6:8
UINT32 MaxRatioLimitGroup7:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_GOLDMONT_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup0

[Bits 7:0] Package. Maximum Ratio Limit for Active cores in Group 0 Maximum turbo ratio limit when number of active cores is less or equal to Group 0 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup1

[Bits 15:8] Package. Maximum Ratio Limit for Active cores in Group 1 Maximum turbo ratio limit when number of active cores is less or equal to Group 1 threshold and greater than Group 0 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup2

[Bits 23:16] Package. Maximum Ratio Limit for Active cores in Group 2 Maximum turbo ratio limit when number of active cores is less or equal to Group 2 threshold and greater than Group 1 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup3

[Bits 31:24] Package. Maximum Ratio Limit for Active cores in Group 3 Maximum turbo ratio limit when number of active cores is less or equal to Group 3 threshold and greater than Group 2 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup4

[Bits 39:32] Package. Maximum Ratio Limit for Active cores in Group 4 Maximum turbo ratio limit when number of active cores is less or equal to Group 4 threshold and greater than Group 3 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup5

[Bits 47:40] Package. Maximum Ratio Limit for Active cores in Group 5 Maximum turbo ratio limit when number of active cores is less or equal to Group 5 threshold and greater than Group 4 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup6

[Bits 55:48] Package. Maximum Ratio Limit for Active cores in Group 6 Maximum turbo ratio limit when number of active cores is less or equal to Group 6 threshold and greater than Group 5 threshold.

UINT32 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup7

[Bits 63:56] Package. Maximum Ratio Limit for Active cores in Group 7 Maximum turbo ratio limit when number of active cores is less or equal to Group 7 threshold and greater than Group 6 threshold.

UINT64 MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Union Reference

Data Fields
MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 TDP_LEVEL:2
UINT32 Reserved1:29
UINT32 Config_TDP_Lock:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_CONTROL

Field Documentation

struct { ... } MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER::Config_TDP_Lock

[Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of this register is locked until a reset.

UINT32 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER::TDP_LEVEL

[Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.

UINT32 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Union Reference

Data Fields
MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PKG_TDP_LVL1:15
UINT32 Reserved1:1
UINT32 Config_TDP_LVL1_Ratio:8
UINT32 Reserved2:8
UINT32 PKG_MAX_PWR_LVL1:15
UINT32 PKG_MIN_PWR_LVL1:16
UINT32 Reserved3:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL1

Field Documentation

struct { ... } MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER::Config_TDP_LVL1_Ratio

[Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used for this specific processor.

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER::PKG_MAX_PWR_LVL1

[Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP Level 1.

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER::PKG_MIN_PWR_LVL1

[Bits 62:47] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP Level 1.

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER::PKG_TDP_LVL1

[Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.

UINT64 MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Union Reference

Data Fields
MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PKG_TDP_LVL2:15
UINT32 Reserved1:1
UINT32 Config_TDP_LVL2_Ratio:8
UINT32 Reserved2:8
UINT32 PKG_MAX_PWR_LVL2:15
UINT32 PKG_MIN_PWR_LVL2:16
UINT32 Reserved3:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_LEVEL2

Field Documentation

struct { ... } MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER::Config_TDP_LVL2_Ratio

[Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used for this specific processor.

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER::PKG_MAX_PWR_LVL2

[Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP Level 2.

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER::PKG_MIN_PWR_LVL2

[Bits 62:47] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP Level 2.

UINT32 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER::PKG_TDP_LVL2

[Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.

UINT64 MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Union Reference

Data Fields
MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Config_TDP_Base:8
UINT32 Reserved1:24
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_CONFIG_TDP_NOMINAL

Field Documentation

struct { ... } MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER::Config_TDP_Base

[Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this specific processor (in units of 100 MHz).

UINT32 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:2
UINT32 GraphicsDriverStatus:1
UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1
UINT32 VRThermAlertStatus:1
UINT32 Reserved2:1
UINT32 ElectricalDesignPointStatus:1
UINT32 PLStatus:1
UINT32 PL1Status:1
UINT32 PL2Status:1
UINT32 MaxTurboLimitStatus:1
UINT32 TurboTransitionAttenuationStatus:1
UINT32 Reserved3:2
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 Reserved4:2
UINT32 GraphicsDriverLog:1
UINT32 AutonomousUtilizationBasedFrequencyControlLog:1
UINT32 VRThermAlertLog:1
UINT32 Reserved5:1
UINT32 ElectricalDesignPointLog:1
UINT32 PLLog:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 MaxTurboLimitLog:1
UINT32 TurboTransitionAttenuationLog:1
UINT32 Reserved6:2
UINT32 Reserved7:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_CORE_PERF_LIMIT_REASONS

Field Documentation

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlLog

[Bit 21] Autonomous Utilization-Based Frequency Control Log When set, indicates that the Autonomous Utilization-Based Frequency Control Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlStatus

[Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low.

struct { ... } MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog

[Bit 24] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::GraphicsDriverLog

[Bit 20] Graphics Driver Log When set, indicates that the Graphics Driver Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::GraphicsDriverStatus

[Bit 4] Graphics Driver Status (R0) When set, frequency is reduced below the operating system request due to Processor Graphics driver override.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitLog

[Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitStatus

[Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 26] Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Status

[Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PLLog

[Bit 25] Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PLStatus

[Bit 9] Core Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationLog

[Bit 29] Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationStatus

[Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 PowerBudgetManagementStatus:1
UINT32 PlatformConfigurationServicesStatus:1
UINT32 Reserved1:1
UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1
UINT32 VRThermAlertStatus:1
UINT32 Reserved2:1
UINT32 ElectricalDesignPointStatus:1
UINT32 Reserved3:1
UINT32 MultiCoreTurboStatus:1
UINT32 Reserved4:2
UINT32 FrequencyP1Status:1
UINT32 TurboFrequencyLimitingStatus:1
UINT32 FrequencyLimitingStatus:1
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 PowerBudgetManagementLog:1
UINT32 PlatformConfigurationServicesLog:1
UINT32 Reserved5:1
UINT32 AutonomousUtilizationBasedFrequencyControlLog:1
UINT32 VRThermAlertLog:1
UINT32 Reserved6:1
UINT32 ElectricalDesignPointLog:1
UINT32 Reserved7:1
UINT32 MultiCoreTurboLog:1
UINT32 Reserved8:2
UINT32 CoreFrequencyP1Log:1
UINT32 TurboFrequencyLimitingLog:1
UINT32 CoreFrequencyLimitingLog:1
UINT32 Reserved9:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS

Field Documentation

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlLog

[Bit 21] Autonomous Utilization-Based Frequency Control Log When set, indicates that the AUBFC Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlStatus

[Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low.

struct { ... } MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::CoreFrequencyLimitingLog

[Bit 31] Core Frequency Limiting Log When set, indicates that the Core Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::CoreFrequencyP1Log

[Bit 29] Core Frequency P1 Log When set, indicates that the Core Frequency P1 Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog

[Bit 24] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::FrequencyLimitingStatus

[Bit 15] Core Frequency Limiting Status (R0) When set, frequency is reduced below the operating system request.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::FrequencyP1Status

[Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced below max non-turbo P1.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::MultiCoreTurboLog

[Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core Turbo Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::MultiCoreTurboStatus

[Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced below the operating system request due to Multi-Core Turbo limits.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::PlatformConfigurationServicesLog

[Bit 19] Platform Configuration Services Log When set, indicates that the PCS Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::PlatformConfigurationServicesStatus

[Bit 3] Platform Configuration Services Status (R0) When set, frequency is reduced below the operating system request due to PCS limit.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::PowerBudgetManagementLog

[Bit 18] Power Budget Management Log When set, indicates that the PBM Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::PowerBudgetManagementStatus

[Bit 2] Power Budget Management Status (R0) When set, frequency is reduced below the operating system request due to PBM limit.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::TurboFrequencyLimitingLog

[Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, indicates that the Core Max n-core Turbo Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::TurboFrequencyLimitingStatus

[Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When set, frequency is reduced below max n-core turbo frequency.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Core_Count:16
UINT32 Thread_Count:16
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_CORE_THREAD_COUNT

Field Documentation

struct { ... } MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER::Core_Count

[Bits 15:0] Core_COUNT (RO) The number of processor cores that are currently enabled (by either factory configuration or BIOS configuration) in the physical package.

UINT32 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER::Thread_Count

[Bits 31:16] THREAD_COUNT (RO) The number of logical processors that are currently enabled (by either factory configuration or BIOS configuration) in the physical package.

UINT32 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Energy:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_DRAM_ENERGY_STATUS

Field Documentation

struct { ... } MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER::Energy

[Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM RAPL mode 0 (Direct VR).

UINT32 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_ERROR_CONTROL_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_ERROR_CONTROL_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 MemErrorLogEnable:1
UINT32 Reserved2:30
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_ERROR_CONTROL

Field Documentation

struct { ... } MSR_HASWELL_E_ERROR_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_ERROR_CONTROL_REGISTER::MemErrorLogEnable

[Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank to log additional info in bits 36:32.

UINT32 MSR_HASWELL_E_ERROR_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_ERROR_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_IA32_MCG_CAP_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Count:8
UINT32 MCG_CTL_P:1
UINT32 MCG_EXT_P:1
UINT32 MCP_CMCI_P:1
UINT32 MCG_TES_P:1
UINT32 Reserved1:4
UINT32 MCG_EXT_CNT:8
UINT32 MCG_SER_P:1
UINT32 MCG_EM_P:1
UINT32 MCG_ELOG_P:1
UINT32 Reserved2:5
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_IA32_MCG_CAP

Field Documentation

struct { ... } MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::Count

[Bits 7:0] Count.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_CTL_P

[Bit 8] MCG_CTL_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_ELOG_P

[Bit 26] MCG_ELOG_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_EM_P

[Bit 25] MCG_EM_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_EXT_CNT

[Bits 23:16] MCG_EXT_CNT.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_EXT_P

[Bit 9] MCG_EXT_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_SER_P

[Bit 24] MCG_SER_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCG_TES_P

[Bit 11] MCG_TES_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::MCP_CMCI_P

[Bit 10] MCP_CMCI_P.

UINT32 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_IA32_MCG_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 RMID:10
UINT32 Reserved1:22
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_IA32_PQR_ASSOC

Field Documentation

struct { ... } MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER::RMID

[Bits 9:0] RMID.

UINT32 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 EventID:8
UINT32 Reserved1:24
UINT32 RMID:10
UINT32 Reserved2:22
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_IA32_QM_EVTSEL

Field Documentation

struct { ... } MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER::EventID

[Bits 7:0] EventID (RW) Event encoding: 0x0: no monitoring 0x1: L3 occupancy monitoring all other encoding reserved..

UINT32 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER::RMID

[Bits 41:32] RMID (RW).

UINT64 MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 MAX_RATIO:7
UINT32 Reserved1:1
UINT32 MIN_RATIO:7
UINT32 Reserved2:17
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT

Field Documentation

struct { ... } MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER::MAX_RATIO

[Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the LLC/Ring.

UINT32 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER::MIN_RATIO

[Bits 14:8] MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring.

UINT32 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 PCIERatio:2
UINT32 LPLLSelect:1
UINT32 LONGRESET:1
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_PCIE_PLL_RATIO

Field Documentation

struct { ... } MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::LONGRESET

[Bit 3] Package. LONG RESET (R/W) if 1, wait additional time-out before re-locking Gen2/Gen3 PLLs.

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::LPLLSelect

[Bit 2] Package. LPLL Select (R/W) if 1, use configured setting of PCIE Ratio.

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::PCIERatio

[Bits 1:0] Package. PCIE Ratio (R/W) 00b: Use 5:5 mapping for100MHz operation (default) 01b: Use 5:4 mapping for125MHz operation 10b: Use 5:3 mapping for166MHz operation 11b: Use 5:2 mapping for250MHz operation.

UINT32 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:9
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 CStateDemotion:1
UINT32 CStateUndemotion:1
UINT32 Reserved4:1
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 State Auto Demotion Enable (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 Undemotion (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 State Auto Demotion Enable (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 Undemotion (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::CStateDemotion

[Bit 29] Package C State Demotion Enable (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::CStateUndemotion

[Bit 30] Package C State UnDemotion Enable (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W).

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 011b: C6 (retention) 111b: No Package C state limits. All C states supported by the processor are available.

UINT32 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnits:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Package. Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules).

UINT32 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER::TimeUnits

[Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_SMM_MCA_CAP_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:26
UINT32 SMM_Code_Access_Chk:1
UINT32 Long_Flow_Indication:1
UINT32 Reserved3:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_SMM_MCA_CAP

Field Documentation

struct { ... } MSR_HASWELL_E_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler.

UINT32 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and a host-space interface available to SMM handler.

UINT64 MSR_HASWELL_E_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_THREAD_ID_INFO_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Logical_Processor_ID:8
UINT32 Reserved1:24
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_THREAD_ID_INFO

Field Documentation

struct { ... } MSR_HASWELL_E_THREAD_ID_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER::Logical_Processor_ID

[Bits 7:0] Logical_Processor_ID (RO) An implementation-specific numerical. value physically assigned to each logical processor. This ID is not related to Initial APIC ID or x2APIC ID, it is unique within a physical package.

UINT32 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_E_THREAD_ID_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Maximum9C:8
UINT32 Maximum10C:8
UINT32 Maximum11C:8
UINT32 Maximum12C:8
UINT32 Maximum13C:8
UINT32 Maximum14C:8
UINT32 Maximum15C:8
UINT32 Maximum16C:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT1

Field Documentation

struct { ... } MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum10C

[Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio limit of 10 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum11C

[Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio limit of 11 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum12C

[Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio limit of 12 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum13C

[Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio limit of 13 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum14C

[Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio limit of 14 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum15C

[Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio limit of 15 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum16C

[Bits 63:56] Package. Maximum Ratio Limit for16C Maximum turbo ratio limit of 16 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Maximum9C

[Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio limit of 9 core active.

UINT64 MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Maximum17C:8
UINT32 Maximum18C:8
UINT32 Reserved1:16
UINT32 Reserved2:31
UINT32 TurboRatioLimitConfigurationSemaphore:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT2

Field Documentation

struct { ... } MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER::Maximum17C

[Bits 7:0] Package. Maximum Ratio Limit for 17C Maximum turbo ratio limit of 17 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER::Maximum18C

[Bits 15:8] Package. Maximum Ratio Limit for 18C Maximum turbo ratio limit of 18 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER::TurboRatioLimitConfigurationSemaphore

[Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration specified in MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1 and MSR_TURBO_RATIO_LIMIT2. If 0, the processor uses factory-set configuration (Default).

UINT64 MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <HaswellEMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Maximum5C:8
UINT32 Maximum6C:8
UINT32 Maximum7C:8
UINT32 Maximum8C:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_E_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum7C

[Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio limit of 7 core active.

UINT32 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Maximum8C

[Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio limit of 8 core active.

UINT64 MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:2
UINT32 GraphicsDriverStatus:1
UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1
UINT32 VRThermAlertStatus:1
UINT32 Reserved2:1
UINT32 ElectricalDesignPointStatus:1
UINT32 GraphicsPowerLimitingStatus:1
UINT32 PL1STatus:1
UINT32 PL2Status:1
UINT32 Reserved3:4
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 Reserved4:2
UINT32 GraphicsDriverLog:1
UINT32 AutonomousUtilizationBasedFrequencyControlLog:1
UINT32 VRThermAlertLog:1
UINT32 Reserved5:1
UINT32 ElectricalDesignPointLog:1
UINT32 CorePowerLimitingLog:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 MaxTurboLimitLog:1
UINT32 TurboTransitionAttenuationLog:1
UINT32 Reserved6:2
UINT32 Reserved7:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS

Field Documentation

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlLog

[Bit 21] Autonomous Utilization-Based Frequency Control Log When set, indicates that the Autonomous Utilization-Based Frequency Control Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlStatus

[Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low.

struct { ... } MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::CorePowerLimitingLog

[Bit 25] Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog

[Bit 24] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::GraphicsDriverLog

[Bit 20] Graphics Driver Log When set, indicates that the Graphics Driver Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::GraphicsDriverStatus

[Bit 4] Graphics Driver Status (R0) When set, frequency is reduced below the operating system request due to Processor Graphics driver override.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::GraphicsPowerLimitingStatus

[Bit 9] Graphics Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to domain-level power limiting.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitLog

[Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 26] Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL1STatus

[Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationLog

[Bit 29] Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Union Reference

Data Fields
MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 EventSelect:8
UINT32 UMASK:8
UINT32 USR:1
UINT32 OS:1
UINT32 E:1
UINT32 PC:1
UINT32 INT:1
UINT32 ANY:1
UINT32 EN:1
UINT32 INV:1
UINT32 CMASK:8
UINT32 Reserved:32
UINT32 IN_TX:1
UINT32 IN_TXCP:1
UINT32 Reserved2:30
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_IA32_PERFEVTSEL2

Field Documentation

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::ANY

[Bit 21] AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR.

struct { ... } MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::CMASK

[Bits 31:24] CMASK: When CMASK is not zero, the corresponding performance counter increments each cycle if the event count is greater than or equal to the CMASK.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::E

[Bit 18] Edge: Enables edge detection if set.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::EN

[Bit 22] EN: enables the corresponding performance counter to commence counting when this bit is set.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::EventSelect

[Bits 7:0] Event Select: Selects a performance event logic unit.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::IN_TX

[Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to prevent incorrect results.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::IN_TXCP

[Bit 33] IN_TXCP: see Section 18.3.6.5.1 When IN_TXCP=1 & IN_TX=1 and in sampling, spurious PMI may occur and transactions may continuously abort near overflow conditions. Software should favor using IN_TXCP for counting over sampling. If sampling, software should use large "sample-after" value after clearing the counter configured to use IN_TXCP and also always reset the counter even when no overflow condition was reported.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::INT

[Bit 20] INT: enables interrupt on counter overflow.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::INV

[Bit 23] INV: invert the CMASK.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::OS

[Bit 17] OS: Counts while in privilege level is ring 0.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::PC

[Bit 19] PC: enables pin control.

UINT64 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::UMASK

[Bits 15:8] UMask: Qualifies the microarchitectural condition to detect on the selected event logic.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER::USR

[Bit 16] USR: Counts while in privilege level is not ring 0.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Union Reference

Data Fields
MSR_HASWELL_IA32_PERFEVTSEL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 EventSelect:8
UINT32 UMASK:8
UINT32 USR:1
UINT32 OS:1
UINT32 E:1
UINT32 PC:1
UINT32 INT:1
UINT32 ANY:1
UINT32 EN:1
UINT32 INV:1
UINT32 CMASK:8
UINT32 Reserved:32
UINT32 IN_TX:1
UINT32 Reserved2:31
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_HASWELL_IA32_PERFEVTSEL0, #MSR_HASWELL_IA32_PERFEVTSEL1, and #MSR_HASWELL_IA32_PERFEVTSEL3.

Field Documentation

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::ANY

[Bit 21] AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR.

struct { ... } MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::CMASK

[Bits 31:24] CMASK: When CMASK is not zero, the corresponding performance counter increments each cycle if the event count is greater than or equal to the CMASK.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::E

[Bit 18] Edge: Enables edge detection if set.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::EN

[Bit 22] EN: enables the corresponding performance counter to commence counting when this bit is set.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::EventSelect

[Bits 7:0] Event Select: Selects a performance event logic unit.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::IN_TX

[Bit 32] IN_TX: see Section 18.3.6.5.1 When IN_TX (bit 32) is set, AnyThread (bit 21) should be cleared to prevent incorrect results.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::INT

[Bit 20] INT: enables interrupt on counter overflow.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::INV

[Bit 23] INV: invert the CMASK.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::OS

[Bit 17] OS: Counts while in privilege level is ring 0.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::PC

[Bit 19] PC: enables pin control.

UINT64 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::UMASK

[Bits 15:8] UMask: Qualifies the microarchitectural condition to detect on the selected event logic.

UINT32 MSR_HASWELL_IA32_PERFEVTSEL_REGISTER::USR

[Bit 16] USR: Counts while in privilege level is not ring 0.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_LBR_SELECT_REGISTER Union Reference

Data Fields
MSR_HASWELL_LBR_SELECT_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 CPL_EQ_0:1
UINT32 CPL_NEQ_0:1
UINT32 JCC:1
UINT32 NEAR_REL_CALL:1
UINT32 NEAR_IND_CALL:1
UINT32 NEAR_RET:1
UINT32 NEAR_IND_JMP:1
UINT32 NEAR_REL_JMP:1
UINT32 FAR_BRANCH:1
UINT32 EN_CALL_STACK:1
UINT32 Reserved1:22
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_LBR_SELECT

Field Documentation

struct { ... } MSR_HASWELL_LBR_SELECT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::CPL_EQ_0

[Bit 0] CPL_EQ_0.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::CPL_NEQ_0

[Bit 1] CPL_NEQ_0.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::EN_CALL_STACK

[Bit 9] EN_CALL_STACK.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::FAR_BRANCH

[Bit 8] FAR_BRANCH.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::JCC

[Bit 2] JCC.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::NEAR_IND_CALL

[Bit 4] NEAR_IND_CALL.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::NEAR_IND_JMP

[Bit 6] NEAR_IND_JMP.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::NEAR_REL_CALL

[Bit 3] NEAR_REL_CALL.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::NEAR_REL_JMP

[Bit 7] NEAR_REL_JMP.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::NEAR_RET

[Bit 5] NEAR_RET.

UINT32 MSR_HASWELL_LBR_SELECT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_LBR_SELECT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Union Reference

Data Fields
MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 C10ResidencyCounter:32
UINT32 C10ResidencyCounterHi:28
UINT32 Reserved:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PKG_C10_RESIDENCY

Field Documentation

struct { ... } MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER::C10ResidencyCounter

[Bits 31:0] Package C10 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C10 states. Count at the same frequency as the TSC.

UINT32 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER::C10ResidencyCounterHi

[Bits 59:32] Package C10 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C10 states. Count at the same frequency as the TSC.

UINT64 MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Union Reference

Data Fields
MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 C8ResidencyCounter:32
UINT32 C8ResidencyCounterHi:28
UINT32 Reserved:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PKG_C8_RESIDENCY

Field Documentation

struct { ... } MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER::C8ResidencyCounter

[Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C8 states. Count at the same frequency as the TSC.

UINT32 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER::C8ResidencyCounterHi

[Bits 59:32] Package C8 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C8 states. Count at the same frequency as the TSC.

UINT64 MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Union Reference

Data Fields
MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 C9ResidencyCounter:32
UINT32 C9ResidencyCounterHi:28
UINT32 Reserved:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PKG_C9_RESIDENCY

Field Documentation

struct { ... } MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER::C9ResidencyCounter

[Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C9 states. Count at the same frequency as the TSC.

UINT32 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER::C9ResidencyCounterHi

[Bits 59:32] Package C9 Residency Counter. (R/O) Value since last reset that this package is in processor-specific C9 states. Count at the same frequency as the TSC.

UINT64 MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Limit:4
UINT32 Reserved1:6
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:9
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 Reserved4:3
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 State Auto Demotion Enable (R/W).

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 Undemotion (R/W).

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 State Auto Demotion Enable (R/W).

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 Undemotion (R/W).

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO).

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W).

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 3:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 0000b: C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6 0100b: C7 0101b: C7s Package C states C7 are not available to processor with signature 06_3CH.

UINT32 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PKGC_IRTL1_REGISTER Union Reference

Data Fields
MSR_HASWELL_PKGC_IRTL1_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 InterruptResponseTimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL1

Field Documentation

struct { ... } MSR_HASWELL_PKGC_IRTL1_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PKGC_IRTL1_REGISTER::InterruptResponseTimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 or C7 state.

UINT32 MSR_HASWELL_PKGC_IRTL1_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-19 for supported time unit encodings.

UINT32 MSR_HASWELL_PKGC_IRTL1_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_PKGC_IRTL1_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_PKGC_IRTL1_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PKGC_IRTL2_REGISTER Union Reference

Data Fields
MSR_HASWELL_PKGC_IRTL2_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 InterruptResponseTimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PKGC_IRTL2

Field Documentation

struct { ... } MSR_HASWELL_PKGC_IRTL2_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PKGC_IRTL2_REGISTER::InterruptResponseTimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 or C7 state.

UINT32 MSR_HASWELL_PKGC_IRTL2_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. See Table 2-19 for supported time unit encodings.

UINT32 MSR_HASWELL_PKGC_IRTL2_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_PKGC_IRTL2_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_PKGC_IRTL2_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_HASWELL_PLATFORM_INFO_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:12
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 Reserved3:2
UINT32 LowPowerModeSupport:1
UINT32 ConfigTDPLevels:2
UINT32 Reserved4:5
UINT32 MaximumEfficiencyRatio:8
UINT32 MinimumOperatingRatio:8
UINT32 Reserved5:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_PLATFORM_INFO

Field Documentation

struct { ... } MSR_HASWELL_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::ConfigTDPLevels

[Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base TDP level available. 01: One additional TDP level available. 02: Two additional TDP level available. 11: Reserved.

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::LowPowerModeSupport

[Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, indicates that LPM is supported, and when set to 0, indicates LPM is not supported.

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::MinimumOperatingRatio

[Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the minimum supported operating ratio in units of 100 MHz.

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_HASWELL_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT64 MSR_HASWELL_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_HASWELL_RAPL_POWER_UNIT_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnits:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_HASWELL_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Package. Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules).

UINT32 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER::TimeUnits

[Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:4
UINT32 VRThermAlertStatus:1
UINT32 Reserved2:1
UINT32 ElectricalDesignPointStatus:1
UINT32 Reserved3:1
UINT32 PL1STatus:1
UINT32 PL2Status:1
UINT32 Reserved4:4
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 Reserved5:2
UINT32 GraphicsDriverLog:1
UINT32 AutonomousUtilizationBasedFrequencyControlLog:1
UINT32 VRThermAlertLog:1
UINT32 Reserved6:1
UINT32 ElectricalDesignPointLog:1
UINT32 CorePowerLimitingLog:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 MaxTurboLimitLog:1
UINT32 TurboTransitionAttenuationLog:1
UINT32 Reserved7:2
UINT32 Reserved8:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_RING_PERF_LIMIT_REASONS

Field Documentation

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlLog

[Bit 21] Autonomous Utilization-Based Frequency Control Log When set, indicates that the Autonomous Utilization-Based Frequency Control Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

struct { ... } MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::CorePowerLimitingLog

[Bit 25] Core Power Limiting Log When set, indicates that the Core Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog

[Bit 24] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::GraphicsDriverLog

[Bit 20] Graphics Driver Log When set, indicates that the Graphics Driver Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitLog

[Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 26] Package-Level PL1 Power Limiting Log When set, indicates that the Package Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::PL1STatus

[Bit 10] Package-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL1.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 27] Package-Level PL2 Power Limiting Log When set, indicates that the Package Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 11] Package-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package-level power limiting PL2.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationLog

[Bit 29] Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Lock:1
UINT32 Reserved1:1
UINT32 SMM_Code_Chk_En:1
UINT32 Reserved2:29
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_SMM_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER::Lock

[Bit 0] Lock (SMM-RWO) When set to '1' locks this register from further changes.

UINT32 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER::SMM_Code_Chk_En

[Bit 2] SMM_Code_Chk_En (SMM-RW) This control bit is available only if MSR_SMM_MCA_CAP[58] == 1. When set to '0' (default) none of the logical processors are prevented from executing SMM code outside the ranges defined by the SMRR. When set to '1' any logical processor in the package that attempts to execute SMM code not within the ranges defined by the SMRR will assert an unrecoverable MCE.

UINT32 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_SMM_MCA_CAP_REGISTER Union Reference

Data Fields
MSR_HASWELL_SMM_MCA_CAP_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:26
UINT32 SMM_Code_Access_Chk:1
UINT32 Long_Flow_Indication:1
UINT32 Reserved3:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_SMM_MCA_CAP

Field Documentation

struct { ... } MSR_HASWELL_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and the MSR_SMM_DELAYED is supported.

UINT32 MSR_HASWELL_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and the MSR_SMM_FEATURE_CONTROL is supported.

UINT64 MSR_HASWELL_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Union Reference

Data Fields
MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 MAX_NON_TURBO_RATIO:8
UINT32 Reserved1:23
UINT32 TURBO_ACTIVATION_RATIO_Lock:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_TURBO_ACTIVATION_RATIO

Field Documentation

struct { ... } MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER::MAX_NON_TURBO_RATIO

[Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this field.

UINT32 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER::TURBO_ACTIVATION_RATIO_Lock

[Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the content of this register is locked until a reset.

UINT32 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Union Reference

Data Fields
MSR_HASWELL_UNC_CBO_CONFIG_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 CBox:4
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_UNC_CBO_CONFIG

Field Documentation

struct { ... } MSR_HASWELL_UNC_CBO_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER::CBox

[Bits 3:0] Encoded number of C-Box, derive value by "-1".

UINT32 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_UNC_CBO_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Union Reference

Data Fields
MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 CurrentCount:32
UINT32 CurrentCountHi:16
UINT32 Reserved:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTR

Field Documentation

struct { ... } MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER::CurrentCount

[Bits 31:0] Current count.

UINT32 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER::CurrentCountHi

[Bits 47:32] Current count.

UINT64 MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Union Reference

Data Fields
MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Reserved1:20
UINT32 EnableOverflow:1
UINT32 Reserved2:1
UINT32 EnableCounting:1
UINT32 Reserved3:9
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_FIXED_CTRL

Field Documentation

struct { ... } MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER::EnableCounting

[Bit 22] Enable counting.

UINT32 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER::EnableOverflow

[Bit 20] Enable overflow propagation.

UINT32 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Union Reference

Data Fields
MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 PMI_Sel_Core0:1
UINT32 PMI_Sel_Core1:1
UINT32 PMI_Sel_Core2:1
UINT32 PMI_Sel_Core3:1
UINT32 Reserved1:15
UINT32 Reserved2:10
UINT32 EN:1
UINT32 WakePMI:1
UINT32 FREEZE:1
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_CTRL

Field Documentation

struct { ... } MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::EN

[Bit 29] Enable all uncore counters.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::FREEZE

[Bit 31] Enable Freezing counter when overflow.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Core0

[Bit 0] Core 0 select.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Core1

[Bit 1] Core 1 select.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Core2

[Bit 2] Core 2 select.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Core3

[Bit 3] Core 3 select.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER::WakePMI

[Bit 30] Enable wake on PMI.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <HaswellMsr.h>

Data Fields

struct {
UINT32 Fixed:1
UINT32 ARB:1
UINT32 Reserved1:1
UINT32 CBox:1
UINT32 Reserved2:28
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_HASWELL_UNC_PERF_GLOBAL_STATUS

Field Documentation

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER::ARB

[Bit 1] An ARB counter overflowed.

struct { ... } MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER::CBox

[Bit 3] A CBox counter overflowed (on any slice).

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER::Fixed

[Bit 0] Fixed counter overflowed.

UINT32 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_APIC_BASE_REGISTER Union Reference

Data Fields
MSR_IA32_APIC_BASE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 BSP:1
UINT32 Reserved2:1
UINT32 EXTD:1
UINT32 EN:1
UINT32 ApicBase:20
UINT32 ApicBaseHi:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_APIC_BASE

Field Documentation

UINT32 MSR_IA32_APIC_BASE_REGISTER::ApicBase

[Bits 31:12] APIC Base (R/W).

UINT32 MSR_IA32_APIC_BASE_REGISTER::ApicBaseHi

[Bits 63:32] APIC Base (R/W).

struct { ... } MSR_IA32_APIC_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_APIC_BASE_REGISTER::BSP

[Bit 8] BSP flag (R/W).

UINT32 MSR_IA32_APIC_BASE_REGISTER::EN

[Bit 11] APIC Global Enable (R/W).

UINT32 MSR_IA32_APIC_BASE_REGISTER::EXTD

[Bit 10] Enable x2APIC mode. Introduced at Display Family / Display Model 06_1AH.

UINT64 MSR_IA32_APIC_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_BIOS_SIGN_ID_REGISTER Union Reference

Data Fields
MSR_IA32_BIOS_SIGN_ID_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved:32
UINT32 MicrocodeUpdateSignature:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_BIOS_SIGN_ID

Field Documentation

struct { ... } MSR_IA32_BIOS_SIGN_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_BIOS_SIGN_ID_REGISTER::MicrocodeUpdateSignature

[Bits 63:32] Microcode update signature. This field contains the signature of the currently loaded microcode update when read following the execution of the CPUID instruction, function 1. It is required that this register field be pre-loaded with zero prior to executing the CPUID, function 1. If the field remains equal to zero, then there is no microcode update loaded. Another nonzero value will be the signature.

UINT64 MSR_IA32_BIOS_SIGN_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_BNDCFGS_REGISTER Union Reference

Data Fields
MSR_IA32_BNDCFGS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 EN:1
UINT32 BNDPRESERVE:1
UINT32 Reserved:10
UINT32 Base:20
UINT32 BaseHi:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_BNDCFGS

Field Documentation

UINT32 MSR_IA32_BNDCFGS_REGISTER::Base

[Bits 31:12] Base Address of Bound Directory.

UINT32 MSR_IA32_BNDCFGS_REGISTER::BaseHi

[Bits 63:32] Base Address of Bound Directory.

struct { ... } MSR_IA32_BNDCFGS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_BNDCFGS_REGISTER::BNDPRESERVE

[Bit 1] BNDPRESERVE: Preserve the bounds registers for near branch instructions in the absence of the BND prefix.

UINT32 MSR_IA32_BNDCFGS_REGISTER::EN

[Bit 0] EN: Enable Intel MPX in supervisor mode.

UINT64 MSR_IA32_BNDCFGS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_CLOCK_MODULATION_REGISTER Union Reference

Data Fields
MSR_IA32_CLOCK_MODULATION_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 ExtendedOnDemandClockModulationDutyCycle:1
UINT32 OnDemandClockModulationDutyCycle:3
UINT32 OnDemandClockModulationEnable:1
UINT32 Reserved1:27
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_CLOCK_MODULATION

Field Documentation

struct { ... } MSR_IA32_CLOCK_MODULATION_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_CLOCK_MODULATION_REGISTER::ExtendedOnDemandClockModulationDutyCycle

[Bit 0] Extended On-Demand Clock Modulation Duty Cycle:. If CPUID.06H:EAX[5] = 1.

UINT32 MSR_IA32_CLOCK_MODULATION_REGISTER::OnDemandClockModulationDutyCycle

[Bits 3:1] On-Demand Clock Modulation Duty Cycle: Specific encoded values for target duty cycle modulation. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_CLOCK_MODULATION_REGISTER::OnDemandClockModulationEnable

[Bit 4] On-Demand Clock Modulation Enable: Set 1 to enable modulation. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_CLOCK_MODULATION_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_CLOCK_MODULATION_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_DCA_0_CAP_REGISTER Union Reference

Data Fields
MSR_IA32_DCA_0_CAP_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 DCA_ACTIVE:1
UINT32 TRANSACTION:2
UINT32 DCA_TYPE:4
UINT32 DCA_QUEUE_SIZE:4
UINT32 Reserved1:2
UINT32 DCA_DELAY:4
UINT32 Reserved2:7
UINT32 SW_BLOCK:1
UINT32 Reserved3:1
UINT32 HW_BLOCK:1
UINT32 Reserved4:5
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_DCA_0_CAP

Field Documentation

struct { ... } MSR_IA32_DCA_0_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::DCA_ACTIVE

[Bit 0] DCA_ACTIVE: Set by HW when DCA is fuseenabled and no defeatures are set.

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::DCA_DELAY

[Bits 16:13] DCA_DELAY: Writes will update the register but have no HW side-effect.

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::DCA_QUEUE_SIZE

[Bits 10:7] DCA_QUEUE_SIZE.

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::DCA_TYPE

[Bits 6:3] DCA_TYPE.

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::HW_BLOCK

[Bit 26] HW_BLOCK: Set when DCA is blocked by HW (e.g. CR0.CD = 1).

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::SW_BLOCK

[Bit 24] SW_BLOCK: SW can request DCA block by setting this bit.

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::TRANSACTION

[Bits 2:1] TRANSACTION.

UINT32 MSR_IA32_DCA_0_CAP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_DCA_0_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_DEBUG_INTERFACE_REGISTER Union Reference

Data Fields
MSR_IA32_DEBUG_INTERFACE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:29
UINT32 Lock:1
UINT32 DebugOccurred:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_DEBUG_INTERFACE

Field Documentation

struct { ... } MSR_IA32_DEBUG_INTERFACE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_DEBUG_INTERFACE_REGISTER::DebugOccurred

[Bit 31] Debug Occurred (R/O): This "sticky bit" is set by hardware to indicate the status of bit 0. Default is 0. If CPUID.01H:ECX.[11] = 1.

UINT32 MSR_IA32_DEBUG_INTERFACE_REGISTER::Enable

[Bit 0] Enable (R/W) BIOS set 1 to enable Silicon debug features. Default is 0. If CPUID.01H:ECX.[11] = 1.

UINT32 MSR_IA32_DEBUG_INTERFACE_REGISTER::Lock

[Bit 30] Lock (R/W): If 1, locks any further change to the MSR. The lock bit is set automatically on the first SMI assertion even if not explicitly set by BIOS. Default is 0. If CPUID.01H:ECX.[11] = 1.

UINT32 MSR_IA32_DEBUG_INTERFACE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_DEBUG_INTERFACE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_DEBUGCTL_REGISTER Union Reference

Data Fields
MSR_IA32_DEBUGCTL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 LBR:1
UINT32 BTF:1
UINT32 Reserved1:4
UINT32 TR:1
UINT32 BTS:1
UINT32 BTINT:1
UINT32 BTS_OFF_OS:1
UINT32 BTS_OFF_USR:1
UINT32 FREEZE_LBRS_ON_PMI:1
UINT32 FREEZE_PERFMON_ON_PMI:1
UINT32 ENABLE_UNCORE_PMI:1
UINT32 FREEZE_WHILE_SMM:1
UINT32 RTM_DEBUG:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_DEBUGCTL

Field Documentation

struct { ... } MSR_IA32_DEBUGCTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_DEBUGCTL_REGISTER::BTF

[Bit 1] BTF: Setting this bit to 1 enables the processor to treat EFLAGS.TF as single-step on branches instead of single-step on instructions. Introduced at Display Family / Display Model 06_01H.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::BTINT

[Bit 8] BTINT: When clear, BTMs are logged in a BTS buffer in circular fashion. When this bit is set, an interrupt is generated by the BTS facility when the BTS buffer is full. Introduced at Display Family / Display Model 06_0EH.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::BTS

[Bit 7] BTS: Setting this bit enables branch trace messages (BTMs) to be logged in a BTS buffer. Introduced at Display Family / Display Model 06_0EH.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::BTS_OFF_OS

[Bit 9] BTS_OFF_OS: When set, BTS or BTM is skipped if CPL = 0. Introduced at Display Family / Display Model 06_0FH.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::BTS_OFF_USR

[Bit 10] BTS_OFF_USR: When set, BTS or BTM is skipped if CPL > 0. Introduced at Display Family / Display Model 06_0FH.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::ENABLE_UNCORE_PMI

[Bit 13] ENABLE_UNCORE_PMI: When set, enables the logical processor to receive and generate PMI on behalf of the uncore. Introduced at Display Family / Display Model 06_1AH.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::FREEZE_LBRS_ON_PMI

[Bit 11] FREEZE_LBRS_ON_PMI: When set, the LBR stack is frozen on a PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::FREEZE_PERFMON_ON_PMI

[Bit 12] FREEZE_PERFMON_ON_PMI: When set, each ENABLE bit of the global counter control MSR are frozen (address 38FH) on a PMI request. If CPUID.01H: ECX[15] = 1 && CPUID.0AH: EAX[7:0] > 1.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::FREEZE_WHILE_SMM

[Bit 14] FREEZE_WHILE_SMM: When set, freezes perfmon and trace messages while in SMM. If IA32_PERF_CAPABILITIES[ 12] = 1.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::LBR

[Bit 0] LBR: Setting this bit to 1 enables the processor to record a running trace of the most recent branches taken by the processor in the LBR stack. Introduced at Display Family / Display Model 06_01H.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::RTM_DEBUG

[Bit 15] RTM_DEBUG: When set, enables DR7 debug bit on XBEGIN. If (CPUID.(EAX=07H, ECX=0):EBX[11] = 1).

UINT32 MSR_IA32_DEBUGCTL_REGISTER::TR

[Bit 6] TR: Setting this bit to 1 enables branch trace messages to be sent. Introduced at Display Family / Display Model 06_0EH.

UINT32 MSR_IA32_DEBUGCTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_DEBUGCTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_EFER_REGISTER Union Reference

Data Fields
MSR_IA32_EFER_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 SCE:1
UINT32 Reserved1:7
UINT32 LME:1
UINT32 Reserved2:1
UINT32 LMA:1
UINT32 NXE:1
UINT32 Reserved3:20
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_EFER

Field Documentation

struct { ... } MSR_IA32_EFER_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_EFER_REGISTER::LMA

[Bit 10] IA-32e Mode Active: IA32_EFER.LMA (R) Indicates IA-32e mode is active when set.

UINT32 MSR_IA32_EFER_REGISTER::LME

[Bit 8] IA-32e Mode Enable: IA32_EFER.LME (R/W) Enables IA-32e mode operation.

UINT32 MSR_IA32_EFER_REGISTER::NXE

[Bit 11] Execute Disable Bit Enable: IA32_EFER.NXE (R/W).

UINT32 MSR_IA32_EFER_REGISTER::SCE

[Bit 0] SYSCALL Enable: IA32_EFER.SCE (R/W) Enables SYSCALL/SYSRET instructions in 64-bit mode.

UINT32 MSR_IA32_EFER_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_EFER_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_ENERGY_PERF_BIAS_REGISTER Union Reference

Data Fields
MSR_IA32_ENERGY_PERF_BIAS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 PowerPolicyPreference:4
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_ENERGY_PERF_BIAS

Field Documentation

struct { ... } MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_ENERGY_PERF_BIAS_REGISTER::PowerPolicyPreference

[Bits 3:0] Power Policy Preference: 0 indicates preference to highest performance. 15 indicates preference to maximize energy saving.

UINT32 MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_ENERGY_PERF_BIAS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_IA32_FEATURE_CONTROL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Lock:1
UINT32 EnableVmxInsideSmx:1
UINT32 EnableVmxOutsideSmx:1
UINT32 Reserved1:5
UINT32 SenterLocalFunctionEnables:7
UINT32 SenterGlobalEnable:1
UINT32 Reserved2:1
UINT32 SgxLaunchControlEnable:1
UINT32 SgxEnable:1
UINT32 Reserved3:1
UINT32 LmceOn:1
UINT32 Reserved4:11
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_IA32_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::EnableVmxInsideSmx

[Bit 1] Enable VMX inside SMX operation (R/WL): This bit enables a system executive to use VMX in conjunction with SMX to support Intel(R) Trusted Execution Technology. BIOS must set this bit only when the CPUID function 1 returns VMX feature flag and SMX feature flag set (ECX bits 5 and 6 respectively). If CPUID.01H:ECX[5] = 1 && CPUID.01H:ECX[6] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::EnableVmxOutsideSmx

[Bit 2] Enable VMX outside SMX operation (R/WL): This bit enables VMX for system executive that do not require SMX. BIOS must set this bit only when the CPUID function 1 returns VMX feature flag set (ECX bit 5). If CPUID.01H:ECX[5] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::LmceOn

[Bit 20] LMCE On (R/WL): When set, system software can program the MSRs associated with LMCE to configure delivery of some machine check exceptions to a single logical processor. If IA32_MCG_CAP[27] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::Lock

[Bit 0] Lock bit (R/WO): (1 = locked). When set, locks this MSR from being written, writes to this bit will result in GP(0). Note: Once the Lock bit is set, the contents of this register cannot be modified. Therefore the lock bit must be set after configuring support for Intel Virtualization Technology and prior to transferring control to an option ROM or the OS. Hence, once the Lock bit is set, the entire IA32_FEATURE_CONTROL contents are preserved across RESET when PWRGOOD is not deasserted. If any one enumeration condition for defined bit field position greater than bit 0 holds.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::SenterGlobalEnable

[Bit 15] SENTER Global Enable (R/WL): This bit must be set to enable SENTER leaf functions. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If CPUID.01H:ECX[6] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::SenterLocalFunctionEnables

[Bits 14:8] SENTER Local Function Enables (R/WL): When set, each bit in the field represents an enable control for a corresponding SENTER function. This bit is supported only if CPUID.1:ECX.[bit 6] is set. If CPUID.01H:ECX[6] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::SgxEnable

[Bit 18] SGX Global Enable (R/WL): This bit must be set to enable SGX leaf functions. If CPUID.(EAX=07H, ECX=0H): EBX[2] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::SgxLaunchControlEnable

[Bit 17] SGX Launch Control Enable (R/WL): This bit must be set to enable runtime reconfiguration of SGX Launch Control via IA32_SGXLEPUBKEYHASHn MSR. If CPUID.(EAX=07H, ECX=0H): ECX[30] = 1.

UINT32 MSR_IA32_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_FIXED_CTR_CTRL_REGISTER Union Reference

Data Fields
MSR_IA32_FIXED_CTR_CTRL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 EN0_OS:1
UINT32 EN0_Usr:1
UINT32 AnyThread0:1
UINT32 EN0_PMI:1
UINT32 EN1_OS:1
UINT32 EN1_Usr:1
UINT32 AnyThread1:1
UINT32 EN1_PMI:1
UINT32 EN2_OS:1
UINT32 EN2_Usr:1
UINT32 AnyThread2:1
UINT32 EN2_PMI:1
UINT32 Reserved1:20
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_FIXED_CTR_CTRL

Field Documentation

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::AnyThread0

[Bit 2] AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::AnyThread1

[Bit 6] AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::AnyThread2

[Bit 10] AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR. If CPUID.0AH: EAX[7:0] > 2.

struct { ... } MSR_IA32_FIXED_CTR_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN0_OS

[Bit 0] EN0_OS: Enable Fixed Counter 0 to count while CPL = 0.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN0_PMI

[Bit 3] EN0_PMI: Enable PMI when fixed counter 0 overflows.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN0_Usr

[Bit 1] EN0_Usr: Enable Fixed Counter 0 to count while CPL > 0.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN1_OS

[Bit 4] EN1_OS: Enable Fixed Counter 1 to count while CPL = 0.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN1_PMI

[Bit 7] EN1_PMI: Enable PMI when fixed counter 1 overflows.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN1_Usr

[Bit 5] EN1_Usr: Enable Fixed Counter 1 to count while CPL > 0.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN2_OS

[Bit 8] EN2_OS: Enable Fixed Counter 2 to count while CPL = 0.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN2_PMI

[Bit 11] EN2_PMI: Enable PMI when fixed counter 2 overflows.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::EN2_Usr

[Bit 9] EN2_Usr: Enable Fixed Counter 2 to count while CPL > 0.

UINT32 MSR_IA32_FIXED_CTR_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_FIXED_CTR_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_HWP_CAPABILITIES_REGISTER Union Reference

Data Fields
MSR_IA32_HWP_CAPABILITIES_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Highest_Performance:8
UINT32 Guaranteed_Performance:8
UINT32 Most_Efficient_Performance:8
UINT32 Lowest_Performance:8
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_HWP_CAPABILITIES

Field Documentation

struct { ... } MSR_IA32_HWP_CAPABILITIES_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_HWP_CAPABILITIES_REGISTER::Guaranteed_Performance

[Bits 15:8] Guaranteed_Performance See Section 14.4.3, "HWP Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_CAPABILITIES_REGISTER::Highest_Performance

[Bits 7:0] Highest_Performance See Section 14.4.3, "HWP Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_CAPABILITIES_REGISTER::Lowest_Performance

[Bits 31:24] Lowest_Performance See Section 14.4.3, "HWP Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_CAPABILITIES_REGISTER::Most_Efficient_Performance

[Bits 23:16] Most_Efficient_Performance See Section 14.4.3, "HWP Performance Range and Dynamic Capabilities". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_CAPABILITIES_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_HWP_CAPABILITIES_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_HWP_INTERRUPT_REGISTER Union Reference

Data Fields
MSR_IA32_HWP_INTERRUPT_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 EN_Guaranteed_Performance_Change:1
UINT32 EN_Excursion_Minimum:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_HWP_INTERRUPT

Field Documentation

struct { ... } MSR_IA32_HWP_INTERRUPT_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_HWP_INTERRUPT_REGISTER::EN_Excursion_Minimum

[Bit 1] EN_Excursion_Minimum. See Section 14.4.6, "HWP Notifications". If CPUID.06H:EAX.[8] = 1.

UINT32 MSR_IA32_HWP_INTERRUPT_REGISTER::EN_Guaranteed_Performance_Change

[Bit 0] EN_Guaranteed_Performance_Change. See Section 14.4.6, "HWP Notifications". If CPUID.06H:EAX.[8] = 1.

UINT32 MSR_IA32_HWP_INTERRUPT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_HWP_INTERRUPT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_HWP_REQUEST_PKG_REGISTER Union Reference

Data Fields
MSR_IA32_HWP_REQUEST_PKG_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Minimum_Performance:8
UINT32 Maximum_Performance:8
UINT32 Desired_Performance:8
UINT32 Energy_Performance_Preference:8
UINT32 Activity_Window:10
UINT32 Reserved:22
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_HWP_REQUEST_PKG

Field Documentation

UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Activity_Window

[Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[9] = 1.

struct { ... } MSR_IA32_HWP_REQUEST_PKG_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Desired_Performance

[Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1.

UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Energy_Performance_Preference

[Bits 31:24] Energy_Performance_Preference See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1 && CPUID.06H:EAX.[10] = 1.

UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Maximum_Performance

[Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1.

UINT32 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Minimum_Performance

[Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[11] = 1.

UINT64 MSR_IA32_HWP_REQUEST_PKG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_HWP_REQUEST_REGISTER Union Reference

Data Fields
MSR_IA32_HWP_REQUEST_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Minimum_Performance:8
UINT32 Maximum_Performance:8
UINT32 Desired_Performance:8
UINT32 Energy_Performance_Preference:8
UINT32 Activity_Window:10
UINT32 Package_Control:1
UINT32 Reserved:21
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_HWP_REQUEST

Field Documentation

UINT32 MSR_IA32_HWP_REQUEST_REGISTER::Activity_Window

[Bits 41:32] Activity_Window See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[9] = 1.

struct { ... } MSR_IA32_HWP_REQUEST_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_HWP_REQUEST_REGISTER::Desired_Performance

[Bits 23:16] Desired_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_REQUEST_REGISTER::Energy_Performance_Preference

[Bits 31:24] Energy_Performance_Preference See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[10] = 1.

UINT32 MSR_IA32_HWP_REQUEST_REGISTER::Maximum_Performance

[Bits 15:8] Maximum_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_REQUEST_REGISTER::Minimum_Performance

[Bits 7:0] Minimum_Performance See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_REQUEST_REGISTER::Package_Control

[Bit 42] Package_Control See Section 14.4.4, "Managing HWP". If CPUID.06H:EAX.[7] = 1 && CPUID.06H:EAX.[11] = 1.

UINT64 MSR_IA32_HWP_REQUEST_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_HWP_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_HWP_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Guaranteed_Performance_Change:1
UINT32 Reserved1:1
UINT32 Excursion_To_Minimum:1
UINT32 Reserved2:29
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_HWP_STATUS

Field Documentation

struct { ... } MSR_IA32_HWP_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_HWP_STATUS_REGISTER::Excursion_To_Minimum

[Bit 2] Excursion_To_Minimum (R/WC0). See Section 14.4.5, "HWP Feedback". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_STATUS_REGISTER::Guaranteed_Performance_Change

[Bit 0] Guaranteed_Performance_Change (R/WC0). See Section 14.4.5, "HWP Feedback". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_HWP_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_HWP_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_L2_QOS_CFG_REGISTER Union Reference

Data Fields
MSR_IA32_L2_QOS_CFG_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_L2_QOS_CFG

Field Documentation

struct { ... } MSR_IA32_L2_QOS_CFG_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_L2_QOS_CFG_REGISTER::Enable

[Bit 0] Enable (R/W) Set 1 to enable L2 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode.

UINT32 MSR_IA32_L2_QOS_CFG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_L2_QOS_CFG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_L3_QOS_CFG_REGISTER Union Reference

Data Fields
MSR_IA32_L3_QOS_CFG_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_L3_QOS_CFG

Field Documentation

struct { ... } MSR_IA32_L3_QOS_CFG_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Enable

[Bit 0] Enable (R/W) Set 1 to enable L3 CAT masks and COS to operate in Code and Data Prioritization (CDP) mode.

UINT32 MSR_IA32_L3_QOS_CFG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_L3_QOS_CFG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MC_CTL2_REGISTER Union Reference

Data Fields
MSR_IA32_MC_CTL2_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 CorrectedErrorCountThreshold:15
UINT32 Reserved1:15
UINT32 CMCI_EN:1
UINT32 Reserved2:1
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_IA32_MC0_CTL2 to #MSR_IA32_MC31_CTL2

Field Documentation

struct { ... } MSR_IA32_MC_CTL2_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MC_CTL2_REGISTER::CMCI_EN

[Bit 30] CMCI_EN.

UINT32 MSR_IA32_MC_CTL2_REGISTER::CorrectedErrorCountThreshold

[Bits 14:0] Corrected error count threshold.

UINT32 MSR_IA32_MC_CTL2_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_MC_CTL2_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MCG_CAP_REGISTER Union Reference

Data Fields
MSR_IA32_MCG_CAP_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Count:8
UINT32 MCG_CTL_P:1
UINT32 MCG_EXT_P:1
UINT32 MCP_CMCI_P:1
UINT32 MCG_TES_P:1
UINT32 Reserved1:4
UINT32 MCG_EXT_CNT:8
UINT32 MCG_SER_P:1
UINT32 Reserved2:1
UINT32 MCG_ELOG_P:1
UINT32 MCG_LMCE_P:1
UINT32 Reserved3:4
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_MCG_CAP

Field Documentation

struct { ... } MSR_IA32_MCG_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MCG_CAP_REGISTER::Count

[Bits 7:0] Count: Number of reporting banks.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_CTL_P

[Bit 8] MCG_CTL_P: IA32_MCG_CTL is present if this bit is set.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_ELOG_P

[Bit 26] MCG_ELOG_P: Indicates that the processor allows platform firmware to be invoked when an error is detected so that it may provide additional platform specific information in an ACPI format "Generic Error Data Entry" that augments the data included in machine check bank registers. Introduced at Display Family / Display Model 06_3EH.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_EXT_CNT

[Bits 23:16] MCG_EXT_CNT: Number of extended machine check state registers present.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_EXT_P

[Bit 9] MCG_EXT_P: Extended machine check state registers are present if this bit is set.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_LMCE_P

[Bit 27] MCG_LMCE_P: Indicates that the processor support extended state in IA32_MCG_STATUS and associated MSR necessary to configure Local Machine Check Exception (LMCE). Introduced at Display Family / Display Model 06_3EH.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_SER_P

[Bit 24] MCG_SER_P: The processor supports software error recovery if this bit is set.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCG_TES_P

[Bit 11] MCG_TES_P: Threshold-based error status register are present if this bit is set.

UINT32 MSR_IA32_MCG_CAP_REGISTER::MCP_CMCI_P

[Bit 10] MCP_CMCI_P: Support for corrected MC error event is present. Introduced at Display Family / Display Model 06_01H.

UINT32 MSR_IA32_MCG_CAP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_MCG_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MCG_EXT_CTL_REGISTER Union Reference

Data Fields
MSR_IA32_MCG_EXT_CTL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 LMCE_EN:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_MCG_EXT_CTL

Field Documentation

struct { ... } MSR_IA32_MCG_EXT_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MCG_EXT_CTL_REGISTER::LMCE_EN

[Bit 0] LMCE_EN.

UINT32 MSR_IA32_MCG_EXT_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_MCG_EXT_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MCG_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_MCG_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 RIPV:1
UINT32 EIPV:1
UINT32 MCIP:1
UINT32 LMCE_S:1
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_MCG_STATUS

Field Documentation

struct { ... } MSR_IA32_MCG_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MCG_STATUS_REGISTER::EIPV

[Bit 1] EIPV. Error IP valid. Introduced at Display Family / Display Model 06_01H.

UINT32 MSR_IA32_MCG_STATUS_REGISTER::LMCE_S

[Bit 3] LMCE_S. If IA32_MCG_CAP.LMCE_P[2 7] =1.

UINT32 MSR_IA32_MCG_STATUS_REGISTER::MCIP

[Bit 2] MCIP. Machine check in progress. Introduced at Display Family / Display Model 06_01H.

UINT32 MSR_IA32_MCG_STATUS_REGISTER::RIPV

[Bit 0] RIPV. Restart IP valid. Introduced at Display Family / Display Model 06_01H.

UINT32 MSR_IA32_MCG_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_MCG_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_IA32_MISC_ENABLE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:3
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved4:3
UINT32 EIST:1
UINT32 Reserved5:1
UINT32 MONITOR:1
UINT32 Reserved6:3
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:2
UINT32 XD:1
UINT32 Reserved9:29
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows the processor to automatically reduce power consumption in response to TCC activation. 0 = Disabled. Note: In some products clearing this bit might be ignored in critical thermal conditions, and TM1, TM2 and adaptive thermal throttling will still be activated. The default value of this field varies with product. See respective tables where default value is listed. Introduced at Display Family / Display Model 0F_0H.

struct { ... } MSR_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported. Introduced at Display Family / Display Model 0F_0H.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 0= Enhanced Intel SpeedStep Technology disabled 1 = Enhanced Intel SpeedStep Technology enabled. If CPUID.01H: ECX[7] =1.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable When set, the fast-strings feature (for REP MOVS and REP STORS) is enabled (default); when clear, fast-strings are disabled. Introduced at Display Family / Display Model 0F_0H.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Limit CPUID Maxval (R/W) When this bit is set to 1, CPUID.00H returns a maximum value in EAX[7:0] of 2. BIOS should contain a setup question that allows users to specify when the installed OS does not support CPUID functions greater than 2. Before setting this bit, BIOS must execute the CPUID.0H and examine the maximum value returned in EAX[7:0]. If the maximum value is greater than 2, this bit is supported. Otherwise, this bit is not supported. Setting this bit when the maximum value is not greater than 2 may generate a #GP exception. Setting this bit may cause unexpected behavior in software that depends on the availability of CPUID leaves greater than 2. Introduced at Display Family / Display Model 0F_03H.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] ENABLE MONITOR FSM (R/W) When this bit is set to 0, the MONITOR feature flag is not set (CPUID.01H:ECX[bit 3] = 0). This indicates that MONITOR/MWAIT are not supported. Software attempts to execute MONITOR/MWAIT will cause #UD when this bit is 0. When this bit is set to 1 (default), MONITOR/MWAIT are supported (CPUID.01H:ECX[bit 3] = 1). If the SSE3 feature flag ECX[0] is not set (CPUID.01H:ECX[bit 0] = 0), the OS must not attempt to alter this bit. BIOS must leave it in the default state. Writing this bit when the SSE3 feature flag is set to 0 may generate a #GP exception. Introduced at Display Family / Display Model 0F_03H.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Processor Event Based Sampling (PEBS) Unavailable (RO) 1 = PEBS is not supported; 0 = PEBS is supported. Introduced at Display Family / Display Model 06_0FH.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R) 1 = Performance monitoring enabled 0 = Performance monitoring disabled. Introduced at Display Family / Display Model 0F_0H.

UINT64 MSR_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] XD Bit Disable (R/W) When set to 1, the Execute Disable Bit feature (XD Bit) is disabled and the XD Bit extended feature flag will be clear (CPUID.80000001H: EDX[20]=0). When set to a 0 (default), the Execute Disable Bit feature (if available) allows the OS to enable PAE paging and take advantage of data only pages. BIOS must not alter the contents of this bit location, if XD bit is not supported. Writing this bit to 1 when the XD Bit extended feature flag is set to 0 may generate a #GP exception. if CPUID.80000001H:EDX[2 0] = 1.

UINT32 MSR_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. if CPUID.01H:ECX[14] = 1.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MTRR_DEF_TYPE_REGISTER Union Reference

Data Fields
MSR_IA32_MTRR_DEF_TYPE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Type:3
UINT32 Reserved1:7
UINT32 FE:1
UINT32 E:1
UINT32 Reserved2:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_MTRR_DEF_TYPE

Field Documentation

struct { ... } MSR_IA32_MTRR_DEF_TYPE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MTRR_DEF_TYPE_REGISTER::E

[Bit 11] MTRR Enable.

UINT32 MSR_IA32_MTRR_DEF_TYPE_REGISTER::FE

[Bit 10] Fixed Range MTRR Enable.

UINT32 MSR_IA32_MTRR_DEF_TYPE_REGISTER::Type

[Bits 2:0] Default Memory Type.

UINT32 MSR_IA32_MTRR_DEF_TYPE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_MTRR_DEF_TYPE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MTRR_PHYSBASE_REGISTER Union Reference

Data Fields
MSR_IA32_MTRR_PHYSBASE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Type:8
UINT32 Reserved1:4
UINT32 PhysBase:20
UINT32 PhysBaseHi:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to #MSR_IA32_MTRR_PHYSBASE9

Field Documentation

struct { ... } MSR_IA32_MTRR_PHYSBASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::PhysBase

[Bits 31:12] PhysBase. MTRR physical Base Address.

UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::PhysBaseHi

[Bits MAXPHYSADDR:32] PhysBase. Upper bits of MTRR physical Base Address. MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum physical address range supported by the processor. It is reported by CPUID leaf function 80000008H. If CPUID does not support leaf 80000008H, the processor supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.

UINT32 MSR_IA32_MTRR_PHYSBASE_REGISTER::Type

[Bits 7:0] Type. Specifies memory type of the range.

UINT64 MSR_IA32_MTRR_PHYSBASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MTRR_PHYSMASK_REGISTER Union Reference

Data Fields
MSR_IA32_MTRR_PHYSMASK_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved1:11
UINT32 V:1
UINT32 PhysMask:20
UINT32 PhysMaskHi:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSMASK0 to #MSR_IA32_MTRR_PHYSMASK9

Field Documentation

struct { ... } MSR_IA32_MTRR_PHYSMASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::PhysMask

[Bits 31:12] PhysMask. MTRR address range mask.

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::PhysMaskHi

[Bits MAXPHYSADDR:32] PhysMask. Upper bits of MTRR address range mask. MAXPHYADDR: The bit position indicated by MAXPHYADDR depends on the maximum physical address range supported by the processor. It is reported by CPUID leaf function 80000008H. If CPUID does not support leaf 80000008H, the processor supports 36-bit physical address size, then bit PhysMask consists of bits 35:12, and bits 63:36 are reserved.

UINT64 MSR_IA32_MTRR_PHYSMASK_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_MTRR_PHYSMASK_REGISTER::V

[Bit 11] Valid Enable range mask.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_MTRRCAP_REGISTER Union Reference

Data Fields
MSR_IA32_MTRRCAP_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 VCNT:8
UINT32 FIX:1
UINT32 Reserved1:1
UINT32 WC:1
UINT32 SMRR:1
UINT32 Reserved2:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_MTRRCAP

Field Documentation

struct { ... } MSR_IA32_MTRRCAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_MTRRCAP_REGISTER::FIX

[Bit 8] Fixed range MTRRs are supported when set.

UINT32 MSR_IA32_MTRRCAP_REGISTER::SMRR

[Bit 11] SMRR Supported when set.

UINT32 MSR_IA32_MTRRCAP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_MTRRCAP_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_MTRRCAP_REGISTER::VCNT

[Bits 7:0] VCNT: The number of variable memory type ranges in the processor.

UINT32 MSR_IA32_MTRRCAP_REGISTER::WC

[Bit 10] WC Supported when set.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Union Reference

Data Fields
MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 HighTempEnable:1
UINT32 LowTempEnable:1
UINT32 PROCHOT_Enable:1
UINT32 Reserved1:1
UINT32 OverheatEnable:1
UINT32 Reserved2:3
UINT32 Threshold1:7
UINT32 Threshold1Enable:1
UINT32 Threshold2:7
UINT32 Threshold2Enable:1
UINT32 PowerLimitNotificationEnable:1
UINT32 Reserved3:7
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_INTERRUPT

Field Documentation

struct { ... } MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::HighTempEnable

[Bit 0] Pkg High-Temperature Interrupt Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::LowTempEnable

[Bit 1] Pkg Low-Temperature Interrupt Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::OverheatEnable

[Bit 4] Pkg Overheat Interrupt Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::PowerLimitNotificationEnable

[Bit 24] Pkg Power Limit Notification Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::PROCHOT_Enable

[Bit 2] Pkg PROCHOT# Interrupt Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold1

[Bits 14:8] Pkg Threshold #1 Value.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold1Enable

[Bit 15] Pkg Threshold #1 Interrupt Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold2

[Bits 22:16] Pkg Threshold #2 Value.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Threshold2Enable

[Bit 23] Pkg Threshold #2 Interrupt Enable.

UINT32 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_PACKAGE_THERM_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 ThermalStatus:1
UINT32 ThermalStatusLog:1
UINT32 PROCHOT_Event:1
UINT32 PROCHOT_Log:1
UINT32 CriticalTempStatus:1
UINT32 CriticalTempStatusLog:1
UINT32 ThermalThreshold1Status:1
UINT32 ThermalThreshold1Log:1
UINT32 ThermalThreshold2Status:1
UINT32 ThermalThreshold2Log:1
UINT32 PowerLimitStatus:1
UINT32 PowerLimitLog:1
UINT32 Reserved1:4
UINT32 DigitalReadout:7
UINT32 Reserved2:9
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PACKAGE_THERM_STATUS

Field Documentation

struct { ... } MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::CriticalTempStatus

[Bit 4] Pkg Critical Temperature Status (RO).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::CriticalTempStatusLog

[Bit 5] Pkg Critical Temperature Status log (R/WC0).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::DigitalReadout

[Bits 22:16] Pkg Digital Readout (RO).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PowerLimitLog

[Bit 11] Pkg Power Limitation log (R/WC0).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PowerLimitStatus

[Bit 10] Pkg Power Limitation Status (RO).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PROCHOT_Event

[Bit 2] Pkg PROCHOT # event (RO).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::PROCHOT_Log

[Bit 3] Pkg PROCHOT # log (R/WC0).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalStatus

[Bit 0] Pkg Thermal Status (RO):.

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalStatusLog

[Bit 1] Pkg Thermal Status Log (R/W):.

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold1Log

[Bit 7] Pkg Thermal Threshold #1 log (R/WC0).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold1Status

[Bit 6] Pkg Thermal Threshold #1 Status (RO).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold2Log

[Bit 9] Pkg Thermal Threshold #1 log (R/WC0).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::ThermalThreshold2Status

[Bit 8] Pkg Thermal Threshold #2 Status (RO).

UINT32 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PACKAGE_THERM_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PAT_REGISTER Union Reference

Data Fields
MSR_IA32_PAT_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 PA0:3
UINT32 Reserved1:5
UINT32 PA1:3
UINT32 Reserved2:5
UINT32 PA2:3
UINT32 Reserved3:5
UINT32 PA3:3
UINT32 Reserved4:5
UINT32 PA4:3
UINT32 Reserved5:5
UINT32 PA5:3
UINT32 Reserved6:5
UINT32 PA6:3
UINT32 Reserved7:5
UINT32 PA7:3
UINT32 Reserved8:5
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PAT

Field Documentation

struct { ... } MSR_IA32_PAT_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PAT_REGISTER::PA0

[Bits 2:0] PA0.

UINT32 MSR_IA32_PAT_REGISTER::PA1

[Bits 10:8] PA1.

UINT32 MSR_IA32_PAT_REGISTER::PA2

[Bits 18:16] PA2.

UINT32 MSR_IA32_PAT_REGISTER::PA3

[Bits 26:24] PA3.

UINT32 MSR_IA32_PAT_REGISTER::PA4

[Bits 34:32] PA4.

UINT32 MSR_IA32_PAT_REGISTER::PA5

[Bits 42:40] PA5.

UINT32 MSR_IA32_PAT_REGISTER::PA6

[Bits 50:48] PA6.

UINT32 MSR_IA32_PAT_REGISTER::PA7

[Bits 58:56] PA7.

UINT64 MSR_IA32_PAT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_IA32_PEBS_ENABLE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Enable:1
UINT32 Reserved1:3
UINT32 Reserved2:28
UINT32 Reserved3:4
UINT32 Reserved4:28
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PEBS_ENABLE

Field Documentation

struct { ... } MSR_IA32_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PEBS_ENABLE_REGISTER::Enable

[Bit 0] Enable PEBS on IA32_PMC0. Introduced at Display Family / Display Model 06_0FH.

UINT32 MSR_IA32_PEBS_ENABLE_REGISTER::Reserved1

[Bits 3:1] Reserved or Model specific.

UINT32 MSR_IA32_PEBS_ENABLE_REGISTER::Reserved3

[Bits 35:32] Reserved or Model specific.

UINT64 MSR_IA32_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_CAPABILITIES_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_CAPABILITIES_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 LBR_FMT:6
UINT32 PEBS_TRAP:1
UINT32 PEBS_ARCH_REG:1
UINT32 PEBS_REC_FMT:4
UINT32 SMM_FREEZE:1
UINT32 FW_WRITE:1
UINT32 Reserved1:18
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_CAPABILITIES

Field Documentation

struct { ... } MSR_IA32_PERF_CAPABILITIES_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::FW_WRITE

[Bit 13] 1: Full width of counter writable via IA32_A_PMCx.

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::LBR_FMT

[Bits 5:0] LBR format.

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_ARCH_REG

[Bit 7] PEBSSaveArchRegs.

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_REC_FMT

[Bits 11:8] PEBS Record Format.

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::PEBS_TRAP

[Bit 6] PEBS Trap.

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::SMM_FREEZE

[Bit 12] 1: Freeze while SMM is supported.

UINT32 MSR_IA32_PERF_CAPABILITIES_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PERF_CAPABILITIES_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_CTL_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_CTL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 TargetState:16
UINT32 Reserved1:16
UINT32 IDA:1
UINT32 Reserved2:31
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_CTL

Field Documentation

struct { ... } MSR_IA32_PERF_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_CTL_REGISTER::IDA

[Bit 32] IDA Engage. (R/W) When set to 1: disengages IDA. 06_0FH (Mobile only).

UINT32 MSR_IA32_PERF_CTL_REGISTER::TargetState

[Bits 15:0] Target performance State Value.

UINT64 MSR_IA32_PERF_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_GLOBAL_CTRL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 EN_PMCn:32
UINT32 EN_FIXED_CTRn:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_CTRL

Field Documentation

struct { ... } MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::EN_FIXED_CTRn

[Bits 63:32] EN_FIXED_CTRn. If CPUID.0AH: EDX[4:0] > n. Enable bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::EN_PMCn

[Bits 31:0] EN_PMCn. If CPUID.0AH: EAX[15:8] > n. Enable bitmask. Only the first n-1 bits are valid. Bits n..31 are reserved.

UINT64 MSR_IA32_PERF_GLOBAL_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_GLOBAL_INUSE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 IA32_PERFEVTSELn:32
UINT32 IA32_FIXED_CTRn:31
UINT32 PMI:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_INUSE

Field Documentation

struct { ... } MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::IA32_FIXED_CTRn

[Bits 62:32] IA32_FIXED_CTRn in use. If CPUID.0AH: EAX[7:0] > n. Status bitmask. Only the first n-1 bits are valid. Bits 30:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::IA32_PERFEVTSELn

[Bits 31:0] IA32_PERFEVTSELn in use. If CPUID.0AH: EAX[7:0] > n. Status bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::PMI

[Bit 63] PMI in use.

UINT64 MSR_IA32_PERF_GLOBAL_INUSE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Ovf_PMCn:32
UINT32 Ovf_FIXED_CTRn:23
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved2:5
UINT32 Ovf_Uncore:1
UINT32 OvfBuf:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_OVF_CTRL

Field Documentation

struct { ... } MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::CondChgd

[Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_FIXED_CTRn

[Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 22:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMCn

[Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / Display Model 06_2EH.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::OvfBuf

[Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.

UINT64 MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Reserved1:28
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 OvfBuf:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS

Field Documentation

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::ASCI

[Bit 60] ASCI: Data in the performance counters in the core PMU may include contributions from the direct or indirect operation intel SGX to protect an enclave. If CPUID.(EAX=07H, ECX=0):EBX[2] = 1.

struct { ... } MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::CondChgd

[Bit 63] CondChgd: status bits of this register has changed. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::CTR_Frz

[Bit 59] CTR_Frz: Performance counters in the core PMU are frozen due to - IA32_DEBUGCTL.FREEZE_PERFMON_ON_ PMI=1, - one or more core PMU counters overflowed. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::LBR_Frz

[Bit 58] LBR_Frz: LBRs are frozen due to - IA32_DEBUGCTL.FREEZE_LBR_ON_PMI=1, - The LBR stack overflowed. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr0

[Bit 32] Ovf_FixedCtr0: Overflow status of IA32_FIXED_CTR0. If CPUID.0AH: EAX[7:0] > 1.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr1

[Bit 33] Ovf_FixedCtr1: Overflow status of IA32_FIXED_CTR1. If CPUID.0AH: EAX[7:0] > 1.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr2

[Bit 34] Ovf_FixedCtr2: Overflow status of IA32_FIXED_CTR2. If CPUID.0AH: EAX[7:0] > 1.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC0

[Bit 0] Ovf_PMC0: Overflow status of IA32_PMC0. If CPUID.0AH: EAX[15:8] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC1

[Bit 1] Ovf_PMC1: Overflow status of IA32_PMC1. If CPUID.0AH: EAX[15:8] > 1.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC2

[Bit 2] Ovf_PMC2: Overflow status of IA32_PMC2. If CPUID.0AH: EAX[15:8] > 2.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC3

[Bit 3] Ovf_PMC3: Overflow status of IA32_PMC3. If CPUID.0AH: EAX[15:8] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_Uncore

[Bit 61] Ovf_Uncore: Uncore counter overflow status. If CPUID.0AH: EAX[7:0] > 2.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::OvfBuf

[Bit 62] OvfBuf: DS SAVE area Buffer overflow status. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Trace_ToPA_PMI

[Bit 55] Trace_ToPA_PMI: A PMI occurred due to a ToPA entry memory buffer was completely filled. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA = 1.

UINT64 MSR_IA32_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Ovf_PMCn:32
UINT32 Ovf_FIXED_CTRn:23
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved2:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 OvfBuf:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_RESET

Field Documentation

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI

[Bit 60] Set 1 to Clear ASCI bit. If CPUID.0AH: EAX[7:0] > 3.

struct { ... } MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd

[Bit 63] Set to 1to clear CondChgd: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz

[Bit 59] Set 1 to Clear CTR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz

[Bit 58] Set 1 to Clear LBR_Frz bit. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FIXED_CTRn

[Bits 54:32] Set 1 to Clear Ovf_FIXED_CTR0 bit. If CPUID.0AH: EDX[4:0] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 22:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMCn

[Bits 31:0] Set 1 to Clear Ovf_PMC0 bit. If CPUID.0AH: EAX[15:8] > n. Clear bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to Clear Ovf_Uncore bit. Introduced at Display Family / Display Model 06_2EH.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::OvfBuf

[Bit 62] Set 1 to Clear OvfBuf: bit. If CPUID.0AH: EAX[7:0] > 0.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to Clear Trace_ToPA_PMI bit. If (CPUID.(EAX=07H, ECX=0):EBX[25] = 1) && IA32_RTIT_CTL.ToPA[8] = 1.

UINT64 MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Ovf_PMCn:32
UINT32 Ovf_FIXED_CTRn:23
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved2:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 OvfBuf:1
UINT32 Reserved3:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_GLOBAL_STATUS_SET

Field Documentation

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::ASCI

[Bit 60] Set 1 to cause ASCI = 1. If CPUID.0AH: EAX[7:0] > 3.

struct { ... } MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::CTR_Frz

[Bit 59] Set 1 to cause CTR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::LBR_Frz

[Bit 58] Set 1 to cause LBR_Frz = 1. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FIXED_CTRn

[Bits 54:32] Set 1 to cause Ovf_FIXED_CTRn = 1. If CPUID.0AH: EAX[7:0] > n. Set bitmask. Only the first n-1 bits are valid. Bits 22:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMCn

[Bits 31:0] Set 1 to cause Ovf_PMCn = 1. If CPUID.0AH: EAX[7:0] > n. Set bitmask. Only the first n-1 bits are valid. Bits 31:n are reserved.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_Uncore

[Bit 61] Set 1 to cause Ovf_Uncore = 1. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::OvfBuf

[Bit 62] Set 1 to cause OvfBuf = 1. If CPUID.0AH: EAX[7:0] > 3.

UINT32 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Trace_ToPA_PMI

[Bit 55] Set 1 to cause Trace_ToPA_PMI = 1. If CPUID.0AH: EAX[7:0] > 3.

UINT64 MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERF_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_PERF_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 State:16
UINT32 Reserved1:16
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PERF_STATUS

Field Documentation

struct { ... } MSR_IA32_PERF_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERF_STATUS_REGISTER::State

[Bits 15:0] Current performance State Value.

UINT32 MSR_IA32_PERF_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PERF_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PERFEVTSEL_REGISTER Union Reference

Data Fields
MSR_IA32_PERFEVTSEL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 EventSelect:8
UINT32 UMASK:8
UINT32 USR:1
UINT32 OS:1
UINT32 E:1
UINT32 PC:1
UINT32 INT:1
UINT32 ANY:1
UINT32 EN:1
UINT32 INV:1
UINT32 CMASK:8
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_IA32_PERFEVTSEL0 to #MSR_IA32_PERFEVTSEL3

Field Documentation

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::ANY

[Bit 21] AnyThread: When set to 1, it enables counting the associated event conditions occurring across all logical processors sharing a processor core. When set to 0, the counter only increments the associated event conditions occurring in the logical processor which programmed the MSR.

struct { ... } MSR_IA32_PERFEVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::CMASK

[Bits 31:24] CMASK: When CMASK is not zero, the corresponding performance counter increments each cycle if the event count is greater than or equal to the CMASK.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::E

[Bit 18] Edge: Enables edge detection if set.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::EN

[Bit 22] EN: enables the corresponding performance counter to commence counting when this bit is set.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::EventSelect

[Bits 7:0] Event Select: Selects a performance event logic unit.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::INT

[Bit 20] INT: enables interrupt on counter overflow.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::INV

[Bit 23] INV: invert the CMASK.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::OS

[Bit 17] OS: Counts while in privilege level is ring 0.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::PC

[Bit 19] PC: enables pin control.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PERFEVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::UMASK

[Bits 15:8] UMask: Qualifies the microarchitectural condition to detect on the selected event logic.

UINT32 MSR_IA32_PERFEVTSEL_REGISTER::USR

[Bit 16] USR: Counts while in privilege level is not ring 0.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PKG_HDC_CTL_REGISTER Union Reference

Data Fields
MSR_IA32_PKG_HDC_CTL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 HDC_Pkg_Enable:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PKG_HDC_CTL

Field Documentation

struct { ... } MSR_IA32_PKG_HDC_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PKG_HDC_CTL_REGISTER::HDC_Pkg_Enable

[Bit 0] HDC_Pkg_Enable (R/W) Force HDC idling or wake up HDC-idled logical processors in the package. See Section 14.5.2, "Package level Enabling HDC". If CPUID.06H:EAX.[13] = 1.

UINT32 MSR_IA32_PKG_HDC_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PKG_HDC_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PLATFORM_ID_REGISTER Union Reference

Data Fields
MSR_IA32_PLATFORM_ID_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:18
UINT32 PlatformId:3
UINT32 Reserved3:11
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PLATFORM_ID

Field Documentation

struct { ... } MSR_IA32_PLATFORM_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PLATFORM_ID_REGISTER::PlatformId

[Bits 52:50] Platform Id (RO) Contains information concerning the intended platform for the processor. 52 51 50

0 0 0 Processor Flag 0. 0 0 1 Processor Flag 1 0 1 0 Processor Flag 2 0 1 1 Processor Flag 3 1 0 0 Processor Flag 4 1 0 1 Processor Flag 5 1 1 0 Processor Flag 6 1 1 1 Processor Flag 7

UINT64 MSR_IA32_PLATFORM_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PM_CTL1_REGISTER Union Reference

Data Fields
MSR_IA32_PM_CTL1_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 HDC_Allow_Block:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PM_CTL1

Field Documentation

struct { ... } MSR_IA32_PM_CTL1_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PM_CTL1_REGISTER::HDC_Allow_Block

[Bit 0] HDC_Allow_Block (R/W) Allow/Block this logical processor for package level HDC control. See Section 14.5.3. If CPUID.06H:EAX.[13] = 1.

UINT32 MSR_IA32_PM_CTL1_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PM_CTL1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PM_ENABLE_REGISTER Union Reference

Data Fields
MSR_IA32_PM_ENABLE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 HWP_ENABLE:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PM_ENABLE

Field Documentation

struct { ... } MSR_IA32_PM_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PM_ENABLE_REGISTER::HWP_ENABLE

[Bit 0] HWP_ENABLE (R/W1-Once). See Section 14.4.2, "Enabling HWP". If CPUID.06H:EAX.[7] = 1.

UINT32 MSR_IA32_PM_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_PM_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_PQR_ASSOC_REGISTER Union Reference

Data Fields
MSR_IA32_PQR_ASSOC_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 ResourceMonitoringID:32
UINT32 COS:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_PQR_ASSOC

Field Documentation

struct { ... } MSR_IA32_PQR_ASSOC_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_PQR_ASSOC_REGISTER::COS

[Bits 63:32] COS (R/W). The class of service (COS) to enforce (on writes); returns the current COS when read. If ( CPUID.(EAX=07H, ECX=0):EBX.[15] = 1 ).

UINT32 MSR_IA32_PQR_ASSOC_REGISTER::ResourceMonitoringID

[Bits 31:0] Resource Monitoring ID (R/W): ID for monitoring hardware to track internal operation, e.g. memory access. N = Ceil (Log:sub:2 ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).

UINT64 MSR_IA32_PQR_ASSOC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_QM_CTR_REGISTER Union Reference

Data Fields
MSR_IA32_QM_CTR_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 ResourceMonitoredData:32
UINT32 ResourceMonitoredDataHi:30
UINT32 Unavailable:1
UINT32 Error:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_QM_CTR

Field Documentation

struct { ... } MSR_IA32_QM_CTR_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_QM_CTR_REGISTER::Error

[Bit 63] Error: If 1, indicates and unsupported RMID or event type was written to IA32_PQR_QM_EVTSEL.

UINT32 MSR_IA32_QM_CTR_REGISTER::ResourceMonitoredData

[Bits 31:0] Resource Monitored Data.

UINT32 MSR_IA32_QM_CTR_REGISTER::ResourceMonitoredDataHi

[Bits 61:32] Resource Monitored Data.

UINT64 MSR_IA32_QM_CTR_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_QM_CTR_REGISTER::Unavailable

[Bit 62] Unavailable: If 1, indicates data for this RMID is not available or not monitored for this resource or RMID.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_QM_EVTSEL_REGISTER Union Reference

Data Fields
MSR_IA32_QM_EVTSEL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 EventID:8
UINT32 Reserved:24
UINT32 ResourceMonitoringID:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_QM_EVTSEL

Field Documentation

struct { ... } MSR_IA32_QM_EVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_QM_EVTSEL_REGISTER::EventID

[Bits 7:0] Event ID: ID of a supported monitoring event to report via IA32_QM_CTR.

UINT32 MSR_IA32_QM_EVTSEL_REGISTER::ResourceMonitoringID

[Bits 63:32] Resource Monitoring ID: ID for monitoring hardware to report monitored data via IA32_QM_CTR. N = Ceil (Log:sub:2 ( CPUID.(EAX= 0FH, ECX=0H).EBX[31:0] +1)).

UINT64 MSR_IA32_QM_EVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_RTIT_ADDR_REGISTER Union Reference

Data Fields
MSR_IA32_RTIT_ADDR_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 VirtualAddress:32
UINT32 VirtualAddressHi:16
UINT32 SignExt_VA:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_IA32_RTIT_ADDR0_A to #MSR_IA32_RTIT_ADDR3_A and #MSR_IA32_RTIT_ADDR0_B to #MSR_IA32_RTIT_ADDR3_B

Field Documentation

struct { ... } MSR_IA32_RTIT_ADDR_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_RTIT_ADDR_REGISTER::SignExt_VA

[Bits 63:48] SignExt_VA.

UINT64 MSR_IA32_RTIT_ADDR_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_RTIT_ADDR_REGISTER::VirtualAddress

[Bits 31:0] Virtual Address.

UINT32 MSR_IA32_RTIT_ADDR_REGISTER::VirtualAddressHi

[Bits 47:32] Virtual Address.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_RTIT_CR3_MATCH_REGISTER Union Reference

Data Fields
MSR_IA32_RTIT_CR3_MATCH_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved:5
UINT32 Cr3:27
UINT32 Cr3Hi:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_RTIT_CR3_MATCH

Field Documentation

struct { ... } MSR_IA32_RTIT_CR3_MATCH_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_RTIT_CR3_MATCH_REGISTER::Cr3

[Bits 31:5] CR3[63:5] value to match.

UINT32 MSR_IA32_RTIT_CR3_MATCH_REGISTER::Cr3Hi

[Bits 63:32] CR3[63:5] value to match.

UINT64 MSR_IA32_RTIT_CR3_MATCH_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_RTIT_CTL_REGISTER Union Reference

Data Fields
MSR_IA32_RTIT_CTL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 TraceEn:1
UINT32 CYCEn:1
UINT32 OS:1
UINT32 User:1
UINT32 PwrEvtEn:1
UINT32 FUPonPTW:1
UINT32 FabricEn:1
UINT32 CR3:1
UINT32 ToPA:1
UINT32 MTCEn:1
UINT32 TSCEn:1
UINT32 DisRETC:1
UINT32 PTWEn:1
UINT32 BranchEn:1
UINT32 MTCFreq:4
UINT32 Reserved3:1
UINT32 CYCThresh:4
UINT32 Reserved4:1
UINT32 PSBFreq:4
UINT32 Reserved5:4
UINT32 ADDR0_CFG:4
UINT32 ADDR1_CFG:4
UINT32 ADDR2_CFG:4
UINT32 ADDR3_CFG:4
UINT32 Reserved6:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_RTIT_CTL

Field Documentation

UINT32 MSR_IA32_RTIT_CTL_REGISTER::ADDR0_CFG

[Bits 35:32] ADDR0_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 0).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::ADDR1_CFG

[Bits 39:36] ADDR1_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::ADDR2_CFG

[Bits 43:40] ADDR2_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 2).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::ADDR3_CFG

[Bits 47:44] ADDR3_CFG. If (CPUID.(EAX=07H, ECX=1):EAX[2:0] > 3).

struct { ... } MSR_IA32_RTIT_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_RTIT_CTL_REGISTER::BranchEn

[Bit 13] BranchEn.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::CR3

[Bit 7] CR3 filter.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::CYCEn

[Bit 1] CYCEn. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::CYCThresh

[Bits 22:19] CYCThresh. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::DisRETC

[Bit 11] DisRETC.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::FabricEn

[Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::FUPonPTW

[Bit 5] FUPonPTW.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::MTCEn

[Bit 9] MTCEn. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::MTCFreq

[Bits 17:14] MTCFreq. If (CPUID.(EAX=07H, ECX=0):EBX[3] = 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::OS

[Bit 2] OS.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::PSBFreq

[Bits 27:24] PSBFreq. If (CPUID.(EAX=07H, ECX=0):EBX[1] = 1).

UINT32 MSR_IA32_RTIT_CTL_REGISTER::PTWEn

[Bit 12] PTWEn.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::PwrEvtEn

[Bit 4] PwrEvtEn.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::ToPA

[Bit 8] ToPA.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::TraceEn

[Bit 0] TraceEn.

UINT32 MSR_IA32_RTIT_CTL_REGISTER::TSCEn

[Bit 10] TSCEn.

UINT64 MSR_IA32_RTIT_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_RTIT_CTL_REGISTER::User

[Bit 3] User.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Union Reference

Data Fields
MSR_IA32_RTIT_OUTPUT_BASE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved:7
UINT32 Base:25
UINT32 BaseHi:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_BASE

Field Documentation

UINT32 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::Base

[Bits 31:7] Base physical address.

UINT32 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::BaseHi

[Bits 63:32] Base physical address.

struct { ... } MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::Bits

Individual bit fields

UINT64 MSR_IA32_RTIT_OUTPUT_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Union Reference

Data Fields
MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved:7
UINT32 MaskOrTableOffset:25
UINT32 OutputOffset:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_RTIT_OUTPUT_MASK_PTRS

Field Documentation

struct { ... } MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::MaskOrTableOffset

[Bits 31:7] MaskOrTableOffset.

UINT32 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::OutputOffset

[Bits 63:32] Output Offset.

UINT64 MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_RTIT_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_RTIT_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 FilterEn:1
UINT32 ContexEn:1
UINT32 TriggerEn:1
UINT32 Reserved1:1
UINT32 Error:1
UINT32 Stopped:1
UINT32 Reserved2:26
UINT32 PacketByteCnt:17
UINT32 Reserved3:15
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_RTIT_STATUS

Field Documentation

struct { ... } MSR_IA32_RTIT_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_RTIT_STATUS_REGISTER::ContexEn

[Bit 1] ContexEn, (writes ignored).

UINT32 MSR_IA32_RTIT_STATUS_REGISTER::Error

[Bit 4] Error.

UINT32 MSR_IA32_RTIT_STATUS_REGISTER::FilterEn

[Bit 0] FilterEn, (writes ignored). If (CPUID.(EAX=07H, ECX=0):EBX[2] = 1).

UINT32 MSR_IA32_RTIT_STATUS_REGISTER::PacketByteCnt

[Bits 48:32] PacketByteCnt. If (CPUID.(EAX=07H, ECX=0):EBX[1] > 3).

UINT32 MSR_IA32_RTIT_STATUS_REGISTER::Stopped

[Bit 5] Stopped.

UINT32 MSR_IA32_RTIT_STATUS_REGISTER::TriggerEn

[Bit 2] TriggerEn, (writes ignored).

UINT64 MSR_IA32_RTIT_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_SGX_SVN_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_SGX_SVN_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Lock:1
UINT32 Reserved1:15
UINT32 SGX_SVN_SINIT:8
UINT32 Reserved2:8
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_SGX_SVN_STATUS

Field Documentation

struct { ... } MSR_IA32_SGX_SVN_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_SGX_SVN_STATUS_REGISTER::Lock

[Bit 0] Lock. See Section 41.11.3, "Interactions with Authenticated Code Modules (ACMs)".

UINT32 MSR_IA32_SGX_SVN_STATUS_REGISTER::SGX_SVN_SINIT

[Bits 23:16] SGX_SVN_SINIT. See Section 41.11.3, "Interactions with Authenticated Code Modules (ACMs)".

UINT32 MSR_IA32_SGX_SVN_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_SGX_SVN_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_SMM_MONITOR_CTL_REGISTER Union Reference

Data Fields
MSR_IA32_SMM_MONITOR_CTL_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Valid:1
UINT32 Reserved1:1
UINT32 BlockSmi:1
UINT32 Reserved2:9
UINT32 MsegBase:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_SMM_MONITOR_CTL

Field Documentation

struct { ... } MSR_IA32_SMM_MONITOR_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_SMM_MONITOR_CTL_REGISTER::BlockSmi

[Bit 2] Controls SMI unblocking by VMXOFF (see Section 34.14.4). If IA32_VMX_MISC[28].

UINT32 MSR_IA32_SMM_MONITOR_CTL_REGISTER::MsegBase

[Bits 31:12] MSEG Base (R/W).

UINT32 MSR_IA32_SMM_MONITOR_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_SMM_MONITOR_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_SMM_MONITOR_CTL_REGISTER::Valid

[Bit 0] Valid (R/W). The STM may be invoked using VMCALL only if this bit is 1. Because VMCALL is used to activate the dual-monitor treatment (see Section 34.15.6), the dual-monitor treatment cannot be activated if the bit is 0. This bit is cleared when the logical processor is reset.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_SMRR_PHYSBASE_REGISTER Union Reference

Data Fields
MSR_IA32_SMRR_PHYSBASE_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Type:8
UINT32 Reserved1:4
UINT32 PhysBase:20
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_SMRR_PHYSBASE

Field Documentation

struct { ... } MSR_IA32_SMRR_PHYSBASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_SMRR_PHYSBASE_REGISTER::PhysBase

[Bits 31:12] PhysBase. SMRR physical Base Address.

UINT32 MSR_IA32_SMRR_PHYSBASE_REGISTER::Type

[Bits 7:0] Type. Specifies memory type of the range.

UINT32 MSR_IA32_SMRR_PHYSBASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_SMRR_PHYSBASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_SMRR_PHYSMASK_REGISTER Union Reference

Data Fields
MSR_IA32_SMRR_PHYSMASK_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved1:11
UINT32 Valid:1
UINT32 PhysMask:20
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_SMRR_PHYSMASK

Field Documentation

struct { ... } MSR_IA32_SMRR_PHYSMASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_SMRR_PHYSMASK_REGISTER::PhysMask

[Bits 31:12] PhysMask SMRR address range mask.

UINT32 MSR_IA32_SMRR_PHYSMASK_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_SMRR_PHYSMASK_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_SMRR_PHYSMASK_REGISTER::Valid

[Bit 11] Valid Enable range mask.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_SYSENTER_CS_REGISTER Union Reference

Data Fields
MSR_IA32_SYSENTER_CS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 CS:16
UINT32 Reserved1:16
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_SYSENTER_CS

Field Documentation

struct { ... } MSR_IA32_SYSENTER_CS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_SYSENTER_CS_REGISTER::CS

[Bits 15:0] CS Selector.

UINT32 MSR_IA32_SYSENTER_CS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_SYSENTER_CS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_THERM_INTERRUPT_REGISTER Union Reference

Data Fields
MSR_IA32_THERM_INTERRUPT_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 HighTempEnable:1
UINT32 LowTempEnable:1
UINT32 PROCHOT_Enable:1
UINT32 FORCEPR_Enable:1
UINT32 CriticalTempEnable:1
UINT32 Reserved1:3
UINT32 Threshold1:7
UINT32 Threshold1Enable:1
UINT32 Threshold2:7
UINT32 Threshold2Enable:1
UINT32 PowerLimitNotificationEnable:1
UINT32 Reserved2:7
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_THERM_INTERRUPT

Field Documentation

struct { ... } MSR_IA32_THERM_INTERRUPT_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::CriticalTempEnable

[Bit 4] Critical Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::FORCEPR_Enable

[Bit 3] FORCEPR# Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::HighTempEnable

[Bit 0] High-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::LowTempEnable

[Bit 1] Low-Temperature Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::PowerLimitNotificationEnable

[Bit 24] Power Limit Notification Enable. If CPUID.06H:EAX[4] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::PROCHOT_Enable

[Bit 2] PROCHOT# Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold1

[Bits 14:8] Threshold #1 Value. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold1Enable

[Bit 15] Threshold #1 Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold2

[Bits 22:16] Threshold #2 Value. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::Threshold2Enable

[Bit 23] Threshold #2 Interrupt Enable. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_INTERRUPT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_THERM_INTERRUPT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_THERM_STATUS_REGISTER Union Reference

Data Fields
MSR_IA32_THERM_STATUS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 ThermalStatus:1
UINT32 ThermalStatusLog:1
UINT32 PROCHOT_FORCEPR_Event:1
UINT32 PROCHOT_FORCEPR_Log:1
UINT32 CriticalTempStatus:1
UINT32 CriticalTempStatusLog:1
UINT32 ThermalThreshold1Status:1
UINT32 ThermalThreshold1Log:1
UINT32 ThermalThreshold2Status:1
UINT32 ThermalThreshold2Log:1
UINT32 PowerLimitStatus:1
UINT32 PowerLimitLog:1
UINT32 CurrentLimitStatus:1
UINT32 CurrentLimitLog:1
UINT32 CrossDomainLimitStatus:1
UINT32 CrossDomainLimitLog:1
UINT32 DigitalReadout:7
UINT32 Reserved1:4
UINT32 ResolutionInDegreesCelsius:4
UINT32 ReadingValid:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_THERM_STATUS

Field Documentation

struct { ... } MSR_IA32_THERM_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_THERM_STATUS_REGISTER::CriticalTempStatus

[Bit 4] Critical Temperature Status (RO). If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::CriticalTempStatusLog

[Bit 5] Critical Temperature Status log (R/WC0). If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::CrossDomainLimitLog

[Bit 15] Cross Domain Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::CrossDomainLimitStatus

[Bit 14] Cross Domain Limit Status (RO). If CPUID.06H:EAX[7] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::CurrentLimitLog

[Bit 13] Current Limit log (R/WC0). If CPUID.06H:EAX[7] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::CurrentLimitStatus

[Bit 12] Current Limit Status (RO). If CPUID.06H:EAX[7] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::DigitalReadout

[Bits 22:16] Digital Readout (RO). If CPUID.06H:EAX[0] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::PowerLimitLog

[Bit 11] Power Limitation log (R/WC0). If CPUID.06H:EAX[4] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::PowerLimitStatus

[Bit 10] Power Limitation Status (RO). If CPUID.06H:EAX[4] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::PROCHOT_FORCEPR_Event

[Bit 2] PROCHOT # or FORCEPR# event (RO). If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::PROCHOT_FORCEPR_Log

[Bit 3] PROCHOT # or FORCEPR# log (R/WC0). If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ReadingValid

[Bit 31] Reading Valid (RO). If CPUID.06H:EAX[0] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ResolutionInDegreesCelsius

[Bits 30:27] Resolution in Degrees Celsius (RO). If CPUID.06H:EAX[0] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ThermalStatus

[Bit 0] Thermal Status (RO):. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ThermalStatusLog

[Bit 1] Thermal Status Log (R/W):. If CPUID.01H:EDX[22] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold1Log

[Bit 7] Thermal Threshold #1 log (R/WC0). If CPUID.01H:ECX[8] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold1Status

[Bit 6] Thermal Threshold #1 Status (RO). If CPUID.01H:ECX[8] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold2Log

[Bit 9] Thermal Threshold #2 log (R/WC0). If CPUID.01H:ECX[8] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::ThermalThreshold2Status

[Bit 8] Thermal Threshold #2 Status (RO). If CPUID.01H:ECX[8] = 1.

UINT32 MSR_IA32_THERM_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_THERM_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_TSC_AUX_REGISTER Union Reference

Data Fields
MSR_IA32_TSC_AUX_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 AUX:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_TSC_AUX

Field Documentation

UINT32 MSR_IA32_TSC_AUX_REGISTER::AUX

[Bits 31:0] AUX: Auxiliary signature of TSC.

struct { ... } MSR_IA32_TSC_AUX_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_TSC_AUX_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_TSC_AUX_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_VMX_BASIC_REGISTER Union Reference

Data Fields
MSR_IA32_VMX_BASIC_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 VmcsRevisonId:31
UINT32 MustBeZero:1
UINT32 VmcsSize:13
UINT32 Reserved1:3
UINT32 VmcsAddressWidth:1
UINT32 DualMonitor:1
UINT32 MemoryType:4
UINT32 InsOutsReporting:1
UINT32 VmxControls:1
UINT32 Reserved2:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_VMX_BASIC

Field Documentation

struct { ... } MSR_IA32_VMX_BASIC_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_VMX_BASIC_REGISTER::DualMonitor

[Bit 49] If bit 49 is read as 1, the logical processor supports the dual-monitor treatment of system-management interrupts and system-management mode. See Section 34.15 for details of this treatment.

UINT32 MSR_IA32_VMX_BASIC_REGISTER::InsOutsReporting

[Bit 54] If bit 54 is read as 1, the processor reports information in the VM-exit instruction-information field on VM exitsdue to execution of the INS and OUTS instructions (see Section 27.2.4). This reporting is done only if this bit is read as 1.

UINT32 MSR_IA32_VMX_BASIC_REGISTER::MemoryType

[Bit 53:50] report the memory type that should be used for the VMCS, for data structures referenced by pointers in the VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX transitions), and for the MSEG header. If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it can configure the paging structures to map them into the linear-address space. If it does so, it should establish mappings that use the memory type reported bits 53:50 in this MSR.

As of this writing, all processors that support VMX operation indicate the write-back type.

If software needs to access these data structures (e.g., to modify the contents of the MSR bitmaps), it can configure the paging structures to map them into the linear-address space. If it does so, it should establish mappings that use the memory type reported in this MSR.

Note
Alternatively, software may map any of these regions or structures with the UC memory type. (This may be necessary for the MSEG header.) Doing so is discouraged unless necessary as it will cause the performance of software accesses to those structures to suffer.
UINT64 MSR_IA32_VMX_BASIC_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_IA32_VMX_BASIC_REGISTER::VmcsAddressWidth

[Bit 48] Indicates the width of the physical addresses that may be used for the VMXON region, each VMCS, and data structures referenced by pointers in a VMCS (I/O bitmaps, virtual-APIC page, MSR areas for VMX transitions). If the bit is 0, these addresses are limited to the processor's physical-address width. If the bit is 1, these addresses are limited to 32 bits. This bit is always 0 for processors that support Intel 64 architecture.

Note
On processors that support Intel 64 architecture, the pointer must not set bits beyond the processor's physical address width.
UINT32 MSR_IA32_VMX_BASIC_REGISTER::VmcsRevisonId

[Bits 30:0] VMCS revision identifier used by the processor. Processors that use the same VMCS revision identifier use the same size for VMCS regions (see subsequent item on bits 44:32).

Note
Earlier versions of this manual specified that the VMCS revision identifier was a 32-bit field in bits 31:0 of this MSR. For all processors produced prior to this change, bit 31 of this MSR was read as 0.
UINT32 MSR_IA32_VMX_BASIC_REGISTER::VmcsSize

[Bit 44:32] Reports the number of bytes that software should allocate for the VMXON region and any VMCS region. It is a value greater than 0 and at most 4096(bit 44 is set if and only if bits 43:32 are clear).

UINT32 MSR_IA32_VMX_BASIC_REGISTER::VmxControls

[Bit 55] Bit 55 is read as 1 if any VMX controls that default to 1 may be cleared to 0. See Appendix A.2 for details. It also reports support for the VMX capability MSRs IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and IA32_VMX_TRUE_ENTRY_CTLS. See Appendix A.3.1, Appendix A.3.2, Appendix A.4, and Appendix A.5 for details.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IA32_XSS_REGISTER Union Reference

Data Fields
MSR_IA32_XSS_REGISTER Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 TracePacketConfigurationState:1
UINT32 Reserved2:23
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IA32_XSS

Field Documentation

struct { ... } MSR_IA32_XSS_REGISTER::Bits

Individual bit fields

UINT32 MSR_IA32_XSS_REGISTER::TracePacketConfigurationState

[Bit 8] Trace Packet Configuration State (R/W).

UINT32 MSR_IA32_XSS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IA32_XSS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 TDP_LEVEL:2
UINT32 Reserved1:29
UINT32 Config_TDP_Lock:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL

Field Documentation

struct { ... } MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER::Config_TDP_Lock

[Bit 31] Config_TDP_Lock (RW/L) When this bit is set, the content of this register is locked until a reset.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER::TDP_LEVEL

[Bits 1:0] TDP_LEVEL (RW/L) System BIOS can program this field.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 PKG_TDP_LVL1:15
UINT32 Reserved1:1
UINT32 Config_TDP_LVL1_Ratio:8
UINT32 Reserved2:8
UINT32 PKG_MAX_PWR_LVL1:15
UINT32 Reserved3:1
UINT32 PKG_MIN_PWR_LVL1:15
UINT32 Reserved4:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1

Field Documentation

struct { ... } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER::Config_TDP_LVL1_Ratio

[Bits 23:16] Config_TDP_LVL1_Ratio. ConfigTDP level 1 ratio to be used for this specific processor.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER::PKG_MAX_PWR_LVL1

[Bits 46:32] PKG_MAX_PWR_LVL1. Max Power setting allowed for ConfigTDP Level 1.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER::PKG_MIN_PWR_LVL1

[Bits 62:48] PKG_MIN_PWR_LVL1. MIN Power setting allowed for ConfigTDP Level 1.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER::PKG_TDP_LVL1

[Bits 14:0] PKG_TDP_LVL1. Power setting for ConfigTDP Level 1.

UINT64 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 PKG_TDP_LVL2:15
UINT32 Reserved1:1
UINT32 Config_TDP_LVL2_Ratio:8
UINT32 Reserved2:8
UINT32 PKG_MAX_PWR_LVL2:15
UINT32 Reserved3:1
UINT32 PKG_MIN_PWR_LVL2:15
UINT32 Reserved4:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2

Field Documentation

struct { ... } MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Config_TDP_LVL2_Ratio

[Bits 23:16] Config_TDP_LVL2_Ratio. ConfigTDP level 2 ratio to be used for this specific processor.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::PKG_MAX_PWR_LVL2

[Bits 46:32] PKG_MAX_PWR_LVL2. Max Power setting allowed for ConfigTDP Level 2.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::PKG_MIN_PWR_LVL2

[Bits 62:48] PKG_MIN_PWR_LVL2. MIN Power setting allowed for ConfigTDP Level 2.

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::PKG_TDP_LVL2

[Bits 14:0] PKG_TDP_LVL2. Power setting for ConfigTDP Level 2.

UINT64 MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Config_TDP_Base:8
UINT32 Reserved1:24
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL

Field Documentation

struct { ... } MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER::Config_TDP_Base

[Bits 7:0] Config_TDP_Base Base TDP level ratio to be used for this specific processor (in units of 100 MHz).

UINT32 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 MemErrorLogEnable:1
UINT32 Reserved2:30
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_ERROR_CONTROL

Field Documentation

struct { ... } MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER::MemErrorLogEnable

[Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank to log additional info in bits 36:32.

UINT32 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 RecoverableAddressLSB:6
UINT32 AddressMode:3
UINT32 Reserved1:7
UINT32 PCIExpressRequestorID:16
UINT32 PCIExpressSegmentNumber:8
UINT32 Reserved2:24
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_IA32_MC6_MISC

Field Documentation

UINT32 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER::AddressMode

[Bits 8:6] Address Mode.

struct { ... } MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER::PCIExpressRequestorID

[Bits 31:16] PCI Express Requestor ID.

UINT32 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER::PCIExpressSegmentNumber

[Bits 39:32] PCI Express Segment Number.

UINT32 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER::RecoverableAddressLSB

[Bits 5:0] Recoverable Address LSB.

UINT64 MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 PEBS_EN_PMC0:1
UINT32 PEBS_EN_PMC1:1
UINT32 PEBS_EN_PMC2:1
UINT32 PEBS_EN_PMC3:1
UINT32 Reserved1:28
UINT32 LL_EN_PMC0:1
UINT32 LL_EN_PMC1:1
UINT32 LL_EN_PMC2:1
UINT32 LL_EN_PMC3:1
UINT32 Reserved2:28
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_PEBS_ENABLE

Field Documentation

struct { ... } MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC0

[Bit 32] Enable Load Latency on IA32_PMC0. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC1

[Bit 33] Enable Load Latency on IA32_PMC1. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC2

[Bit 34] Enable Load Latency on IA32_PMC2. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC3

[Bit 35] Enable Load Latency on IA32_PMC3. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC0

[Bit 0] Enable PEBS on IA32_PMC0. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC1

[Bit 1] Enable PEBS on IA32_PMC1. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC2

[Bit 2] Enable PEBS on IA32_PMC2. (R/W).

UINT32 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC3

[Bit 3] Enable PEBS on IA32_PMC3. (R/W).

UINT64 MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:9
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 Reserved4:3
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 state auto demotion enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from demoted C1.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 state auto demotion enable (R/W) When set, the processor will conditionally demote C6/C7 requests to C3 based on uncore auto-demote information.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from demoted C3.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register until next reset.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power). for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: This field cannot be used to limit package C-state to C3.

UINT32 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:7
UINT32 PPIN_CAP:1
UINT32 Reserved3:4
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 TJOFFSET:1
UINT32 Reserved4:1
UINT32 Reserved5:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved6:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO_1

Field Documentation

struct { ... } MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::PPIN_CAP

[Bit 23] Package. PPIN_CAP (R/O) When set to 1, indicates that Protected Processor Inventory Number (PPIN) capability can be enabled for privileged system inventory agent to read PPIN from MSR_PPIN. When set to 0, PPIN capability is not supported. An attempt to access MSR_PPIN_CTL or MSR_PPIN will cause #GP.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::TJOFFSET

[Bit 30] Package. Programmable TJ OFFSET (R/O) When set to 1, indicates that MSR_TEMPERATURE_TARGET.[27:24] is valid and writable to specify an temperature offset.

UINT64 MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:12
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 Reserved3:2
UINT32 LowPowerModeSupport:1
UINT32 ConfigTDPLevels:2
UINT32 Reserved4:5
UINT32 MaximumEfficiencyRatio:8
UINT32 MinimumOperatingRatio:8
UINT32 Reserved5:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_PLATFORM_INFO

Field Documentation

struct { ... } MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::ConfigTDPLevels

[Bits 34:33] Package. Number of ConfigTDP Levels (R/O) 00: Only Base TDP level available. 01: One additional TDP level available. 02: Two additional TDP level available. 11: Reserved.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::LowPowerModeSupport

[Bit 32] Package. Low Power Mode Support (LPM) (R/O) When set to 1, indicates that LPM is supported, and when set to 0, indicates LPM is not supported.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::MinimumOperatingRatio

[Bits 55:48] Package. Minimum Operating Ratio (R/O) Contains the minimum supported operating ratio in units of 100 MHz.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT64 MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 LockOut:1
UINT32 Enable_PPIN:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_PPIN_CTL

Field Documentation

struct { ... } MSR_IVY_BRIDGE_PPIN_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER::Enable_PPIN

[Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0.

UINT32 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER::LockOut

[Bit 0] LockOut (R/WO) Set 1to prevent further writes to MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is clear, Default is 0. BIOS should provide an opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for privileged inventory initialization agent to access MSR_PPIN. After reading MSR_PPIN, the privileged inventory initialization agent should write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and prevent unauthorized modification to MSR_PPIN_CTL.

UINT32 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_PPIN_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 TCCActivationOffset:4
UINT32 Reserved2:4
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER::TCCActivationOffset

[Bits 27:24] TCC Activation Offset (R/W) Specifies a temperature offset in degrees C from the temperature target (bits 23:16). PROCHOT# will assert at the offset target temperature. Write is permitted only MSR_PLATFORM_INFO.[30] is set.

UINT32 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (RO) The minimum temperature at which PROCHOT# will be asserted. The value is degree C.

UINT32 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 MAX_NON_TURBO_RATIO:8
UINT32 Reserved1:23
UINT32 TURBO_ACTIVATION_RATIO_Lock:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO

Field Documentation

struct { ... } MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER::MAX_NON_TURBO_RATIO

[Bits 7:0] MAX_NON_TURBO_RATIO (RW/L) System BIOS can program this field.

UINT32 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER::TURBO_ACTIVATION_RATIO_Lock

[Bit 31] TURBO_ACTIVATION_RATIO_Lock (RW/L) When this bit is set, the content of this register is locked until a reset.

UINT32 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Union Reference

Data Fields
MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER Union Reference

#include <IvyBridgeMsr.h>

Data Fields

struct {
UINT32 Maximum9C:8
UINT32 Maximum10C:8
UINT32 Maximum11C:8
UINT32 Maximum12C:8
UINT32 Maximum13C:8
UINT32 Maximum14C:8
UINT32 Maximum15C:8
UINT32 Reserved:7
UINT32 TurboRatioLimitConfigurationSemaphore:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1

Field Documentation

struct { ... } MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Bits

Individual bit fields

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum10C

[Bits 15:8] Package. Maximum Ratio Limit for 10C Maximum turbo ratio limit of 10core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum11C

[Bits 23:16] Package. Maximum Ratio Limit for 11C Maximum turbo ratio limit of 11 core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum12C

[Bits 31:24] Package. Maximum Ratio Limit for 12C Maximum turbo ratio limit of 12 core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum13C

[Bits 39:32] Package. Maximum Ratio Limit for 13C Maximum turbo ratio limit of 13 core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum14C

[Bits 47:40] Package. Maximum Ratio Limit for 14C Maximum turbo ratio limit of 14 core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum15C

[Bits 55:48] Package. Maximum Ratio Limit for 15C Maximum turbo ratio limit of 15 core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Maximum9C

[Bits 7:0] Package. Maximum Ratio Limit for 9C Maximum turbo ratio limit of 9 core active.

UINT32 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::TurboRatioLimitConfigurationSemaphore

[Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration specified in MSR_TURBO_RATIO_LIMIT and MSR_TURBO_RATIO_LIMIT1. If 0, the processor uses factory-set configuration (Default).

UINT64 MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Union Reference

Data Fields
MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 FromMtoS:1
UINT32 FromEtoS:1
UINT32 FromStoS:1
UINT32 FromFtoS:1
UINT32 FromMtoI:1
UINT32 FromEtoI:1
UINT32 FromStoI:1
UINT32 FromFtoI:1
UINT32 Reserved1:24
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_GQ_SNOOP_MESF

Field Documentation

struct { ... } MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromEtoI

[Bit 5] From E to I (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromEtoS

[Bit 1] From E to S (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromFtoI

[Bit 7] From F to I (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromFtoS

[Bit 3] From F to S (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromMtoI

[Bit 4] From M to I (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromMtoS

[Bit 0] From M to S (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromStoI

[Bit 6] From S to I (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::FromStoS

[Bit 2] From S to S (R/W).

UINT32 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:3
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved4:3
UINT32 EIST:1
UINT32 Reserved5:1
UINT32 MONITOR:1
UINT32 Reserved6:3
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:2
UINT32 XD:1
UINT32 Reserved9:3
UINT32 TurboModeDisable:1
UINT32 Reserved10:25
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Thread. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 1.

struct { ... } MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Thread. Fast-Strings Enable See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Thread. ENABLE MONITOR FSM. (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

UINT64 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_LBR_SELECT_REGISTER Union Reference

Data Fields
MSR_NEHALEM_LBR_SELECT_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 CPL_EQ_0:1
UINT32 CPL_NEQ_0:1
UINT32 JCC:1
UINT32 NEAR_REL_CALL:1
UINT32 NEAR_IND_CALL:1
UINT32 NEAR_RET:1
UINT32 NEAR_IND_JMP:1
UINT32 NEAR_REL_JMP:1
UINT32 FAR_BRANCH:1
UINT32 Reserved1:23
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_LBR_SELECT

Field Documentation

struct { ... } MSR_NEHALEM_LBR_SELECT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::CPL_EQ_0

[Bit 0] CPL_EQ_0.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::CPL_NEQ_0

[Bit 1] CPL_NEQ_0.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::FAR_BRANCH

[Bit 8] FAR_BRANCH.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::JCC

[Bit 2] JCC.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::NEAR_IND_CALL

[Bit 4] NEAR_IND_CALL.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::NEAR_IND_JMP

[Bit 6] NEAR_IND_JMP.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::NEAR_REL_CALL

[Bit 3] NEAR_REL_CALL.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::NEAR_REL_JMP

[Bit 7] NEAR_REL_JMP.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::NEAR_RET

[Bit 5] NEAR_RET.

UINT32 MSR_NEHALEM_LBR_SELECT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_LBR_SELECT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 L2HardwarePrefetcherDisable:1
UINT32 L2AdjacentCacheLinePrefetcherDisable:1
UINT32 DCUHardwarePrefetcherDisable:1
UINT32 DCUIPPrefetcherDisable:1
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_MISC_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache.

UINT32 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::DCUIPPrefetcherDisable

[Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 data cache IP prefetcher, which uses sequential load history (based on instruction Pointer of previous loads) to determine whether to prefetch additional lines.

UINT32 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::L2AdjacentCacheLinePrefetcherDisable

[Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, disables the adjacent cache line prefetcher, which fetches the cache line that comprises a cache line pair (128 bytes).

UINT32 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache.

UINT32 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Union Reference

Data Fields
MSR_NEHALEM_MISC_PWR_MGMT_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 EISTHardwareCoordinationDisable:1
UINT32 EnergyPerformanceBiasEnable:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_MISC_PWR_MGMT

Field Documentation

struct { ... } MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::EISTHardwareCoordinationDisable

[Bit 0] Package. EIST Hardware Coordination Disable (R/W) When 0, enables hardware coordination of Enhanced Intel Speedstep Technology request from processor cores; When 1, disables hardware coordination of Enhanced Intel Speedstep Technology requests.

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::EnergyPerformanceBiasEnable

[Bit 1] Thread. Energy/Performance Bias Enable (R/W) This bit makes the IA32_ENERGY_PERF_BIAS register (MSR 1B0h) visible to software with Ring 0 privileges. This bit's status (1 or 0) is also reflected by CPUID.(EAX=06h):ECX[3].

UINT32 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_MISC_PWR_MGMT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PEBS_ENABLE_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 PEBS_EN_PMC0:1
UINT32 PEBS_EN_PMC1:1
UINT32 PEBS_EN_PMC2:1
UINT32 PEBS_EN_PMC3:1
UINT32 Reserved1:28
UINT32 LL_EN_PMC0:1
UINT32 LL_EN_PMC1:1
UINT32 LL_EN_PMC2:1
UINT32 LL_EN_PMC3:1
UINT32 Reserved2:28
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PEBS_ENABLE

Field Documentation

struct { ... } MSR_NEHALEM_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::LL_EN_PMC0

[Bit 32] Enable Load Latency on IA32_PMC0. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::LL_EN_PMC1

[Bit 33] Enable Load Latency on IA32_PMC1. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::LL_EN_PMC2

[Bit 34] Enable Load Latency on IA32_PMC2. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::LL_EN_PMC3

[Bit 35] Enable Load Latency on IA32_PMC3. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::PEBS_EN_PMC0

[Bit 0] Enable PEBS on IA32_PMC0. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::PEBS_EN_PMC1

[Bit 1] Enable PEBS on IA32_PMC1. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::PEBS_EN_PMC2

[Bit 2] Enable PEBS on IA32_PMC2. (R/W).

UINT32 MSR_NEHALEM_PEBS_ENABLE_REGISTER::PEBS_EN_PMC3

[Bit 3] Enable PEBS on IA32_PMC3. (R/W).

UINT64 MSR_NEHALEM_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PEBS_LD_LAT_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PEBS_LD_LAT_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 MinimumThreshold:16
UINT32 Reserved1:16
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PEBS_LD_LAT

Field Documentation

struct { ... } MSR_NEHALEM_PEBS_LD_LAT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PEBS_LD_LAT_REGISTER::MinimumThreshold

[Bits 15:0] Minimum threshold latency value of tagged load operation that will be counted. (R/W).

UINT32 MSR_NEHALEM_PEBS_LD_LAT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_PEBS_LD_LAT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:29
UINT32 Ovf_Uncore:1
UINT32 Reserved3:2
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL

Field Documentation

struct { ... } MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_Uncore

[Bit 61] CLR_UNC_Ovf Set 1 to clear UNC_Ovf.

UINT64 MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:29
UINT32 Ovf_Uncore:1
UINT32 Reserved3:2
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PERF_GLOBAL_STATUS

Field Documentation

struct { ... } MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER::Ovf_Uncore

[Bit 61] UNC_Ovf Uncore overflowed if 1.

UINT64 MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:8
UINT32 InterruptFiltering:1
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 CStateDemotion:1
UINT32 CStateUndemotion:1
UINT32 Reserved4:1
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 state auto demotion enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information.

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 Undemotion (R/W).

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 state auto demotion enable (R/W) When set, the processor will conditionally demote C6/C7 requests to C3 based on uncore auto-demote information.

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 Undemotion (R/W).

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register until next reset.

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::CStateDemotion

[Bit 29] Package C State Demotion Enable (R/W).

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::CStateUndemotion

[Bit 30] Package C State UnDemotion Enable (R/W).

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::InterruptFiltering

[Bit 24] Interrupt filtering enable (R/W) When set, processor cores in a deep C-State will wake only when the event message is destined for that core. When 0, all processor cores in a deep C-State will wake for an event message.

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power). for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) 010b: C3 011b: C6 100b: C7 101b and 110b: Reserved 111: No package C-state limit. Note: This field cannot be used to limit package C-state to C3.

UINT32 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PLATFORM_ID_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PLATFORM_ID_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:18
UINT32 PlatformId:3
UINT32 Reserved3:11
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_ID

Field Documentation

struct { ... } MSR_NEHALEM_PLATFORM_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PLATFORM_ID_REGISTER::PlatformId

[Bits 52:50] See Table 2-2.

UINT64 MSR_NEHALEM_PLATFORM_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PLATFORM_INFO_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:12
UINT32 RatioLimit:1
UINT32 TDC_TDPLimit:1
UINT32 Reserved3:2
UINT32 Reserved4:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved5:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PLATFORM_INFO

Field Documentation

struct { ... } MSR_NEHALEM_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 133.33MHz.

UINT32 MSR_NEHALEM_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. The invariant TSC frequency can be computed by multiplying this ratio by 133.33 MHz.

UINT32 MSR_NEHALEM_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_NEHALEM_PLATFORM_INFO_REGISTER::TDC_TDPLimit

[Bit 29] Package. Programmable TDC-TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDC/TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDC and TDP Limits for Turbo mode are not programmable.

UINT64 MSR_NEHALEM_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

Data Fields
MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Lvl2Base:16
UINT32 CStateRange:3
UINT32 Reserved1:13
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_PMG_IO_CAPTURE_BASE

Field Documentation

struct { ... } MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER::CStateRange

[Bits 18:16] C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 is the max C-State to include 001b - C6 is the max C-State to include 010b - C7 is the max C-State to include.

UINT32 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER::Lvl2Base

[Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software.

UINT32 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_POWER_CTL_REGISTER Union Reference

Data Fields
MSR_NEHALEM_POWER_CTL_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 C1EEnable:1
UINT32 Reserved2:30
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_POWER_CTL

Field Documentation

struct { ... } MSR_NEHALEM_POWER_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_POWER_CTL_REGISTER::C1EEnable

[Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1).

UINT32 MSR_NEHALEM_POWER_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_POWER_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_SMI_COUNT_REGISTER Union Reference

Data Fields
MSR_NEHALEM_SMI_COUNT_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 SMICount:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_SMI_COUNT

Field Documentation

struct { ... } MSR_NEHALEM_SMI_COUNT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_SMI_COUNT_REGISTER::SMICount

[Bits 31:0] SMI Count (R/O) Running count of SMI events since last RESET.

UINT32 MSR_NEHALEM_SMI_COUNT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_SMI_COUNT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 Reserved2:8
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (R) The minimum temperature at which PROCHOT# will be asserted. The value is degree C.

UINT32 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Union Reference

Data Fields
MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 TDPLimit:15
UINT32 TDPLimitOverrideEnable:1
UINT32 TDCLimit:15
UINT32 TDCLimitOverrideEnable:1
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT

Field Documentation

struct { ... } MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::TDCLimit

[Bits 30:16] Package. TDC Limit (R/W) TDC limit in 1/8 Amp granularity.

UINT32 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::TDCLimitOverrideEnable

[Bit 31] Package. TDC Limit Override Enable (R/W) A value = 0 indicates override is not active, and a value = 1 indicates active.

UINT32 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::TDPLimit

[Bits 14:0] Package. TDP Limit (R/W) TDP limit in 1/8 Watt granularity.

UINT32 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::TDPLimitOverrideEnable

[Bit 15] Package. TDP Limit Override Enable (R/W) A value = 0 indicates override is not active, and a value = 1 indicates active.

UINT32 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <NehalemMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_NEHALEM_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_APIC_BASE_REGISTER Union Reference

Data Fields
MSR_P6_APIC_BASE_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 BSP:1
UINT32 Reserved2:2
UINT32 EN:1
UINT32 ApicBase:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_APIC_BASE

Field Documentation

UINT32 MSR_P6_APIC_BASE_REGISTER::ApicBase

[Bits 31:12] APIC Base Address.

struct { ... } MSR_P6_APIC_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_APIC_BASE_REGISTER::BSP

[Bit 8] Boot Strap Processor indicator Bit 1 = BSP.

UINT32 MSR_P6_APIC_BASE_REGISTER::EN

[Bit 11] APIC Global Enable Bit - Permanent till reset 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_APIC_BASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_APIC_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_BBL_CR_ADDR_REGISTER Union Reference

Data Fields
MSR_P6_BBL_CR_ADDR_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 Reserved1:3
UINT32 Address:29
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_BBL_CR_ADDR

Field Documentation

UINT32 MSR_P6_BBL_CR_ADDR_REGISTER::Address

[Bits 31:3] Address bits

struct { ... } MSR_P6_BBL_CR_ADDR_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_BBL_CR_ADDR_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_BBL_CR_ADDR_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_BBL_CR_CTL3_REGISTER Union Reference

Data Fields
MSR_P6_BBL_CR_CTL3_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 L2Configured:1
UINT32 L2CacheLatency:4
UINT32 ECCCheckEnable:1
UINT32 AddressParityCheckEnable:1
UINT32 CRTNParityCheckEnable:1
UINT32 L2Enabled:1
UINT32 L2Associativity:2
UINT32 L2Banks:2
UINT32 CacheSizePerBank:5
UINT32 CacheStateErrorEnable:1
UINT32 Reserved1:1
UINT32 L2AddressRange:3
UINT32 L2HardwareDisable:1
UINT32 Reserved2:1
UINT32 CacheBusFraction:1
UINT32 Reserved3:6
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_BBL_CR_CTL3

Field Documentation

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::AddressParityCheckEnable

[Bit 6] Address Parity Check Enable (read/write).

struct { ... } MSR_P6_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::CacheBusFraction

[Bit 25] Cache bus fraction (read only).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::CacheSizePerBank

[Bits 17:13] Cache size per bank (read/write) 256KBytes 512KBytes 1MByte 2MByte 4MBytes.

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::CacheStateErrorEnable

[Bit 18] Cache State error checking enable (read/write).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::CRTNParityCheckEnable

[Bit 7] CRTN Parity Check Enable (read/write).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::ECCCheckEnable

[Bit 5] ECC Check Enable (read/write).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2AddressRange

[Bits 22:20] L2 Physical Address Range support 64GBytes 32GBytes 16GBytes 8GBytes 4GBytes 2GBytes 1GBytes 512MBytes.

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2Associativity

[Bits 10:9] L2 Associativity (read only) Direct Mapped 2 Way 4 Way Reserved.

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2Banks

[Bits 12:11] Number of L2 banks (read only).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2CacheLatency

[Bits 4:1] L2 Cache Latency (read/write).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2Configured

[Bit 0] L2 Configured (read/write ).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled (read/write).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::L2HardwareDisable

[Bit 23] L2 Hardware Disable (read only).

UINT32 MSR_P6_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_BBL_CR_CTL_REGISTER Union Reference

Data Fields
MSR_P6_BBL_CR_CTL_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 L2Command:5
UINT32 StateToL2:2
UINT32 Reserved:1
UINT32 WayToL2:2
UINT32 Way:2
UINT32 MESI:2
UINT32 StateFromL2:2
UINT32 Reserved2:1
UINT32 L2Hit:1
UINT32 Reserved3:1
UINT32 UserEcc:2
UINT32 ProcessorNumber:1
UINT32 Reserved4:10
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_BBL_CR_CTL

Field Documentation

struct { ... } MSR_P6_BBL_CR_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::L2Command

[Bits 4:0] L2 Command Data Read w/ LRU update (RLU) Tag Read w/ Data Read (TRR) Tag Inquire (TI) L2 Control Register Read (CR) L2 Control Register Write (CW) Tag Write w/ Data Read (TWR) Tag Write w/ Data Write (TWW) Tag Write (TW).

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::L2Hit

[Bit 17] L2 Hit.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::MESI

[Bits 13:12] Modified - 11,Exclusive - 10, Shared - 01, Invalid - 00.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::ProcessorNumber

[Bit 21] Processor number Disable = 1 Enable = 0 Reserved.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::StateFromL2

[Bits 15:14] State from L2.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::StateToL2

[Bits 6:5] State to L2

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_BBL_CR_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::UserEcc

[Bits 20:19] User supplied ECC.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::Way

[Bits 11:10] Way 0 - 00, Way 1 - 01, Way 2 - 10, Way 3 - 11.

UINT32 MSR_P6_BBL_CR_CTL_REGISTER::WayToL2

[Bits 9:8] Way to L2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_DEBUGCTLMSR_REGISTER Union Reference

Data Fields
MSR_P6_DEBUGCTLMSR_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 LBR:1
UINT32 BTF:1
UINT32 PB0:1
UINT32 PB1:1
UINT32 PB2:1
UINT32 PB3:1
UINT32 TR:1
UINT32 Reserved1:25
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_DEBUGCTLMSR

Field Documentation

struct { ... } MSR_P6_DEBUGCTLMSR_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::BTF

[Bit 1] Branch Trap Flag.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::LBR

[Bit 0] Enable/Disable Last Branch Records.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::PB0

[Bit 2] Performance Monitoring/Break Point Pins.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::PB1

[Bit 3] Performance Monitoring/Break Point Pins.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::PB2

[Bit 4] Performance Monitoring/Break Point Pins.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::PB3

[Bit 5] Performance Monitoring/Break Point Pins.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::TR

[Bit 6] Enable/Disable Execution Trace Messages.

UINT32 MSR_P6_DEBUGCTLMSR_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_DEBUGCTLMSR_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
MSR_P6_EBL_CR_POWERON_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 DataErrorCheckingEnable:1
UINT32 ResponseErrorCheckingEnable:1
UINT32 AERR_DriveEnable:1
UINT32 BERR_Enable:1
UINT32 Reserved2:1
UINT32 BERR_DriverEnable:1
UINT32 BINIT_DriverEnable:1
UINT32 OutputTriStateEnable:1
UINT32 ExecuteBIST:1
UINT32 AERR_ObservationEnabled:1
UINT32 Reserved3:1
UINT32 BINIT_ObservationEnabled:1
UINT32 InOrderQueueDepth:1
UINT32 ResetVector:1
UINT32 FRCModeEnable:1
UINT32 APICClusterID:2
UINT32 SystemBusFrequency:2
UINT32 SymmetricArbitrationID:2
UINT32 ClockFrequencyRatio:4
UINT32 LowPowerModeEnable:1
UINT32 ClockFrequencyRatio1:1
UINT32 Reserved4:4
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_EBL_CR_POWERON

Field Documentation

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::AERR_DriveEnable

[Bit 3] AERR# Drive Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::AERR_ObservationEnabled

[Bit 10] AERR# Observation Enabled (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BERR_DriverEnable

[Bit 6] BERR# Driver Enable for Initiator Internal Errors (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BERR_Enable

[Bit 4] BERR# Enable for Initiator Bus Requests (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R) 1 = Enabled 0 = Disabled.

struct { ... } MSR_P6_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio

[Bits 25:22] Clock Frequency Ratio (R).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio1

[Bit 27] Clock Frequency Ratio.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::FRCModeEnable

[Bit 15] FRC Mode Enable (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::InOrderQueueDepth

[Bit 13] In Order Queue Depth (R) 1 = 1 0 = 8.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::LowPowerModeEnable

[Bit 26] Low Power Mode Enable (R/W).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::OutputTriStateEnable

[Bit 8] Output Tri-state Enabled (R) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1-MByte Power on Reset Vector (R) 1 = 1MByte 0 = 4GBytes.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable FRCERR Observation Enable (R/W) 1 = Enabled 0 = Disabled.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R).

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::SystemBusFrequency

[Bits 19:18] System Bus Frequency (R) 00 = 66MHz 10 = 100Mhz 01 = 133MHz 11 = Reserved.

UINT32 MSR_P6_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_IA32_PLATFORM_ID_REGISTER Union Reference

Data Fields
MSR_P6_IA32_PLATFORM_ID_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:18
UINT32 PlatformId:3
UINT32 L2CacheLatencyRead:4
UINT32 Reserved3:3
UINT32 ClockFrequencyRatioRead:1
UINT32 Reserved4:3
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_IA32_PLATFORM_ID

Field Documentation

struct { ... } MSR_P6_IA32_PLATFORM_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_IA32_PLATFORM_ID_REGISTER::ClockFrequencyRatioRead

[Bit 60] Clock Frequency Ratio Read.

UINT32 MSR_P6_IA32_PLATFORM_ID_REGISTER::L2CacheLatencyRead

[Bits 56:53] L2 Cache Latency Read.

UINT32 MSR_P6_IA32_PLATFORM_ID_REGISTER::PlatformId

[Bits 52:50] Platform Id (R) Contains information concerning the intended platform for the processor.

52 51 50 0 0 0 Processor Flag 0. 0 0 1 Processor Flag 1 0 1 0 Processor Flag 2 0 1 1 Processor Flag 3 1 0 0 Processor Flag 4 1 0 1 Processor Flag 5 1 1 0 Processor Flag 6 1 1 1 Processor Flag 7

UINT64 MSR_P6_IA32_PLATFORM_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_MC_STATUS_REGISTER Union Reference

Data Fields
MSR_P6_MC_STATUS_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 MC_STATUS_MCACOD:16
UINT32 MC_STATUS_MSCOD:16
UINT32 Reserved:25
UINT32 MC_STATUS_DAM:1
UINT32 MC_STATUS_ADDRV:1
UINT32 MC_STATUS_MISCV:1
UINT32 MC_STATUS_EN:1
UINT32 MC_STATUS_UC:1
UINT32 MC_STATUS_O:1
UINT32 MC_STATUS_V:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_MC0_STATUS to #MSR_P6_MC4_STATUS

Field Documentation

struct { ... } MSR_P6_MC_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_ADDRV

[Bit 58] MC_STATUS_ADDRV.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_DAM

[Bit 57] MC_STATUS_DAM.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_EN

[Bit 60] MC_STATUS_EN. (Note: For MC0_STATUS only, this bit is hardcoded to 1.).

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_MCACOD

[Bits 15:0] MC_STATUS_MCACOD.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_MISCV

[Bit 59] MC_STATUS_MISCV.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_MSCOD

[Bits 31:16] MC_STATUS_MSCOD.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_O

[Bit 62] MC_STATUS_O.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_UC

[Bit 61] MC_STATUS_UC.

UINT32 MSR_P6_MC_STATUS_REGISTER::MC_STATUS_V

[Bit 63] MC_STATUS_V.

UINT64 MSR_P6_MC_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_MTRRDEFTYPE_REGISTER Union Reference

Data Fields
MSR_P6_MTRRDEFTYPE_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 Type:3
UINT32 Reserved1:7
UINT32 FE:1
UINT32 E:1
UINT32 Reserved2:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_MTRRDEFTYPE

Field Documentation

struct { ... } MSR_P6_MTRRDEFTYPE_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_MTRRDEFTYPE_REGISTER::E

[Bit 11] MTRR Enable.

UINT32 MSR_P6_MTRRDEFTYPE_REGISTER::FE

[Bit 10] Fixed MTRR enable.

UINT32 MSR_P6_MTRRDEFTYPE_REGISTER::Type

[Bits 2:0] Default memory type.

UINT32 MSR_P6_MTRRDEFTYPE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_MTRRDEFTYPE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_PERFEVTSEL_REGISTER Union Reference

Data Fields
MSR_P6_PERFEVTSEL_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 EventSelect:8
UINT32 UMASK:8
UINT32 USR:1
UINT32 OS:1
UINT32 E:1
UINT32 PC:1
UINT32 INT:1
UINT32 Reserved1:1
UINT32 EN:1
UINT32 INV:1
UINT32 CMASK:8
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_P6_PERFEVTSEL0 and #MSR_P6_PERFEVTSEL1.

Field Documentation

struct { ... } MSR_P6_PERFEVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_PERFEVTSEL_REGISTER::CMASK

[Bits 31:24] CMASK (Counter Mask).

UINT32 MSR_P6_PERFEVTSEL_REGISTER::E

[Bit 18] E Occurrence/Duration Mode Select 1 = Occurrence 0 = Duration.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::EN

[Bit 22] ENABLE Enables the counting of performance events in both counters 1 = Enable 0 = Disable.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::EventSelect

[Bits 7:0] Event Select Refer to Performance Counter section for a list of event encodings.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::INT

[Bit 20] INT Enables the signaling of counter overflow via input to APIC 1 = Enable 0 = Disable.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::INV

[Bit 23] INV Inverts the result of the CMASK condition 1 = Inverted 0 = Non-Inverted.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::OS

[Bit 17] OS Controls the counting of events at Privilege level of 0.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::PC

[Bit 19] PC Enabled the signaling of performance counter overflow via BP0 pin.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_PERFEVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_P6_PERFEVTSEL_REGISTER::UMASK

[Bits 15:8] UMASK (Unit Mask) Unit mask register set to 0 to enable all count options.

UINT32 MSR_P6_PERFEVTSEL_REGISTER::USR

[Bit 16] USER Controls the counting of events at Privilege levels of 1, 2, and 3.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_P6_TEST_CTL_REGISTER Union Reference

Data Fields
MSR_P6_TEST_CTL_REGISTER Union Reference

#include <P6Msr.h>

Data Fields

struct {
UINT32 Reserved1:30
UINT32 StreamingBufferDisable:1
UINT32 Disable_LOCK:1
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_P6_TEST_CTL

Field Documentation

struct { ... } MSR_P6_TEST_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_P6_TEST_CTL_REGISTER::Disable_LOCK

[Bit 31] Disable LOCK# Assertion for split locked access.

UINT32 MSR_P6_TEST_CTL_REGISTER::StreamingBufferDisable

[Bit 30] Streaming Buffer Disable.

UINT32 MSR_P6_TEST_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_P6_TEST_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/P6Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 Reserved1:21
UINT32 ScalableBusSpeed:3
UINT32 Reserved2:8
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID_1

Field Documentation

struct { ... } MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER::ScalableBusSpeed

[Bits 23:21] Scalable Bus Speed (R/W) Indicates the intended scalable bus speed: Encoding Scalable Bus Speed

000B 100 MHz All others values reserved.

UINT32 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 ScalableBusSpeed:3
UINT32 Reserved2:5
UINT32 ClockRatio:8
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_EBC_FREQUENCY_ID

Field Documentation

struct { ... } MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER::ClockRatio

[Bits 31:24] Core Clock Frequency to System Bus Frequency Ratio (R) The processor core clock frequency to system bus frequency ratio observed at the de-assertion of the reset pin.

UINT32 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER::ScalableBusSpeed

[Bits 18:16] Scalable Bus Speed (R/W) Indicates the intended scalable bus speed: EncodingScalable Bus Speed

000B 100 MHz (Model 2). 000B 266 MHz (Model 3 or 4) 001B 133 MHz 010B 200 MHz 011B 166 MHz 100B 333 MHz (Model 6)

133.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 001B. 166.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 011B. 266.67 MHz should be utilized if performing calculation with System Bus Speed when encoding is 000B and model encoding = 3 or 4. 333.33 MHz should be utilized if performing calculation with System Bus Speed when encoding is 100B and model encoding = 6. All other values are reserved.

UINT32 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 OutputTriStateEnabled:1
UINT32 ExecuteBIST:1
UINT32 InOrderQueueDepth:1
UINT32 MCERR_ObservationDisabled:1
UINT32 BINIT_ObservationEnabled:1
UINT32 APICClusterID:2
UINT32 BusParkDisable:1
UINT32 Reserved1:4
UINT32 AgentID:2
UINT32 Reserved2:18
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_EBC_HARD_POWERON

Field Documentation

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::AgentID

[Bits 13:12] Agent ID (R) Contains the logical agent ID value as set by the strapping of BR[3:0]. The logical ID value is written into the field on the deassertion of RESET#; the field is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::APICClusterID

[Bits 6:5] APIC Cluster ID (R) Contains the logical APIC cluster ID value as set by the strapping of A12# and A11#. The logical cluster ID value is written into the field on the deassertion of RESET#; the field is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 4] BINIT# Observation Enabled (R) Indicates whether BINIT# observation is enabled (0) or disabled (1) as determined by the strapping of A10#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

struct { ... } MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::BusParkDisable

[Bit 7] Bus Park Disable (R) Indicates whether bus park is enabled (0) or disabled (1) as set by the strapping of A15#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::ExecuteBIST

[Bit 1] Execute BIST (R) Indicates whether the execution of the BIST is enabled (1) or disabled (0) as set by the strapping of INIT#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::InOrderQueueDepth

[Bit 2] In Order Queue Depth (R) Indicates whether the in order queue depth for the system bus is 1 (1) or up to 12 (0) as set by the strapping of A7#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::MCERR_ObservationDisabled

[Bit 3] MCERR# Observation Disabled (R) Indicates whether MCERR# observation is enabled (0) or disabled (1) as determined by the strapping of A9#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::OutputTriStateEnabled

[Bit 0] Output Tri-state Enabled (R) Indicates whether tri-state output is enabled (1) or disabled (0) as set by the strapping of SMI#. The value in this bit is written on the deassertion of RESET#; the bit is set to 1 when the address bus signal is asserted.

UINT32 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 RCNT_SCNT:1
UINT32 DataErrorCheckingDisable:1
UINT32 ResponseErrorCheckingDisable:1
UINT32 AddressRequestErrorCheckingDisable:1
UINT32 InitiatorMCERR_Disable:1
UINT32 InternalMCERR_Disable:1
UINT32 BINIT_DriverDisable:1
UINT32 Reserved1:25
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_EBC_SOFT_POWERON

Field Documentation

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::AddressRequestErrorCheckingDisable

[Bit 3] Address/Request Error Checking Disable (R/W) Set to disable (default); clear to enable.

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::BINIT_DriverDisable

[Bit 6] BINIT# Driver Disable (R/W) Set to disable BINIT# driver (default); clear to enable driver.

struct { ... } MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::DataErrorCheckingDisable

[Bit 1] Data Error Checking Disable (R/W) Set to disable system data bus parity checking; clear to enable parity checking.

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::InitiatorMCERR_Disable

[Bit 4] Initiator MCERR# Disable (R/W) Set to disable MCERR# driving for initiator bus requests (default); clear to enable.

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::InternalMCERR_Disable

[Bit 5] Internal MCERR# Disable (R/W) Set to disable MCERR# driving for initiator internal errors (default); clear to enable.

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::RCNT_SCNT

[Bit 0] RCNT/SCNT On Request Encoding Enable (R/W) Controls the driving of RCNT/SCNT on the request encoding. Set to enable (1); clear to disabled (0, default).

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::ResponseErrorCheckingDisable

[Bit 2] Response Error Checking Disable (R/W) Set to disable (default); clear to enable.

UINT32 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:1
UINT32 FPU:1
UINT32 TM1:1
UINT32 SplitLockDisable:1
UINT32 Reserved2:1
UINT32 ThirdLevelCacheDisable:1
UINT32 PerformanceMonitoring:1
UINT32 SuppressLockEnable:1
UINT32 PrefetchQueueDisable:1
UINT32 FERR:1
UINT32 BTS:1
UINT32 PEBS:1
UINT32 TM2:1
UINT32 Reserved3:4
UINT32 MONITOR:1
UINT32 AdjacentCacheLinePrefetchDisable:1
UINT32 Reserved4:2
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 L1DataCacheContextMode:1
UINT32 Reserved5:7
UINT32 Reserved6:2
UINT32 XD:1
UINT32 Reserved7:29
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::AdjacentCacheLinePrefetchDisable

[Bit 19] Adjacent Cache Line Prefetch Disable (R/W) When set to 1, the processor fetches the cache line of the 128-byte sector containing currently required data. When set to 0, the processor fetches both cache lines in the sector. Single processor platforms should not set this bit. Server platforms should set or clear this bit based on platform performance observed in validation and testing. BIOS may contain a setup option that controls the setting of this bit.

struct { ... } MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (BTS_UNAVILABLE) (R) See Table 2-2. When set, the processor does not support branch trace storage (BTS); when clear, BTS is supported.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable. See Table 2-2.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::FERR

[Bit 10] FERR# Interrupt Reporting Enable (R/W) When set, interrupt reporting through the FERR# pin is enabled; when clear, this interrupt reporting function is disabled. When this flag is set and the processor is in the stop-clock state (STPCLK# is asserted), asserting the FERR# pin signals to the processor that an interrupt (such as, INIT#, BINIT#, INTR, NMI, SMI#, or RESET#) is pending and that the processor should return to normal operation to handle the interrupt. This flag does not affect the normal operation of the FERR# pin (to indicate an unmasked floatingpoint error) when the STPCLK# pin is not asserted.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::FPU

[Bit 2] x87 FPU Fopcode Compatibility Mode Enable.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::L1DataCacheContextMode

[Bit 24] L1 Data Cache Context Mode (R/W) When set, the L1 data cache is placed in shared mode; when clear (default), the cache is placed in adaptive mode. This bit is only enabled for IA-32 processors that support Intel Hyper-Threading Technology. See Section 11.5.6, "L1 Data Cache Context Mode." When L1 is running in adaptive mode and CR3s are identical, data in L1 is shared across logical processors. Otherwise, L1 is not shared and cache use is competitive. If the Context ID feature flag (ECX[10]) is set to 0 after executing CPUID with EAX = 1, the ability to switch modes is not supported. BIOS must not alter the contents of IA32_MISC_ENABLE[24].

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] 3, 4, 6. Limit CPUID MAXVAL (R/W) See Table 2-2. Setting this can cause unexpected behavior to software that depends on the availability of CPUID leaves greater than 3.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] 3, 4, 6. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] PEBS_UNAVILABLE: Processor Event Based Sampling Unavailable (R) See Table 2-2. When set, the processor does not support processor event-based sampling (PEBS); when clear, PEBS is supported.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::PrefetchQueueDisable

[Bit 9] Prefetch Queue Disable When set, disables the prefetch queue. When clear (default), enables the prefetch queue.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::SplitLockDisable

[Bit 4] Split-Lock Disable When set, the bit causes an #AC exception to be issued instead of a split-lock cycle. Operating systems that set this bit must align system structures to avoid split-lock scenarios. When the bit is clear (default), normal split-locks are issued to the bus. This debug feature is specific to the Pentium 4 processor.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::SuppressLockEnable

[Bit 8] Suppress Lock Enable When set, assertion of LOCK on the bus is suppressed during a Split Lock access. When clear (default), LOCK is not suppressed.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::ThirdLevelCacheDisable

[Bit 6] Third-Level Cache Disable (R/W) When set, the third-level cache is disabled; when clear (default) the third-level cache is enabled. This flag is reserved for processors that do not have a third-level cache. Note that the bit controls only the third-level cache; and only if overall caching is enabled through the CD flag of control register CR0, the page-level cache controls, and/or the MTRRs. See Section 11.5.4, "Disabling and Enabling the L3 Cache.".

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::TM1

[Bit 3] Thermal Monitor 1 Enable See Section 14.7.2, "Thermal Monitor," and see Table 2-2.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::TM2

[Bit 13] 3. TM2 Enable (R/W) When this bit is set (1) and the thermal sensor indicates that the die temperature is at the predetermined threshold, the Thermal Monitor 2 mechanism is engaged. TM2 will reduce the bus to core ratio and voltage according to the value last written to MSR_THERM2_CTL bits 15:0. When this bit is clear (0, default), the processor does not change the VID signals or the bus to core ratio when the processor enters a thermal managed state. If the TM2 feature flag (ECX[8]) is not set to 1 after executing CPUID with EAX = 1, then this feature is not supported and BIOS must not alter the contents of this bit location. The processor is operating out of spec if both this bit and the TM1 bit are set to disabled states.

UINT64 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Unique. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Shared. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_MCG_MISC_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_MCG_MISC_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 DS:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_MCG_MISC

Field Documentation

struct { ... } MSR_PENTIUM_4_MCG_MISC_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_MCG_MISC_REGISTER::DS

[Bit 0] DS When set, the bit indicates that a page assist or page fault occurred during DS normal operation. The processors response is to shut down. The bit is used as an aid for debugging DS handling code. It is the responsibility of the user (BIOS or operating system) to clear this bit for normal operation.

UINT32 MSR_PENTIUM_4_MCG_MISC_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_MCG_MISC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_PEBS_ENABLE_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 EventNum:13
UINT32 Reserved1:11
UINT32 UOP:1
UINT32 ENABLE_PEBS_MY_THR:1
UINT32 ENABLE_PEBS_OTH_THR:1
UINT32 Reserved2:5
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_PEBS_ENABLE

Field Documentation

struct { ... } MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::ENABLE_PEBS_MY_THR

[Bit 25] ENABLE_PEBS_MY_THR (R/W) Enables PEBS for the target logical processor when set; disables PEBS when clear (default). See Section 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target logical processor. This bit is called ENABLE_PEBS in IA-32 processors that do not support Intel HyperThreading Technology.

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::ENABLE_PEBS_OTH_THR

[Bit 26] ENABLE_PEBS_OTH_THR (R/W) Enables PEBS for the target logical processor when set; disables PEBS when clear (default). See Section 18.6.4.3, "IA32_PEBS_ENABLE MSR," for an explanation of the target logical processor. This bit is reserved for IA-32 processors that do not support Intel Hyper-Threading Technology.

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::EventNum

[Bits 12:0] See Table 19-36.

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_PENTIUM_4_PEBS_ENABLE_REGISTER::UOP

[Bit 24] UOP Tag Enables replay tagging when set.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Union Reference

Data Fields
MSR_PENTIUM_4_PLATFORM_BRV_REGISTER Union Reference

#include <Pentium4Msr.h>

Data Fields

struct {
UINT32 Reserved1:18
UINT32 PLATFORM:1
UINT32 Reserved2:13
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_4_PLATFORM_BRV

Field Documentation

struct { ... } MSR_PENTIUM_4_PLATFORM_BRV_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER::PLATFORM

[Bit 18] PLATFORM Requirements When set to 1, indicates the processor has specific platform requirements. The details of the platform requirements are listed in the respective data sheets of the processor.

UINT32 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_4_PLATFORM_BRV_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Union Reference

Data Fields
MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER Union Reference

#include <PentiumMMsr.h>

Data Fields

struct {
UINT32 L2HardwareEnabled:1
UINT32 Reserved1:4
UINT32 ECCCheckEnable:1
UINT32 Reserved2:2
UINT32 L2Enabled:1
UINT32 Reserved3:14
UINT32 L2NotPresent:1
UINT32 Reserved4:8
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_M_BBL_CR_CTL3

Field Documentation

struct { ... } MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::ECCCheckEnable

[Bit 5] ECC Check Enable (RO) This bit enables ECC checking on the cache data bus. ECC is always generated on write cycles. 1. = Disabled (default) 2. = Enabled For the Pentium M processor, ECC checking on the cache data bus is always enabled.

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input.

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::L2HardwareEnabled

[Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = Indicates if the L2 is hardware-disabled.

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::L2NotPresent

[Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.

UINT32 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER Union Reference

#include <PentiumMMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 DataErrorCheckingEnable:1
UINT32 ResponseErrorCheckingEnable:1
UINT32 MCERR_DriveEnable:1
UINT32 AddressParityEnable:1
UINT32 Reserved2:2
UINT32 BINIT_DriverEnable:1
UINT32 OutputTriStateEnable:1
UINT32 ExecuteBIST:1
UINT32 MCERR_ObservationEnabled:1
UINT32 Reserved3:1
UINT32 BINIT_ObservationEnabled:1
UINT32 Reserved4:1
UINT32 ResetVector:1
UINT32 Reserved5:1
UINT32 APICClusterID:2
UINT32 SystemBusFrequency:1
UINT32 Reserved6:1
UINT32 SymmetricArbitrationID:2
UINT32 ClockFrequencyRatio:5
UINT32 Reserved7:5
UINT32 Reserved8:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_M_EBL_CR_POWERON

Field Documentation

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::AddressParityEnable

[Bit 4] Address Parity Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::APICClusterID

[Bits 17:16] APIC Cluster ID (R/O) Always 00B on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::BINIT_DriverEnable

[Bit 7] BINIT# Driver Enable (R) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::BINIT_ObservationEnabled

[Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor.

struct { ... } MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ClockFrequencyRatio

[Bits 26:22] Clock Frequency Ratio (R/O).

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::DataErrorCheckingEnable

[Bit 1] Data Error Checking Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ExecuteBIST

[Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::MCERR_DriveEnable

[Bit 3] MCERR# Drive Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::MCERR_ObservationEnabled

[Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::OutputTriStateEnable

[Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ResetVector

[Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::ResponseErrorCheckingEnable

[Bit 2] Response Error Checking Enable (R) 0 = Disabled Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::SymmetricArbitrationID

[Bits 21:20] Symmetric Arbitration ID (R/O) Always 00B on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::SystemBusFrequency

[Bit 18] System Bus Frequency (R/O) 1. = 100 MHz 2. = Reserved Always 0 on the Pentium M processor.

UINT32 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER Union Reference

#include <PentiumMMsr.h>

Data Fields

struct {
UINT32 Reserved1:3
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:2
UINT32 FERR:1
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved5:3
UINT32 EIST:1
UINT32 Reserved6:6
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_M_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Automatic Thermal Control Circuit Enable (R/W) 1 = Setting this bit enables the thermal control circuit (TCC) portion of the Intel Thermal Monitor feature. This allows processor clocks to be automatically modulated based on the processor's thermal sensor operation. 0 = Disabled (default). The automatic thermal control circuit enable bit determines if the thermal control circuit (TCC) will be activated when the processor's internal thermal sensor determines the processor is about to exceed its maximum operating temperature. When the TCC is activated and TM1 is enabled, the processors clocks will be forced to a 50% duty cycle. BIOS must enable this feature. The bit should not be confused with the on-demand thermal control circuit enable bit.

struct { ... } MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W) 1 = Enhanced Intel SpeedStep Technology enabled. On the Pentium M processor, this bit may be configured to be read-only.

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::FERR

[Bit 10] FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by the processor to indicate a pending break event within the processor 0 = Indicates compatible FERR# signaling behavior This bit must be set to 1 to support XAPIC interrupt model usage. Branch Trace Storage Unavailable (RO) 1 = Processor doesn't support branch trace storage (BTS) 0 = BTS is supported

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Processor Event Based Sampling Unavailable (RO) 1 = Processor does not support processor event based sampling (PEBS); 0 = PEBS is supported. The Pentium M processor does not support PEBS.

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R) 1 = Performance monitoring enabled 0 = Performance monitoring disabled.

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] xTPR Message Disable (R/W) When set to 1, xTPR messages are disabled. xTPR messages are optional messages that allow the processor to inform the chipset of its priority. The default is processor specific.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_PENTIUM_M_THERM2_CTL_REGISTER Union Reference

Data Fields
MSR_PENTIUM_M_THERM2_CTL_REGISTER Union Reference

#include <PentiumMMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TM_SELECT:1
UINT32 Reserved2:15
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_PENTIUM_M_THERM2_CTL

Field Documentation

struct { ... } MSR_PENTIUM_M_THERM2_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_PENTIUM_M_THERM2_CTL_REGISTER::TM_SELECT

[Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. = Thermal Monitor 1 (thermally-initiated on-die modulation of the stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is cleared, TM_SELECT has no effect. Neither TM1 nor TM2 will be enabled.

UINT32 MSR_PENTIUM_M_THERM2_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_PENTIUM_M_THERM2_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 MemErrorLogEnable:1
UINT32 Reserved2:30
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER::MemErrorLogEnable

[Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank to log additional info in bits 36:32.

UINT32 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 AESConfiguration:2
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG

Field Documentation

UINT32 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

struct { ... } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 OnDemandClockModulationDutyCycle:4
UINT32 OnDemandClockModulationEnable:1
UINT32 Reserved1:27
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER::OnDemandClockModulationDutyCycle

[Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25% increment.

UINT32 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER::OnDemandClockModulationEnable

[Bit 4] On demand Clock Modulation Enable (R/W).

UINT32 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 PCUHardwareError:1
UINT32 PCUControllerError:1
UINT32 PCUFirmwareError:1
UINT32 Reserved1:29
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER::PCUControllerError

[Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU controller detected errors.

UINT32 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER::PCUFirmwareError

[Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU firmware detected errors.

UINT32 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER::PCUHardwareError

[Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU hardware detected errors.

UINT32 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:6
UINT32 PerformanceMonitoring:1
UINT32 Reserved2:3
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved3:3
UINT32 EIST:1
UINT32 Reserved4:1
UINT32 MONITOR:1
UINT32 Reserved5:3
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved6:8
UINT32 Reserved7:2
UINT32 XD:1
UINT32 Reserved8:3
UINT32 TurboModeDisable:1
UINT32 Reserved9:25
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Thread. Fast-Strings Enable See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

UINT64 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 PCM0_EN:1
UINT32 PCM1_EN:1
UINT32 PCM2_EN:1
UINT32 PCM3_EN:1
UINT32 PCM4_EN:1
UINT32 PCM5_EN:1
UINT32 PCM6_EN:1
UINT32 PCM7_EN:1
UINT32 Reserved1:24
UINT32 FIXED_CTR0:1
UINT32 FIXED_CTR1:1
UINT32 FIXED_CTR2:1
UINT32 Reserved2:29
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::FIXED_CTR0

[Bit 32] Thread. Set 1 to enable FixedCtr0 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::FIXED_CTR1

[Bit 33] Thread. Set 1 to enable FixedCtr1 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::FIXED_CTR2

[Bit 34] Thread. Set 1 to enable FixedCtr2 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM0_EN

[Bit 0] Thread. Set 1 to enable PMC0 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM1_EN

[Bit 1] Thread. Set 1 to enable PMC1 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM2_EN

[Bit 2] Thread. Set 1 to enable PMC2 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM3_EN

[Bit 3] Thread. Set 1 to enable PMC3 to count.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM4_EN

[Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM5_EN

[Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM6_EN

[Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::PCM7_EN

[Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] > 7).

UINT64 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Ovf_PMC4:1
UINT32 Ovf_PMC5:1
UINT32 Ovf_PMC6:1
UINT32 Ovf_PMC7:1
UINT32 Reserved1:24
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:26
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::CondChgd

[Bit 63] Thread. Set 1 to clear CondChgd.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC0

[Bit 0] Thread. Set 1 to clear Ovf_PMC0.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC1

[Bit 1] Thread. Set 1 to clear Ovf_PMC1.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC2

[Bit 2] Thread. Set 1 to clear Ovf_PMC2.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC3

[Bit 3] Thread. Set 1 to clear Ovf_PMC3.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC4

[Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC5

[Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC6

[Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_PMC7

[Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Ovf_Uncore

[Bit 61] Thread. Set 1 to clear Ovf_Uncore.

UINT64 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Ovf_PMC4:1
UINT32 Ovf_PMC5:1
UINT32 Ovf_PMC6:1
UINT32 Ovf_PMC7:1
UINT32 Reserved1:24
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:26
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::CondChgd

[Bit 63] Thread. CondChgd.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Ovf_BufDSSAVE.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Ovf_FixedCtr0.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Ovf_FixedCtr1.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Ovf_FixedCtr2.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC0

[Bit 0] Thread. Ovf_PMC0.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC1

[Bit 1] Thread. Ovf_PMC1.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC2

[Bit 2] Thread. Ovf_PMC2.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC3

[Bit 3] Thread. Ovf_PMC3.

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC4

[Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC5

[Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC6

[Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC7

[Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).

UINT32 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_Uncore

[Bit 61] Thread. Ovf_Uncore.

UINT64 MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 CPL_EQ_0:1
UINT32 CPL_NEQ_0:1
UINT32 JCC:1
UINT32 NEAR_REL_CALL:1
UINT32 NEAR_IND_CALL:1
UINT32 NEAR_RET:1
UINT32 NEAR_IND_JMP:1
UINT32 NEAR_REL_JMP:1
UINT32 FAR_BRANCH:1
UINT32 Reserved1:23
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::CPL_EQ_0

[Bit 0] CPL_EQ_0.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::CPL_NEQ_0

[Bit 1] CPL_NEQ_0.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::FAR_BRANCH

[Bit 8] FAR_BRANCH.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::JCC

[Bit 2] JCC.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::NEAR_IND_CALL

[Bit 4] NEAR_IND_CALL.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::NEAR_IND_JMP

[Bit 6] NEAR_IND_JMP.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::NEAR_REL_CALL

[Bit 3] NEAR_REL_CALL.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::NEAR_REL_JMP

[Bit 7] NEAR_REL_JMP.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::NEAR_RET

[Bit 5] NEAR_RET.

UINT32 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 L2HardwarePrefetcherDisable:1
UINT32 L2AdjacentCacheLinePrefetcherDisable:1
UINT32 DCUHardwarePrefetcherDisable:1
UINT32 DCUIPPrefetcherDisable:1
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache.

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::DCUIPPrefetcherDisable

[Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1 data cache IP prefetcher, which uses sequential load history (based on instruction Pointer of previous loads) to determine whether to prefetch additional lines.

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::L2AdjacentCacheLinePrefetcherDisable

[Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1, disables the adjacent cache line prefetcher, which fetches the cache line that comprises a cache line pair (128 bytes).

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache.

UINT32 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 PEBS_EN_PMC0:1
UINT32 PEBS_EN_PMC1:1
UINT32 PEBS_EN_PMC2:1
UINT32 PEBS_EN_PMC3:1
UINT32 Reserved1:28
UINT32 LL_EN_PMC0:1
UINT32 LL_EN_PMC1:1
UINT32 LL_EN_PMC2:1
UINT32 LL_EN_PMC3:1
UINT32 Reserved2:27
UINT32 PS_EN:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC0

[Bit 32] Enable Load Latency on IA32_PMC0. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC1

[Bit 33] Enable Load Latency on IA32_PMC1. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC2

[Bit 34] Enable Load Latency on IA32_PMC2. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::LL_EN_PMC3

[Bit 35] Enable Load Latency on IA32_PMC3. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC0

[Bit 0] Enable PEBS on IA32_PMC0. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC1

[Bit 1] Enable PEBS on IA32_PMC1. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC2

[Bit 2] Enable PEBS on IA32_PMC2. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PEBS_EN_PMC3

[Bit 3] Enable PEBS on IA32_PMC3. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::PS_EN

[Bit 63] Enable Precise Store. (R/W).

UINT64 MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 MinimumThreshold:16
UINT32 Reserved1:16
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER::MinimumThreshold

[Bits 15:0] Minimum threshold latency value of tagged load operation that will be counted. (R/W).

UINT32 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 ENABLE_PEBS_NUM_ALT:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER::ENABLE_PEBS_NUM_ALT

[Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS counting logic for specific events requiring additional configuration, see Table 19-17.

UINT32 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 CoreVoltage:16
UINT32 Reserved2:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER::CoreVoltage

[Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).

UINT64 MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:9
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 Reserved4:3
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 state auto demotion enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from demoted C1.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 state auto demotion enable (R/W) When set, the processor will conditionally demote C6/C7 requests to C3 based on uncore auto-demote information.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from demoted C3.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register until next reset.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power). for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b: C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note: This field cannot be used to limit package C-state to C3.

UINT32 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 TimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER::TimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C3 state.

UINT32 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. The following time unit encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 32768 ns 100b: 1048576 ns 101b: 33554432 ns.

UINT32 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 TimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER::TimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C6 state.

UINT32 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. The following time unit encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 32768 ns 100b: 1048576 ns 101b: 33554432 ns.

UINT32 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 TimeLimit:10
UINT32 TimeUnit:3
UINT32 Reserved1:2
UINT32 Valid:1
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER::TimeLimit

[Bits 9:0] Interrupt response time limit (R/W) Specifies the limit that should be used to decide if the package should be put into a package C7 state.

UINT32 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER::TimeUnit

[Bits 12:10] Time Unit (R/W) Specifies the encoding value of time unit of the interrupt response time limit. The following time unit encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b: 32768 ns 100b: 1048576 ns 101b: 33554432 ns.

UINT32 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER::Valid

[Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are valid and can be used by the processor for package C-sate management.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:12
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 Reserved3:2
UINT32 Reserved4:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved5:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT64 MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Lvl2Base:16
UINT32 CStateRange:3
UINT32 Reserved1:13
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER::CStateRange

[Bits 18:16] C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3 is the max C-State to include 001b - C6 is the max C-State to include 010b - C7 is the max C-State to include.

UINT32 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER::Lvl2Base

[Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software.

UINT32 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 SMICount:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER::SMICount

[Bits 31:0] SMI Count (R/O) Count SMIs.

UINT32 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 Reserved2:8
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (R) The minimum temperature at which PROCHOT# will be asserted. The value is degree C.

UINT32 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Maximum5C:8
UINT32 Maximum6C:8
UINT32 Maximum7C:8
UINT32 Maximum8C:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum7C

[Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio limit of 7 core active.

UINT32 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Maximum8C

[Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio limit of 8 core active.

UINT64 MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 CBox:4
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER::CBox

[Bits 3:0] Report the number of C-Box units with performance counters, including processor cores and processor graphics".

UINT32 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 CurrentCount:32
UINT32 CurrentCountHi:16
UINT32 Reserved:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER::CurrentCount

[Bits 31:0] Current count.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER::CurrentCountHi

[Bits 47:32] Current count.

UINT64 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Reserved1:20
UINT32 EnableOverflow:1
UINT32 Reserved2:1
UINT32 EnableCounting:1
UINT32 Reserved3:9
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER::EnableCounting

[Bit 22] Enable counting.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER::EnableOverflow

[Bit 20] Enable overflow propagation.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 PMI_Sel_Slice0:1
UINT32 PMI_Sel_Slice1:1
UINT32 PMI_Sel_Slice2:1
UINT32 PMI_Sel_Slice3:1
UINT32 PMI_Sel_Slice4:1
UINT32 Reserved1:14
UINT32 Reserved2:10
UINT32 EN:1
UINT32 WakePMI:1
UINT32 FREEZE:1
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL

Field Documentation

struct { ... } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::EN

[Bit 29] Enable all uncore counters.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::FREEZE

[Bit 31] Enable Freezing counter when overflow.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice0

[Bit 0] Slice 0 select.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice1

[Bit 1] Slice 1 select.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice2

[Bit 2] Slice 2 select.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice3

[Bit 3] Slice 3 select.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice4

[Bit 4] Slice 4 select.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER::WakePMI

[Bit 30] Enable wake on PMI.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <SandyBridgeMsr.h>

Data Fields

struct {
UINT32 Fixed:1
UINT32 ARB:1
UINT32 Reserved1:1
UINT32 CBox:1
UINT32 Reserved2:28
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS

Field Documentation

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER::ARB

[Bit 1] An ARB counter overflowed.

struct { ... } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER::CBox

[Bit 3] A CBox counter overflowed (on any slice).

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER::Fixed

[Bit 0] Fixed counter overflowed.

UINT32 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SEV_STATUS_REGISTER Union Reference

Data Fields
MSR_SEV_STATUS_REGISTER Union Reference

#include <Fam17Msr.h>

Data Fields

struct {
UINT32 SevBit:1
UINT32 SevEsBit:1
UINT32 Reserved:30
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for #MSR_SEV_STATUS

Field Documentation

struct { ... } MSR_SEV_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SEV_STATUS_REGISTER::SevBit

[Bit 0] Secure Encrypted Virtualization (Sev) is enabled

UINT32 MSR_SEV_STATUS_REGISTER::SevEsBit

[Bit 1] Secure Encrypted Virtualization Encrypted State (SevEs) is enabled

UINT32 MSR_SEV_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SEV_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Amd/Fam17Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_BBL_CR_CTL3_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 L2HardwareEnabled:1
UINT32 Reserved1:7
UINT32 L2Enabled:1
UINT32 Reserved2:14
UINT32 L2NotPresent:1
UINT32 Reserved3:8
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_BBL_CR_CTL3

Field Documentation

struct { ... } MSR_SILVERMONT_BBL_CR_CTL3_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER::L2Enabled

[Bit 8] L2 Enabled. (R/W) 1 = L2 cache has been initialized 0 = Disabled (default) Until this bit is set the processor will not respond to the WBINVD instruction or the assertion of the FLUSH# input.

UINT32 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER::L2HardwareEnabled

[Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 = Indicates if the L2 is hardware-disabled.

UINT32 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER::L2NotPresent

[Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.

UINT32 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_BBL_CR_CTL3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_EBL_CR_POWERON_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_EBL_CR_POWERON

Field Documentation

struct { ... } MSR_SILVERMONT_EBL_CR_POWERON_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_EBL_CR_POWERON_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_EBL_CR_POWERON_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_FEATURE_CONFIG_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 AESConfiguration:2
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_FEATURE_CONFIG

Field Documentation

UINT32 MSR_SILVERMONT_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

struct { ... } MSR_SILVERMONT_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_FSB_FREQ_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_FSB_FREQ_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 ScalableBusSpeed:4
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_FSB_FREQ

Field Documentation

struct { ... } MSR_SILVERMONT_FSB_FREQ_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_FSB_FREQ_REGISTER::ScalableBusSpeed

[Bits 3:0] Scalable Bus Speed

Silvermont Processor Family

100B: 080.0 MHz 000B: 083.3 MHz 001B: 100.0 MHz 010B: 133.3 MHz 011B: 116.7 MHz

Airmont Processor Family

0000B: 083.3 MHz 0001B: 100.0 MHz 0010B: 133.3 MHz 0011B: 116.7 MHz 0100B: 080.0 MHz 0101B: 093.3 MHz 0110B: 090.0 MHz 0111B: 088.9 MHz 1000B: 087.5 MHz

UINT32 MSR_SILVERMONT_FSB_FREQ_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_FSB_FREQ_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Lock:1
UINT32 Reserved1:1
UINT32 EnableVmxOutsideSmx:1
UINT32 Reserved2:29
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_IA32_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER::EnableVmxOutsideSmx

[Bit 2] Enable VMX outside SMX operation (R/WL).

UINT32 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER::Lock

[Bit 0] Lock (R/WL).

UINT32 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:3
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved4:3
UINT32 EIST:1
UINT32 Reserved5:1
UINT32 MONITOR:1
UINT32 Reserved6:3
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:2
UINT32 XD:1
UINT32 Reserved9:3
UINT32 TurboModeDisable:1
UINT32 Reserved10:25
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Module. Automatic Thermal Control Circuit Enable (R/W) See Table 2-2. Default value is 0.

struct { ... } MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Core. Branch Trace Storage Unavailable (RO) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Module. Enhanced Intel SpeedStep Technology Enable (R/W) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Core. Fast-Strings Enable See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Core. Limit CPUID Maxval (R/W) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] Core. ENABLE MONITOR FSM (R/W) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Core. Processor Event Based Sampling Unavailable (RO) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Core. Performance Monitoring Available (R) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Module. Turbo Mode Disable (R/W) When set to 1 on processors that support Intel Turbo Boost Technology, the turbo mode feature is disabled and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H: EAX[1] reports the processor's support of turbo mode is enabled. Note: the power-on default value is used by BIOS to detect hardware support of turbo mode. If power-on default value is 1, turbo mode is available in the processor. If power-on default value is 0, turbo mode is not available.

UINT64 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] Core. XD Bit Disable (R/W) See Table 2-2.

UINT32 MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] Module. xTPR Message Disable (R/W) See Table 2-2.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_LBR_SELECT_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_LBR_SELECT_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 CPL_EQ_0:1
UINT32 CPL_NEQ_0:1
UINT32 JCC:1
UINT32 NEAR_REL_CALL:1
UINT32 NEAR_IND_CALL:1
UINT32 NEAR_RET:1
UINT32 NEAR_IND_JMP:1
UINT32 NEAR_REL_JMP:1
UINT32 FAR_BRANCH:1
UINT32 Reserved1:23
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_LBR_SELECT

Field Documentation

struct { ... } MSR_SILVERMONT_LBR_SELECT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::CPL_EQ_0

[Bit 0] CPL_EQ_0.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::CPL_NEQ_0

[Bit 1] CPL_NEQ_0.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::FAR_BRANCH

[Bit 8] FAR_BRANCH.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::JCC

[Bit 2] JCC.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::NEAR_IND_CALL

[Bit 4] NEAR_IND_CALL.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::NEAR_IND_JMP

[Bit 6] NEAR_IND_JMP.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::NEAR_REL_CALL

[Bit 3] NEAR_REL_CALL.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::NEAR_REL_JMP

[Bit 7] NEAR_REL_JMP.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::NEAR_RET

[Bit 5] NEAR_RET.

UINT32 MSR_SILVERMONT_LBR_SELECT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_LBR_SELECT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 L2HardwarePrefetcherDisable:1
UINT32 Reserved1:1
UINT32 DCUHardwarePrefetcherDisable:1
UINT32 Reserved2:29
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_MISC_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher, which fetches the next cache line into L1 data cache.

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher, which fetches additional lines of code or data into the L2 cache.

UINT32 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PEBS_ENABLE_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PEBS_ENABLE_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 PEBS:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PEBS_ENABLE

Field Documentation

struct { ... } MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::PEBS

[Bit 0] Enable PEBS for precise event on IA32_PMC0. (R/W).

UINT32 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PEBS_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved3:16
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register until next reset.

UINT32 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map IO_read instructions sent to IO register specified by MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.

UINT32 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power). for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0 (no package C-sate support) 001b: C1 (Behavior is the same as 000b) 100b: C4 110b: C6 111b: C7 (Silvermont only).

UINT32 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PKG_POWER_INFO_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 ThermalSpecPower:15
UINT32 Reserved1:17
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_INFO

Field Documentation

struct { ... } MSR_SILVERMONT_PKG_POWER_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PKG_POWER_INFO_REGISTER::ThermalSpecPower

[Bits 14:0] Thermal Spec Power. (R/0) The unsigned integer value is the equivalent of thermal specification power of the package domain. The unit of this field is specified by the "Power Units" field of MSR_RAPL_POWER_UNIT.

UINT32 MSR_SILVERMONT_PKG_POWER_INFO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PKG_POWER_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Limit:15
UINT32 Enable:1
UINT32 ClampingLimit:1
UINT32 Time:7
UINT32 Reserved1:8
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PKG_POWER_LIMIT

Field Documentation

struct { ... } MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::ClampingLimit

[Bit 16] Package Clamping Limitation #1. (R/W) See Section 14.9.3, "Package RAPL Domain.".

UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Enable

[Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.3, "Package RAPL Domain.".

UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Limit

[Bits 14:0] Package Power Limit #1 (R/W) See Section 14.9.3, "Package RAPL Domain." and MSR_RAPL_POWER_UNIT in Table 2-8.

UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Time

[Bits 23:17] Time Window for Power Limit #1. (R/W) in unit of second. If 0 is specified in bits [23:17], defaults to 1 second window.

UINT32 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PLATFORM_ID_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PLATFORM_ID_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumQualifiedRatio:5
UINT32 Reserved2:19
UINT32 Reserved3:18
UINT32 PlatformId:3
UINT32 Reserved4:11
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_ID

Field Documentation

struct { ... } MSR_SILVERMONT_PLATFORM_ID_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PLATFORM_ID_REGISTER::MaximumQualifiedRatio

[Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.

UINT32 MSR_SILVERMONT_PLATFORM_ID_REGISTER::PlatformId

[Bits 52:50] See Table 2-2.

UINT64 MSR_SILVERMONT_PLATFORM_ID_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PLATFORM_INFO_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNon_TurboRatio:8
UINT32 Reserved2:16
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO

Field Documentation

struct { ... } MSR_SILVERMONT_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PLATFORM_INFO_REGISTER::MaximumNon_TurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio of the maximum frequency that does not require turbo. Frequency = ratio * Scalable Bus Frequency.

UINT32 MSR_SILVERMONT_PLATFORM_INFO_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Lvl2Base:16
UINT32 CStateRange:3
UINT32 Reserved1:13
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PMG_IO_CAPTURE_BASE

Field Documentation

struct { ... } MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::CStateRange

[Bits 18:16] C-state Range (R/W) Specifies the encoding value of the maximum C-State code name to be included when IO read to MWAIT redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 100b - C4 is the max C-State to include 110b - C6 is the max C-State to include 111b - C7 is the max C-State to include.

UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Lvl2Base

[Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address visible to software for IO redirection. If IO MWAIT Redirection is enabled, reads to this address will be consumed by the power management logic and decoded to MWAIT instructions. When IO port address redirection is enabled, this is the IO port address reported to the OS/software.

UINT32 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Limit:15
UINT32 Enable:1
UINT32 Reserved1:1
UINT32 Time:7
UINT32 Reserved2:8
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_PP0_POWER_LIMIT

Field Documentation

struct { ... } MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Enable

[Bit 15] Enable Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains.".

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Limit

[Bits 14:0] PP0 Power Limit #1. (R/W) See Section 14.9.4, "PP0/PP1 RAPL Domains." and MSR_RAPL_POWER_UNIT in Table 35-8.

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Time

[Bits 23:17] Time Window for Power Limit #1. (R/W) Specifies the time duration over which the average power must remain below PP0_POWER_LIMIT #1(14:0). Supported Encodings: 0x0: 1 second time duration. 0x1: 5 second time duration (Default). 0x2: 10 second time duration. 0x3: 15 second time duration. 0x4: 20 second time duration. 0x5: 25 second time duration. 0x6: 30 second time duration. 0x7: 35 second time duration. 0x8: 40 second time duration. 0x9: 45 second time duration. 0xA: 50 second time duration. 0xB-0x7F - reserved.

UINT32 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnits:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Energy Status Units. Energy related information (in microJoules) is based on the multiplier, 2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 00101b, indicating energy unit is in 32 microJoules increment.

UINT32 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Power Units. Power related information (in milliWatts) is based on the multiplier, 2^PU; where PU is an unsigned integer represented by bits 3:0. Default value is 0101b, indicating power unit is in 32 milliWatts increment.

UINT32 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER::TimeUnits

[Bits 19:16] Time Unit. The value is 0000b, indicating time unit is in one second.

UINT32 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_SMI_COUNT_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_SMI_COUNT_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 SMICount:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_SMI_COUNT

Field Documentation

struct { ... } MSR_SILVERMONT_SMI_COUNT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_SMI_COUNT_REGISTER::SMICount

[Bits 31:0] SMI Count (R/O) Running count of SMI events since last RESET.

UINT32 MSR_SILVERMONT_SMI_COUNT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_SMI_COUNT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 TargetOffset:6
UINT32 Reserved2:2
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER::TargetOffset

[Bits 29:24] Target Offset (R/W) Specifies an offset in degrees C to adjust the throttling and PROCHOT# activation temperature from the default target specified in TEMPERATURE_TARGET (bits 23:16).

UINT32 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (R) The default thermal throttling or PROCHOT# activation temperature in degree C, The effective temperature for thermal throttling or PROCHOT# activation is "Temperature Target"

  • "Target Offset".
UINT32 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <SilvermontMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Maximum5C:8
UINT32 Maximum6C:8
UINT32 Maximum7C:8
UINT32 Maximum8C:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SILVERMONT_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum7C

[Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio limit of 7 core active.

UINT32 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Maximum8C

[Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio limit of 8 core active.

UINT64 MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 EnMonitoring:1
UINT32 EnExcept:1
UINT32 EnLBRFrz:1
UINT32 DisableInGuest:1
UINT32 Reserved1:4
UINT32 WindowSize:10
UINT32 Reserved2:6
UINT32 WindowCntSel:2
UINT32 CntAndMode:1
UINT32 Reserved3:5
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL

Field Documentation

struct { ... } MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::CntAndMode

[Bit 26] CntAndMode When set to '1', the overall branch monitoring event triggering condition is true only if all enabled counters' threshold conditions are true. When '0', the threshold tripping condition is true if any enabled counters' threshold is true.

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::DisableInGuest

[Bit 3] DisableInGuest When set to '1', branch monitoring, event triggering and LBR freeze actions are disabled when operating at VMX non-root operation.

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::EnExcept

[Bit 1] EnExcept Enable branch monitoring event signaling on threshold trip. The branch monitoring event handler is signaled via the existing PMI signaling mechanism as programmed from the corresponding local APIC LVT entry.

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::EnLBRFrz

[Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a triggering condition occurs and this bit is enabled.

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::EnMonitoring

[Bit 0] EnMonitoring Global enable for branch monitoring.

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::WindowCntSel

[Bits 25:24] WindowCntSel Window event count select: '00 = Instructions retired. '01 = Branch instructions retired '10 = Return instructions retired. '11 = Indirect branch instructions retired.

UINT32 MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER::WindowSize

[Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 - 1023 are supported. Once the Window counter reaches the WindowSize count both the Window Counter and all Branch Monitoring Counters are cleared.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 BranchMonitoringEventSignaled:1
UINT32 LBRsValid:1
UINT32 Reserved1:6
UINT32 CntrHit0:1
UINT32 CntrHit1:1
UINT32 Reserved2:6
UINT32 CountWindow:10
UINT32 Reserved3:6
UINT32 Count0:8
UINT32 Count1:8
UINT32 Reserved4:16
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS

Field Documentation

struct { ... } MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::BranchMonitoringEventSignaled

[Bit 0] Branch Monitoring Event Signaled When set to '1', Branch Monitoring event signaling is blocked until this bit is cleared by software.

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::CntrHit0

[Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This status bit is sticky and once set requires clearing by software. Counter operation continues independent of the state of the bit.

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::CntrHit1

[Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This status bit is sticky and once set requires clearing by software. Counter operation continues independent of the state of the bit.

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::Count0

[Bits 39:32] Count0 The current value of counter 0 updated after each occurrence of the event being counted. The count value is frozen on a valid branch monitoring triggering condition (in which case CntrHit0 will also be set). This is an 8-bit signed value (2's complement). Heuristic events which only increment will saturate and freeze at maximum value 0xFF (256). RET-CALL event counter saturate at maximum value 0x7F (+127) and minimum value 0x80 (-128).

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::Count1

[Bits 47:40] Count1 The current value of counter 1 updated after each occurrence of the event being counted. The count value is frozen on a valid branch monitoring triggering condition (in which case CntrHit1 will also be set). This is an 8-bit signed value (2's complement). Heuristic events which only increment will saturate and freeze at maximum value 0xFF (256). RET-CALL event counter saturate at maximum value 0x7F (+127) and minimum value 0x80 (-128).

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::CountWindow

[Bits 25:16] CountWindow The current value of the window counter. The count value is frozen on a valid branch monitoring triggering condition. This is a 10-bit unsigned value.

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::LBRsValid

[Bit 1] LBRsValid This status bit is set to '1' if the LBR state is considered valid for sampling by branch monitoring software.

UINT32 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:2
UINT32 ResidencyStateRegulationStatus:1
UINT32 RunningAverageThermalLimitStatus:1
UINT32 VRThermAlertStatus:1
UINT32 VRThermDesignCurrentStatus:1
UINT32 OtherStatus:1
UINT32 Reserved2:1
UINT32 PL1Status:1
UINT32 PL2Status:1
UINT32 MaxTurboLimitStatus:1
UINT32 TurboTransitionAttenuationStatus:1
UINT32 Reserved3:2
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 Reserved4:2
UINT32 ResidencyStateRegulationLog:1
UINT32 RunningAverageThermalLimitLog:1
UINT32 VRThermAlertLog:1
UINT32 VRThermalDesignCurrentLog:1
UINT32 OtherLog:1
UINT32 Reserved5:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 MaxTurboLimitLog:1
UINT32 TurboTransitionAttenuationLog:1
UINT32 Reserved6:2
UINT32 Reserved7:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS

Field Documentation

struct { ... } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitLog

[Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo Limit Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::MaxTurboLimitStatus

[Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced below the operating system request due to multi-core turbo limits.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::OtherLog

[Bit 24] Other Log When set, indicates that the Other Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::OtherStatus

[Bit 8] Other Status (R0) When set, frequency is reduced below the operating system request due to electrical or other constraints.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package or Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::PL1Status

[Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced below the operating system request due to package/platform-level power limiting PL1.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package or Platform Level PL2/PL3 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced below the operating system request due to package/platform-level power limiting PL2/PL3.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::ResidencyStateRegulationLog

[Bit 20] Residency State Regulation Log When set, indicates that the Residency State Regulation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::ResidencyStateRegulationStatus

[Bit 4] Residency State Regulation Status (R0) When set, frequency is reduced below the operating system request due to residency state regulation limit.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitLog

[Bit 21] Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitStatus

[Bit 5] Running Average Thermal Limit Status (R0) When set, frequency is reduced below the operating system request due to Running Average Thermal Limit (RATL).

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationLog

[Bit 29] Turbo Transition Attenuation Log When set, indicates that the Turbo Transition Attenuation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::TurboTransitionAttenuationStatus

[Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency is reduced below the operating system request due to Turbo transition attenuation. This prevents performance degradation due to frequent operating ratio changes.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentLog

[Bit 23] VR Thermal Design Current Log When set, indicates that the VR TDC Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from a processor Voltage Regulator (VR).

UINT32 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermDesignCurrentStatus

[Bit 7] VR Therm Design Current Status (R0) When set, frequency is reduced below the operating system request due to VR thermal design current limit.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Energy:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS

Field Documentation

struct { ... } MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER::Energy

[Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM RAPL mode 0 (Direct VR).

UINT32 MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:3
UINT32 RunningAverageThermalLimitStatus:1
UINT32 VRThermAlertStatus:1
UINT32 VRThermalDesignCurrentStatus:1
UINT32 OtherStatus:1
UINT32 Reserved2:1
UINT32 PL1Status:1
UINT32 PL2Status:1
UINT32 InefficientOperationStatus:1
UINT32 Reserved3:3
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 Reserved4:3
UINT32 RunningAverageThermalLimitLog:1
UINT32 VRThermAlertLog:1
UINT32 VRThermalDesignCurrentLog:1
UINT32 OtherLog:1
UINT32 Reserved5:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 InefficientOperationLog:1
UINT32 Reserved6:3
UINT32 Reserved7:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS

Field Documentation

struct { ... } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::InefficientOperationLog

[Bit 28] Inefficient Operation Log When set, indicates that the Inefficient Operation Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::InefficientOperationStatus

[Bit 12] Inefficient Operation Status (R0) When set, processor graphics frequency is operating below target frequency.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::OtherLog

[Bit 24] Other Log When set, indicates that the OTHER Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::OtherStatus

[Bit 8] Other Status (R0) When set, frequency is reduced due to electrical or other constraints.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package/Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL1Status

[Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced due to package/platform-level power limiting PL1.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package/Platform Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced due to package/platform-level power limiting PL2/PL3.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to assertion of external PROCHOT.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitLog

[Bit 21] Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitStatus

[Bit 5] Running Average Thermal Limit Status (R0) When set, frequency is reduced due to running average thermal limit.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced due to a thermal event.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentLog

[Bit 23] VR Thermal Design Current Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentStatus

[Bit 7] VR Thermal Design Current Status (R0) When set, frequency is reduced due to VR TDC limit.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due to a thermal alert from a processor Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 CBM:20
UINT32 Reserved2:12
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N

Field Documentation

struct { ... } MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::CBM

[Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.

UINT32 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Count:8
UINT32 MCG_CTL_P:1
UINT32 MCG_EXT_P:1
UINT32 MCP_CMCI_P:1
UINT32 MCG_TES_P:1
UINT32 Reserved1:4
UINT32 MCG_EXT_CNT:8
UINT32 MCG_SER_P:1
UINT32 MCG_EM_P:1
UINT32 MCG_ELOG_P:1
UINT32 Reserved2:5
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP

Field Documentation

struct { ... } MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::Count

[Bits 7:0] Count.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_CTL_P

[Bit 8] MCG_CTL_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_ELOG_P

[Bit 26] MCG_ELOG_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_EM_P

[Bit 25] MCG_EM_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_EXT_CNT

[Bits 23:16] MCG_EXT_CNT.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_EXT_P

[Bit 9] MCG_EXT_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_SER_P

[Bit 24] MCG_SER_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCG_TES_P

[Bit 11] MCG_TES_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::MCP_CMCI_P

[Bit 10] MCP_CMCI_P.

UINT32 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_IA32_MCG_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Ovf_PMC4:1
UINT32 Ovf_PMC5:1
UINT32 Ovf_PMC6:1
UINT32 Ovf_PMC7:1
UINT32 Reserved1:24
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS

Field Documentation

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::ASCI

[Bit 60] Thread. ASCI.

struct { ... } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::CondChgd

[Bit 63] Thread. CondChgd.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::CTR_Frz

[Bit 59] Thread. CTR_Frz.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::LBR_Frz

[Bit 58] Thread. LBR_Frz.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Ovf_BufDSSAVE.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Ovf_FixedCtr0.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Ovf_FixedCtr1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Ovf_FixedCtr2.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC0

[Bit 0] Thread. Ovf_PMC0.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC1

[Bit 1] Thread. Ovf_PMC1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC2

[Bit 2] Thread. Ovf_PMC2.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC3

[Bit 3] Thread. Ovf_PMC3.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC4

[Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC5

[Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC6

[Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_PMC7

[Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Ovf_Uncore

[Bit 61] Thread. Ovf_Uncore.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Trace_ToPA_PMI

[Bit 55] Thread. Trace_ToPA_PMI.

UINT64 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Ovf_PMC4:1
UINT32 Ovf_PMC5:1
UINT32 Ovf_PMC6:1
UINT32 Ovf_PMC7:1
UINT32 Reserved1:24
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 CondChgd:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET

Field Documentation

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::ASCI

[Bit 60] Thread. Set 1 to clear ASCI.

struct { ... } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CondChgd

[Bit 63] Thread. Set 1 to clear CondChgd.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::CTR_Frz

[Bit 59] Thread. Set 1 to clear CTR_Frz.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::LBR_Frz

[Bit 58] Thread. Set 1 to clear LBR_Frz.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC0

[Bit 0] Thread. Set 1 to clear Ovf_PMC0.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC1

[Bit 1] Thread. Set 1 to clear Ovf_PMC1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC2

[Bit 2] Thread. Set 1 to clear Ovf_PMC2.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC3

[Bit 3] Thread. Set 1 to clear Ovf_PMC3.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC4

[Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC5

[Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC6

[Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_PMC7

[Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Ovf_Uncore

[Bit 61] Thread. Set 1 to clear Ovf_Uncore.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Trace_ToPA_PMI

[Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI.

UINT64 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Ovf_PMC0:1
UINT32 Ovf_PMC1:1
UINT32 Ovf_PMC2:1
UINT32 Ovf_PMC3:1
UINT32 Ovf_PMC4:1
UINT32 Ovf_PMC5:1
UINT32 Ovf_PMC6:1
UINT32 Ovf_PMC7:1
UINT32 Reserved1:24
UINT32 Ovf_FixedCtr0:1
UINT32 Ovf_FixedCtr1:1
UINT32 Ovf_FixedCtr2:1
UINT32 Reserved2:20
UINT32 Trace_ToPA_PMI:1
UINT32 Reserved3:2
UINT32 LBR_Frz:1
UINT32 CTR_Frz:1
UINT32 ASCI:1
UINT32 Ovf_Uncore:1
UINT32 Ovf_BufDSSAVE:1
UINT32 Reserved4:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET

Field Documentation

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::ASCI

[Bit 60] Thread. Set 1 to cause ASCI = 1.

struct { ... } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::CTR_Frz

[Bit 59] Thread. Set 1 to cause CTR_Frz = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::LBR_Frz

[Bit 58] Thread. Set 1 to cause LBR_Frz = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_BufDSSAVE

[Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr0

[Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr1

[Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_FixedCtr2

[Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC0

[Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC1

[Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC2

[Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC3

[Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC4

[Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC5

[Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC6

[Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_PMC7

[Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7).

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Ovf_Uncore

[Bit 61] Thread. Set 1 to cause Ovf_Uncore.

UINT32 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Trace_ToPA_PMI

[Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1.

UINT64 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 RMID:10
UINT32 Reserved1:22
UINT32 COS:20
UINT32 Reserved2:12
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC

Field Documentation

struct { ... } MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER::COS

[Bits 51:32] COS (R/W).

UINT32 MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER::RMID

[Bits 9:0] RMID.

UINT64 MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 EventID:8
UINT32 Reserved1:24
UINT32 RMID:10
UINT32 Reserved2:22
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL

Field Documentation

struct { ... } MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::EventID

[Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3 occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03: Local memory bandwidth monitoring. All other encoding reserved.

UINT32 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::RMID

[Bits 41:32] RMID (RW).

UINT64 MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 MAX_RATIO:7
UINT32 Reserved1:1
UINT32 MIN_RATIO:7
UINT32 Reserved2:17
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT

Field Documentation

struct { ... } MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER::MAX_RATIO

[Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the LLC/Ring.

UINT32 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER::MIN_RATIO

[Bits 14:8] MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring.

UINT32 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 EventCodeSelect:3
UINT32 Reserved1:1
UINT32 EventCodeSelectHigh:1
UINT32 Reserved2:3
UINT32 IDQ_Bubble_Length:12
UINT32 IDQ_Bubble_Width:3
UINT32 Reserved3:9
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND

Field Documentation

struct { ... } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::EventCodeSelect

[Bits 2:0] Event Code Select.

UINT32 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::EventCodeSelectHigh

[Bit 4] Event Code Select High.

UINT32 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::IDQ_Bubble_Length

[Bits 19:8] IDQ_Bubble_Length Specifier.

UINT32 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::IDQ_Bubble_Width

[Bits 22:20] IDQ_Bubble_Width Specifier.

UINT32 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 C_StateLimit:3
UINT32 Reserved1:7
UINT32 MWAITRedirectionEnable:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 AutomaticC_StateConversionEnable:1
UINT32 Reserved3:8
UINT32 C3StateAutoDemotionEnable:1
UINT32 C1StateAutoDemotionEnable:1
UINT32 EnableC3Undemotion:1
UINT32 EnableC1Undemotion:1
UINT32 CStateDemotionEnable:1
UINT32 CStateUnDemotionEnable:1
UINT32 Reserved4:1
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL

Field Documentation

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::AutomaticC_StateConversionEnable

[Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).

struct { ... } MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::C1StateAutoDemotionEnable

[Bit 26] C1 State Auto Demotion Enable (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::C3StateAutoDemotionEnable

[Bit 25] C3 State Auto Demotion Enable (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::C_StateLimit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package Cstate limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 011b: C6 (retention) 111b: No Package C state limits. All C states supported by the processor are available.

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::CStateDemotionEnable

[Bit 29] Package C State Demotion Enable (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::CStateUnDemotionEnable

[Bit 30] Package C State UnDemotion Enable (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::EnableC1Undemotion

[Bit 28] Enable C1 Undemotion (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::EnableC3Undemotion

[Bit 27] Enable C3 Undemotion (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::MWAITRedirectionEnable

[Bit 10] I/O MWAIT Redirection Enable (R/W).

UINT32 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PKG_Cx_Monitor:3
UINT32 Reserved1:29
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG

Field Documentation

struct { ... } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER::PKG_Cx_Monitor

[Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for MSR_PKG_HDC_DEEP_RESIDENCY.

UINT32 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 TotalEnergy:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER

Field Documentation

struct { ... } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER::TotalEnergy

[Bits 31:0] Total energy consumed by all devices in the platform that receive power from integrated power delivery mechanism, Included platform devices are processor cores, SOC, memory, add-on or peripheral devices that get powered directly from the platform power delivery means. The energy units are specified in the MSR_RAPL_POWER_UNIT.Enery_Status_Unit.

UINT32 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PLATFORM_INFO_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNon_TurboRatio:8
UINT32 Reserved2:7
UINT32 PPIN_CAP:1
UINT32 Reserved3:4
UINT32 ProgrammableRatioLimit:1
UINT32 ProgrammableTDPLimit:1
UINT32 ProgrammableTJOFFSET:1
UINT32 Reserved4:1
UINT32 Reserved5:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved6:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO

Field Documentation

struct { ... } MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::MaximumNon_TurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::PPIN_CAP

[Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::ProgrammableRatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See Table 2-25.

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::ProgrammableTDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See Table 2-25.

UINT32 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::ProgrammableTJOFFSET

[Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.

UINT64 MSR_SKYLAKE_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PlatformPowerLimit1:15
UINT32 EnablePlatformPowerLimit1:1
UINT32 PlatformClampingLimitation1:1
UINT32 Time:7
UINT32 Reserved1:8
UINT32 PlatformPowerLimit2:15
UINT32 EnablePlatformPowerLimit2:1
UINT32 PlatformClampingLimitation2:1
UINT32 Reserved2:14
UINT32 Lock:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT

Field Documentation

struct { ... } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::EnablePlatformPowerLimit1

[Bit 15] Enable Platform Power Limit #1. When set, enables the processor to apply control policy such that the platform power does not exceed Platform Power limit #1 over the time window specified by Power Limit #1 Time Window.

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::EnablePlatformPowerLimit2

[Bit 47] Enable Platform Power Limit #2. When set, enables the processor to apply control policy such that the platform power does not exceed Platform Power limit #2 over the Short Duration time window.

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::Lock

[Bit 63] Lock. Setting this bit will lock all other bits of this MSR until system RESET.

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::PlatformClampingLimitation1

[Bit 16] Platform Clamping Limitation #1. When set, allows the processor to go below the OS requested P states in order to maintain the power below specified Platform Power Limit #1 value. This bit is writeable only when CPUID (EAX=6):EAX[4] is set.

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::PlatformClampingLimitation2

[Bit 48] Platform Clamping Limitation #2. When set, allows the processor to go below the OS requested P states in order to maintain the power below specified Platform Power Limit #2 value.

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::PlatformPowerLimit1

[Bits 14:0] Platform Power Limit #1. Average Power limit value which the platform must not exceed over a time window as specified by Power_Limit_1_TIME field. The default value is the Thermal Design Power (TDP) and varies with product skus. The unit is specified in MSR_RAPLPOWER_UNIT.

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::PlatformPowerLimit2

[Bits 46:32] Platform Power Limit #2. Average Power limit value which the platform must not exceed over the Short Duration time window chosen by the processor. The recommended default value is 1.25 times the Long Duration Power Limit (i.e. Platform Power Limit # 1).

UINT32 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::Time

[Bits 23:17] Time Window for Platform Power Limit #1. Specifies the duration of the time window over which Platform Power Limit 1 value should be maintained for sustained long duration. This field is made up of two numbers from the following equation: Time Window = (float) ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. = POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH, The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit].

UINT64 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_POWER_CTL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_POWER_CTL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 C1EEnable:1
UINT32 Reserved2:17
UINT32 Fix_Me_1:1
UINT32 DisableEnergyEfficiencyOptimization:1
UINT32 Reserved3:11
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL

Field Documentation

struct { ... } MSR_SKYLAKE_POWER_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::C1EEnable

[Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU to switch to the Minimum Enhanced Intel SpeedStep Technology operating point when all execution cores enter MWAIT (C1).

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::DisableEnergyEfficiencyOptimization

[Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit disables the P-States energy efficiency optimization. Default value is 0. Disable/enable the energy efficiency optimization in P-State legacy mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS desired or OS maximize to the OS minimize performance setting.

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Fix_Me_1

[Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit disables the Race to Halt optimization and avoids this optimization limitation to execute below the most efficient frequency ratio. Default value is 0 for processors that support Race to Halt optimization. Default value is 1 for processors that do not support Race to Halt optimization.

UINT32 MSR_SKYLAKE_POWER_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_POWER_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PPIN_CTL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PPIN_CTL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 LockOut:1
UINT32 Enable_PPIN:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL

Field Documentation

struct { ... } MSR_SKYLAKE_PPIN_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::Enable_PPIN

[Bit 1] Enable_PPIN (R/W) See Table 2-25.

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::LockOut

[Bit 0] LockOut (R/WO) See Table 2-25.

UINT32 MSR_SKYLAKE_PPIN_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_PPIN_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 MemTypePRMRRBASEMemType:3
UINT32 Reserved1:9
UINT32 BasePRMRRBaseAddress:20
UINT32 Fix_Me_1:14
UINT32 Reserved2:18
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE

Field Documentation

UINT32 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER::BasePRMRRBaseAddress

[Bits 31:12] Base PRMRR Base Address.

struct { ... } MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER::Fix_Me_1

[Bits 45:32] Base PRMRR Base Address.

UINT32 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER::MemTypePRMRRBASEMemType

[Bits 2:0] MemType PRMRR BASE MemType.

UINT64 MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:10
UINT32 Fix_Me_1:1
UINT32 VLD:1
UINT32 Fix_Me_2:20
UINT32 Fix_Me_3:14
UINT32 Reserved2:18
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK

Field Documentation

struct { ... } MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_1

[Bit 10] Lock Lock bit for the PRMRR.

UINT32 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_2

[Bits 31:12] Mask PRMRR MASK bits.

UINT32 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_3

[Bits 45:32] Mask PRMRR MASK bits.

UINT64 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER::VLD

[Bit 11] VLD Enable bit for the PRMRR.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Fix_Me_1:1
UINT32 Reserved1:4
UINT32 Fix_Me_2:1
UINT32 Fix_Me_3:1
UINT32 Fix_Me_4:1
UINT32 Reserved2:24
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG

Field Documentation

struct { ... } MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Fix_Me_1

[Bit 0] 1M supported MEE size.

UINT32 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Fix_Me_2

[Bit 5] 32M supported MEE size.

UINT32 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Fix_Me_3

[Bit 6] 64M supported MEE size.

UINT32 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Fix_Me_4

[Bit 7] 128M supported MEE size.

UINT32 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnits:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Package. Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules).

UINT32 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER::TimeUnits

[Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:3
UINT32 RunningAverageThermalLimitStatus:1
UINT32 VRThermAlertStatus:1
UINT32 VRThermalDesignCurrentStatus:1
UINT32 OtherStatus:1
UINT32 Reserved2:1
UINT32 PL1Status:1
UINT32 PL2Status:1
UINT32 Reserved3:4
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 Reserved4:3
UINT32 RunningAverageThermalLimitLog:1
UINT32 VRThermAlertLog:1
UINT32 VRThermalDesignCurrentLog:1
UINT32 OtherLog:1
UINT32 Reserved5:1
UINT32 PL1Log:1
UINT32 PL2Log:1
UINT32 Reserved6:4
UINT32 Reserved7:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS

Field Documentation

struct { ... } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::OtherLog

[Bit 24] Other Log When set, indicates that the OTHER Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::OtherStatus

[Bit 8] Other Status (R0) When set, frequency is reduced due to electrical or other constraints.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL1Log

[Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, indicates that the Package/Platform Level PL1 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL1Status

[Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When set, frequency is reduced due to package/Platform-level power limiting PL1.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL2Log

[Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, indicates that the Package/Platform Level PL2 Power Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PL2Status

[Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When set, frequency is reduced due to package/Platform-level power limiting PL2/PL3.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to assertion of external PROCHOT.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitLog

[Bit 21] Running Average Thermal Limit Log When set, indicates that the RATL Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::RunningAverageThermalLimitStatus

[Bit 5] Running Average Thermal Limit Status (R0) When set, frequency is reduced due to running average thermal limit.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced due to a thermal event.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentLog

[Bit 23] VR Thermal Design Current Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermalDesignCurrentStatus

[Bit 7] VR Thermal Design Current Status (R0) When set, frequency is reduced due to VR TDC limit.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due to a thermal alert from a processor Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Fix_Me_1:7
UINT32 Reserved1:1
UINT32 Fix_Me_2:7
UINT32 Reserved2:17
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT

Field Documentation

struct { ... } MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER::Fix_Me_1

[Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the LLC/Ring.

UINT32 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER::Fix_Me_2

[Bits 14:8] MIN_Ratio Writing to this field controls the minimum possible ratio of the LLC/Ring.

UINT32 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:26
UINT32 SMM_Code_Access_Chk:1
UINT32 Long_Flow_Indication:1
UINT32 Reserved3:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP

Field Documentation

struct { ... } MSR_SKYLAKE_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and a host-space interface is available to SMM handler.

UINT32 MSR_SKYLAKE_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and a host-space interface is available to SMM handler.

UINT64 MSR_SKYLAKE_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 TCCActivationOffset:4
UINT32 Reserved2:4
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER::TCCActivationOffset

[Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.

UINT32 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (RO) See Table 2-25.

UINT32 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Fix_Me_1:1
UINT32 Reserved:17
UINT32 ACPIBAR_BASE_ADDRESS:14
UINT32 Fix_Me_2:32
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE

Field Documentation

UINT32 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER::ACPIBAR_BASE_ADDRESS

[Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.

struct { ... } MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER::Fix_Me_1

[Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock bit has to be set in order for the AET packets to be directed to NPK MMIO.

UINT32 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER::Fix_Me_2

[Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.

UINT64 MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 NUMCORE_0:8
UINT32 NUMCORE_1:8
UINT32 NUMCORE_2:8
UINT32 NUMCORE_3:8
UINT32 NUMCORE_4:8
UINT32 NUMCORE_5:8
UINT32 NUMCORE_6:8
UINT32 NUMCORE_7:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES

Field Documentation

struct { ... } MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_0

[Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_1

[Bits 15:8] NUMCORE_1 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_2

[Bits 23:16] NUMCORE_2 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_3

[Bits 31:24] NUMCORE_3 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_4

[Bits 39:32] NUMCORE_4 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_5

[Bits 47:40] NUMCORE_5 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_6

[Bits 55:48] NUMCORE_6 Defines the active core ranges for each frequency point.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::NUMCORE_7

[Bits 63:56] NUMCORE_7 Defines the active core ranges for each frequency point.

UINT64 MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 CBox:4
UINT32 Reserved1:28
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG

Field Documentation

struct { ... } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER::CBox

[Bits 3:0] Specifies the number of C-Box units with programmable counters (including processor cores and processor graphics),.

UINT32 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 CurrentCount:32
UINT32 CurrentCountHi:12
UINT32 Reserved:20
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR

Field Documentation

struct { ... } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER::CurrentCount

[Bits 31:0] Current count.

UINT32 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER::CurrentCountHi

[Bits 43:32] Current count.

UINT64 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:20
UINT32 EnableOverflow:1
UINT32 Reserved2:1
UINT32 EnableCounting:1
UINT32 Reserved3:9
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL

Field Documentation

struct { ... } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER::EnableCounting

[Bit 22] Enable counting.

UINT32 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER::EnableOverflow

[Bit 20] Enable overflow propagation.

UINT32 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 PMI_Sel_Slice0:1
UINT32 PMI_Sel_Slice1:1
UINT32 PMI_Sel_Slice2:1
UINT32 PMI_Sel_Slice3:1
UINT32 PMI_Sel_Slice4:1
UINT32 Reserved1:14
UINT32 Reserved2:10
UINT32 EN:1
UINT32 WakePMI:1
UINT32 FREEZE:1
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL

Field Documentation

struct { ... } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::EN

[Bit 29] Enable all uncore counters.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::FREEZE

[Bit 31] Enable Freezing counter when overflow.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice0

[Bit 0] Slice 0 select.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice1

[Bit 1] Slice 1 select.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice2

[Bit 2] Slice 2 select.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice3

[Bit 3] Slice 3 select.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::PMI_Sel_Slice4

[Bit 4] Slice 4select.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER::WakePMI

[Bit 30] Enable wake on PMI.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Fixed:1
UINT32 ARB:1
UINT32 Reserved1:1
UINT32 CBox:1
UINT32 Reserved2:28
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS

Field Documentation

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER::ARB

[Bit 1] An ARB counter overflowed.

struct { ... } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER::CBox

[Bit 3] A CBox counter overflowed (on any slice).

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER::Fixed

[Bit 0] Fixed counter overflowed.

UINT32 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:12
UINT32 Fix_Me_1:20
UINT32 Fix_Me_2:7
UINT32 Reserved2:25
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE

Field Documentation

struct { ... } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER::Fix_Me_1

[Bits 31:12] Range Base This field corresponds to bits 38:12 of the base address memory range which is allocated to PRMRR memory.

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER::Fix_Me_2

[Bits 38:32] Range Base This field corresponds to bits 38:12 of the base address memory range which is allocated to PRMRR memory.

UINT64 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Union Reference

Data Fields
MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Union Reference

#include <SkylakeMsr.h>

Data Fields

struct {
UINT32 Reserved1:10
UINT32 Fix_Me_1:1
UINT32 Fix_Me_2:1
UINT32 Reserved2:20
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK

Field Documentation

struct { ... } MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_1

[Bit 10] Lock Setting this bit locks all writeable settings in this register, including itself.

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Fix_Me_2

[Bit 11] Range_En Indicates whether the PRMRR range is enabled and valid.

UINT32 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_5600_FEATURE_CONFIG_REGISTER Union Reference

Data Fields
MSR_XEON_5600_FEATURE_CONFIG_REGISTER Union Reference

#include <Xeon5600Msr.h>

Data Fields

struct {
UINT32 AESConfiguration:2
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG

Field Documentation

UINT32 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

struct { ... } MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_5600_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <Xeon5600Msr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Maximum5C:8
UINT32 Maximum6C:8
UINT32 Reserved:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER

Field Documentation

struct { ... } MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio limit of 1 core active.

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio limit of 2 core active.

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio limit of 3 core active.

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio limit of 4 core active.

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio limit of 5 core active.

UINT32 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio limit of 6 core active.

UINT64 MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 PowerBudgetManagementStatus:1
UINT32 PlatformConfigurationServicesStatus:1
UINT32 Reserved1:1
UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1
UINT32 VRThermAlertStatus:1
UINT32 Reserved2:1
UINT32 ElectricalDesignPointStatus:1
UINT32 Reserved3:1
UINT32 MultiCoreTurboStatus:1
UINT32 Reserved4:2
UINT32 FrequencyP1Status:1
UINT32 TurboFrequencyLimitingStatus:1
UINT32 FrequencyLimitingStatus:1
UINT32 PROCHOT_Log:1
UINT32 ThermalLog:1
UINT32 PowerBudgetManagementLog:1
UINT32 PlatformConfigurationServicesLog:1
UINT32 Reserved5:1
UINT32 AutonomousUtilizationBasedFrequencyControlLog:1
UINT32 VRThermAlertLog:1
UINT32 Reserved6:1
UINT32 ElectricalDesignPointLog:1
UINT32 Reserved7:1
UINT32 MultiCoreTurboLog:1
UINT32 Reserved8:2
UINT32 CoreFrequencyP1Log:1
UINT32 TurboFrequencyLimitingLog:1
UINT32 CoreFrequencyLimitingLog:1
UINT32 Reserved9:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS

Field Documentation

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlLog

[Bit 21] Autonomous Utilization-Based Frequency Control Log When set, indicates that the AUBFC Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::AutonomousUtilizationBasedFrequencyControlStatus

[Bit 5] Autonomous Utilization-Based Frequency Control Status (R0) When set, frequency is reduced below the operating system request because the processor has detected that utilization is low.

struct { ... } MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::CoreFrequencyLimitingLog

[Bit 31] Core Frequency Limiting Log When set, indicates that the Core Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::CoreFrequencyP1Log

[Bit 29] Core Frequency P1 Log When set, indicates that the Core Frequency P1 Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointLog

[Bit 24] Electrical Design Point Log When set, indicates that the EDP Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0) When set, frequency is reduced below the operating system request due to electrical design point constraints (e.g. maximum electrical current consumption).

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::FrequencyLimitingStatus

[Bit 15] Core Frequency Limiting Status (R0) When set, frequency is reduced below the operating system request.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::FrequencyP1Status

[Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced below max non-turbo P1.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::MultiCoreTurboLog

[Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core Turbo Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::MultiCoreTurboStatus

[Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced below the operating system request due to Multi-Core Turbo limits.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::PlatformConfigurationServicesLog

[Bit 19] Platform Configuration Services Log When set, indicates that the PCS Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::PlatformConfigurationServicesStatus

[Bit 3] Platform Configuration Services Status (R0) When set, frequency is reduced below the operating system request due to PCS limit.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::PowerBudgetManagementLog

[Bit 18] Power Budget Management Log When set, indicates that the PBM Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::PowerBudgetManagementStatus

[Bit 2] Power Budget Management Status (R0) When set, frequency is reduced below the operating system request due to PBM limit.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Log

[Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0) When set, processor core frequency is reduced below the operating system request due to assertion of external PROCHOT.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalLog

[Bit 17] Thermal Log When set, indicates that the Thermal Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0) When set, frequency is reduced below the operating system request due to a thermal event.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::TurboFrequencyLimitingLog

[Bit 30] Core Max n-core Turbo Frequency Limiting Log When set, indicates that the Core Max n-core Turbo Frequency Limiting Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::TurboFrequencyLimitingStatus

[Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When set, frequency is reduced below max n-core turbo frequency.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertLog

[Bit 22] VR Therm Alert Log When set, indicates that the VR Therm Alert Status bit has asserted since the log bit was last cleared. This log bit will remain set until cleared by software writing 0.

UINT32 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced below the operating system request due to a thermal alert from the Voltage Regulator.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Union Reference

Data Fields
MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Energy:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS

Field Documentation

struct { ... } MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER::Energy

[Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration to enable DRAM RAPL mode 0 (Direct VR).

UINT32 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Union Reference

Data Fields
MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 CAT:1
UINT32 Reserved1:31
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG

Field Documentation

struct { ... } MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER::CAT

[Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.

UINT32 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Union Reference

Data Fields
MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 CBM:20
UINT32 Reserved2:12
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.

Field Documentation

struct { ... } MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER::CBM

[Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.

UINT32 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_IA32_MCG_CAP_REGISTER Union Reference

Data Fields
MSR_XEON_D_IA32_MCG_CAP_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Count:8
UINT32 MCG_CTL_P:1
UINT32 MCG_EXT_P:1
UINT32 MCP_CMCI_P:1
UINT32 MCG_TES_P:1
UINT32 Reserved1:4
UINT32 MCG_EXT_CNT:8
UINT32 MCG_SER_P:1
UINT32 MCG_EM_P:1
UINT32 MCG_ELOG_P:1
UINT32 Reserved2:5
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP

Field Documentation

struct { ... } MSR_XEON_D_IA32_MCG_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::Count

[Bits 7:0] Count.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_CTL_P

[Bit 8] MCG_CTL_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_ELOG_P

[Bit 26] MCG_ELOG_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_EM_P

[Bit 25] MCG_EM_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_EXT_CNT

[Bits 23:16] MCG_EXT_CNT.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_EXT_P

[Bit 9] MCG_EXT_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_SER_P

[Bit 24] MCG_SER_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCG_TES_P

[Bit 11] MCG_TES_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::MCP_CMCI_P

[Bit 10] MCP_CMCI_P.

UINT32 MSR_XEON_D_IA32_MCG_CAP_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_IA32_MCG_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Union Reference

Data Fields
MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 RMID:10
UINT32 Reserved1:22
UINT32 COS:20
UINT32 Reserved2:12
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC

Field Documentation

struct { ... } MSR_XEON_D_IA32_PQR_ASSOC_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER::COS

[Bits 51:32] COS (R/W).

UINT32 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER::RMID

[Bits 9:0] RMID.

UINT64 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Union Reference

Data Fields
MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 EventID:8
UINT32 Reserved1:24
UINT32 RMID:10
UINT32 Reserved2:22
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL

Field Documentation

struct { ... } MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::EventID

[Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3 occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03: Local memory bandwidth monitoring All other encoding reserved.

UINT32 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::RMID

[Bits 41:32] RMID (RW).

UINT64 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 MAX_RATIO:7
UINT32 Reserved1:1
UINT32 MIN_RATIO:7
UINT32 Reserved2:17
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT

Field Documentation

struct { ... } MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER::MAX_RATIO

[Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the LLC/Ring.

UINT32 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER::MIN_RATIO

[Bits 14:8] MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring.

UINT32 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 CStateConversion:1
UINT32 Reserved3:8
UINT32 C3AutoDemotion:1
UINT32 C1AutoDemotion:1
UINT32 C3Undemotion:1
UINT32 C1Undemotion:1
UINT32 CStateDemotion:1
UINT32 CStateUndemotion:1
UINT32 Reserved4:1
UINT32 Reserved5:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::C1AutoDemotion

[Bit 26] C1 State Auto Demotion Enable (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::C1Undemotion

[Bit 28] Enable C1 Undemotion (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::C3AutoDemotion

[Bit 25] C3 State Auto Demotion Enable (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::C3Undemotion

[Bit 27] Enable C3 Undemotion (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::CStateConversion

[Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor will convert HALT or MWAT(C1) to MWAIT(C6).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::CStateDemotion

[Bit 29] Package C State Demotion Enable (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::CStateUndemotion

[Bit 30] Package C State UnDemotion Enable (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W).

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) Specifies the lowest processor-specific C-state code name (consuming the least power) for the package. The default is set as factory-configured package C-state limit. The following C-state code name encodings are supported: 000b: C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention) 011b: C6 (retention) 111b: No Package C state limits. All C states supported by the processor are available.

UINT32 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_XEON_D_PLATFORM_INFO_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:7
UINT32 PPIN_CAP:1
UINT32 Reserved3:4
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 TJOFFSET:1
UINT32 Reserved4:1
UINT32 Reserved5:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved6:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO

Field Documentation

struct { ... } MSR_XEON_D_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.

UINT32 MSR_XEON_D_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.

UINT32 MSR_XEON_D_PLATFORM_INFO_REGISTER::PPIN_CAP

[Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.

UINT32 MSR_XEON_D_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See Table 2-25.

UINT32 MSR_XEON_D_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See Table 2-25.

UINT32 MSR_XEON_D_PLATFORM_INFO_REGISTER::TJOFFSET

[Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.

UINT64 MSR_XEON_D_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_PPIN_CTL_REGISTER Union Reference

Data Fields
MSR_XEON_D_PPIN_CTL_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 LockOut:1
UINT32 Enable_PPIN:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL

Field Documentation

struct { ... } MSR_XEON_D_PPIN_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_PPIN_CTL_REGISTER::Enable_PPIN

[Bit 1] Enable_PPIN (R/W) See Table 2-25.

UINT32 MSR_XEON_D_PPIN_CTL_REGISTER::LockOut

[Bit 0] LockOut (R/WO) See Table 2-25.

UINT32 MSR_XEON_D_PPIN_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_PPIN_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnits:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_XEON_D_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Package. Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules).

UINT32 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER::TimeUnits

[Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_SMM_MCA_CAP_REGISTER Union Reference

Data Fields
MSR_XEON_D_SMM_MCA_CAP_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:26
UINT32 SMM_Code_Access_Chk:1
UINT32 Long_Flow_Indication:1
UINT32 Reserved3:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP

Field Documentation

struct { ... } MSR_XEON_D_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler.

UINT32 MSR_XEON_D_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and a host-space interface available to SMM handler.

UINT64 MSR_XEON_D_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 TCCActivationOffset:4
UINT32 Reserved2:4
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_XEON_D_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER::TCCActivationOffset

[Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.

UINT32 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (RO) See Table 2-25.

UINT32 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Union Reference

Data Fields
MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Maximum9C:8
UINT32 Maximum10C:8
UINT32 Maximum11C:8
UINT32 Maximum12C:8
UINT32 Maximum13C:8
UINT32 Maximum14C:8
UINT32 Maximum15C:8
UINT32 Maximum16C:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1

Field Documentation

struct { ... } MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum10C

[Bits 15:8] Package. Maximum Ratio Limit for 10C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum11C

[Bits 23:16] Package. Maximum Ratio Limit for 11C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum12C

[Bits 31:24] Package. Maximum Ratio Limit for 12C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum13C

[Bits 39:32] Package. Maximum Ratio Limit for 13C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum14C

[Bits 47:40] Package. Maximum Ratio Limit for 14C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum15C

[Bits 55:48] Package. Maximum Ratio Limit for 15C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum16C

[Bits 63:56] Package. Maximum Ratio Limit for 16C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Maximum9C

[Bits 7:0] Package. Maximum Ratio Limit for 9C.

UINT64 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Union Reference

Data Fields
MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Reserved1:32
UINT32 Reserved2:31
UINT32 TurboRatioLimitConfigurationSemaphore:1
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3

Field Documentation

struct { ... } MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER::TurboRatioLimitConfigurationSemaphore

[Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1, the processor uses override configuration specified in MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor uses factory-set configuration (Default).

UINT64 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <XeonDMsr.h>

Data Fields

struct {
UINT32 Maximum1C:8
UINT32 Maximum2C:8
UINT32 Maximum3C:8
UINT32 Maximum4C:8
UINT32 Maximum5C:8
UINT32 Maximum6C:8
UINT32 Maximum7C:8
UINT32 Maximum8C:8
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum1C

[Bits 7:0] Package. Maximum Ratio Limit for 1C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum2C

[Bits 15:8] Package. Maximum Ratio Limit for 2C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum3C

[Bits 23:16] Package. Maximum Ratio Limit for 3C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum4C

[Bits 31:24] Package. Maximum Ratio Limit for 4C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum5C

[Bits 39:32] Package. Maximum Ratio Limit for 5C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum6C

[Bits 47:40] Package. Maximum Ratio Limit for 6C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum7C

[Bits 55:48] Package. Maximum Ratio Limit for 7C.

UINT32 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Maximum8C

[Bits 63:56] Package. Maximum Ratio Limit for 8C.

UINT64 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_E7_FEATURE_CONFIG_REGISTER Union Reference

Data Fields
MSR_XEON_E7_FEATURE_CONFIG_REGISTER Union Reference

#include <XeonE7Msr.h>

Data Fields

struct {
UINT32 AESConfiguration:2
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_E7_FEATURE_CONFIG

Field Documentation

UINT32 MSR_XEON_E7_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

struct { ... } MSR_XEON_E7_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_E7_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_E7_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 PROCHOT_Status:1
UINT32 ThermalStatus:1
UINT32 Reserved1:4
UINT32 VRThermAlertStatus:1
UINT32 Reserved2:1
UINT32 ElectricalDesignPointStatus:1
UINT32 Reserved3:23
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS

Field Documentation

struct { ... } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::ElectricalDesignPointStatus

[Bit 8] Electrical Design Point Status (R0).

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::PROCHOT_Status

[Bit 0] PROCHOT Status (R0).

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::ThermalStatus

[Bit 1] Thermal Status (R0).

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER::VRThermAlertStatus

[Bit 6] VR Therm Alert Status (R0).

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 AESConfiguration:2
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG

Field Documentation

UINT32 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::AESConfiguration

[Bits 1:0] AES Configuration (RW-L) Upon a successful read of this MSR, the configuration of AES instruction set availability is as follows: 11b: AES instructions are not available until next RESET. otherwise, AES instructions are available. Note, AES instruction set is not available if read is unsuccessful. If the configuration is not 01b, AES instruction can be mis-configured if a privileged agent unintentionally writes 11b.

struct { ... } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_FEATURE_CONFIG_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 FastStrings:1
UINT32 Reserved1:2
UINT32 AutomaticThermalControlCircuit:1
UINT32 Reserved2:3
UINT32 PerformanceMonitoring:1
UINT32 Reserved3:3
UINT32 BTS:1
UINT32 PEBS:1
UINT32 Reserved4:3
UINT32 EIST:1
UINT32 Reserved5:1
UINT32 MONITOR:1
UINT32 Reserved6:3
UINT32 LimitCpuidMaxval:1
UINT32 xTPR_Message_Disable:1
UINT32 Reserved7:8
UINT32 Reserved8:2
UINT32 XD:1
UINT32 Reserved9:3
UINT32 TurboModeDisable:1
UINT32 Reserved10:25
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE

Field Documentation

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::AutomaticThermalControlCircuit

[Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value is 1.

struct { ... } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::BTS

[Bit 11] Branch Trace Storage Unavailable (RO).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::EIST

[Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::FastStrings

[Bit 0] Fast-Strings Enable.

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::LimitCpuidMaxval

[Bit 22] Limit CPUID Maxval (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::MONITOR

[Bit 18] ENABLE MONITOR FSM (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::PEBS

[Bit 12] Processor Event Based Sampling Unavailable (RO).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::PerformanceMonitoring

[Bit 7] Performance Monitoring Available (R).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::TurboModeDisable

[Bit 38] Turbo Mode Disable (R/W).

UINT64 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::XD

[Bit 34] XD Bit Disable (R/W).

UINT32 MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER::xTPR_Message_Disable

[Bit 23] xTPR Message Disable (R/W).

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_LBR_SELECT_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_LBR_SELECT_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 CPL_EQ_0:1
UINT32 CPL_NEQ_0:1
UINT32 JCC:1
UINT32 NEAR_REL_CALL:1
UINT32 NEAR_IND_CALL:1
UINT32 NEAR_RET:1
UINT32 NEAR_IND_JMP:1
UINT32 NEAR_REL_JMP:1
UINT32 FAR_BRANCH:1
UINT32 Reserved1:23
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT

Field Documentation

struct { ... } MSR_XEON_PHI_LBR_SELECT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::CPL_EQ_0

[Bit 0] CPL_EQ_0.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::CPL_NEQ_0

[Bit 1] CPL_NEQ_0.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::FAR_BRANCH

[Bit 8] FAR_BRANCH.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::JCC

[Bit 2] JCC.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::NEAR_IND_CALL

[Bit 4] NEAR_IND_CALL.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::NEAR_IND_JMP

[Bit 6] NEAR_IND_JMP.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::NEAR_REL_CALL

[Bit 3] NEAR_REL_CALL.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::NEAR_REL_JMP

[Bit 7] NEAR_REL_JMP.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::NEAR_RET

[Bit 5] NEAR_RET.

UINT32 MSR_XEON_PHI_LBR_SELECT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_LBR_SELECT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 DCUHardwarePrefetcherDisable:1
UINT32 L2HardwarePrefetcherDisable:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL

Field Documentation

struct { ... } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::DCUHardwarePrefetcherDisable

[Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the L1 data cache prefetcher.

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::L2HardwarePrefetcherDisable

[Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the L2 hardware prefetcher.

UINT32 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 Reserved1:1
UINT32 UserModeMonitorAndMwait:1
UINT32 Reserved2:30
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES

Field Documentation

struct { ... } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::Uint64

All bit fields as a 64-bit value

UINT32 MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER::UserModeMonitorAndMwait

[Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and MWAIT instructions do not cause invalid-opcode exceptions when executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state other than C0 or C1, the instruction operates as if EAX indicated the C-state C1.

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 MAX_RATIO:7
UINT32 Reserved1:1
UINT32 MIN_RATIO:7
UINT32 Reserved2:17
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT

Field Documentation

struct { ... } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER::MAX_RATIO

[Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the LLC/Ring.

UINT32 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER::MIN_RATIO

[Bits 14:8] MIN_RATIO Writing to this field controls the minimum possible ratio of the LLC/Ring.

UINT32 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 Limit:3
UINT32 Reserved1:7
UINT32 IO_MWAIT:1
UINT32 Reserved2:4
UINT32 CFGLock:1
UINT32 Reserved5:10
UINT32 C1StateAutoDemotionEnable:1
UINT32 Reserved6:1
UINT32 C1StateAutoUndemotionEnable:1
UINT32 PKGC_StateAutoDemotionEnable:1
UINT32 Reserved7:2
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL

Field Documentation

struct { ... } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::C1StateAutoDemotionEnable

[Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor will conditionally demote C3/C6/C7 requests to C1 based on uncore auto-demote information.

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::C1StateAutoUndemotionEnable

[Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables Undemotion from Demoted C1.

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::CFGLock

[Bit 15] CFG Lock (R/WO).

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::IO_MWAIT

[Bit 10] I/O MWAIT Redirection Enable (R/W).

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Limit

[Bits 2:0] Package C-State Limit (R/W) The following C-state code name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No Retention 011b: C6 Retention 111b: No limit.

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::PKGC_StateAutoDemotionEnable

[Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables Package C state demotion.

UINT32 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_PLATFORM_INFO_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_PLATFORM_INFO_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 Reserved1:8
UINT32 MaximumNonTurboRatio:8
UINT32 Reserved2:12
UINT32 RatioLimit:1
UINT32 TDPLimit:1
UINT32 Reserved3:2
UINT32 Reserved4:8
UINT32 MaximumEfficiencyRatio:8
UINT32 Reserved5:16
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO

Field Documentation

struct { ... } MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::MaximumEfficiencyRatio

[Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the minimum ratio (maximum efficiency) that the processor can operates, in units of 100MHz.

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::MaximumNonTurboRatio

[Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio of the frequency that invariant TSC runs at. Frequency = ratio * 100 MHz.

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::RatioLimit

[Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When set to 1, indicates that Programmable Ratio Limits for Turbo mode is enabled, and when set to 0, indicates Programmable Ratio Limits for Turbo mode is disabled.

UINT32 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::TDPLimit

[Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When set to 1, indicates that TDP Limits for Turbo mode are programmable, and when set to 0, indicates TDP Limit for Turbo mode is not programmable.

UINT64 MSR_XEON_PHI_PLATFORM_INFO_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 Lvl2Base:16
UINT32 CStateRange:7
UINT32 Reserved3:9
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE

Field Documentation

struct { ... } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::CStateRange

[Bits 22:16] C-State Range (R/W) The IO-port block size in which IO-redirection will be executed (0-127). Should be programmed based on the number of LVLx registers existing in the chipset.

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Lvl2Base

[Bits 15:0] LVL_2 Base Address (R/W).

UINT32 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_PPIN_CTL_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_PPIN_CTL_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 LockOut:1
UINT32 Enable_PPIN:1
UINT32 Reserved1:30
UINT32 Reserved2:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL

Field Documentation

struct { ... } MSR_XEON_PHI_PPIN_CTL_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::Enable_PPIN

[Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0] will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP. Default is 0.

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::LockOut

[Bit 0] LockOut (R/WO) Set 1 to prevent further writes to MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a privileged inventory initialization agent to access MSR_PPIN. After reading MSR_PPIN, the privileged inventory initialization agent should write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and prevent unauthorized modification to MSR_PPIN_CTL.

UINT32 MSR_XEON_PHI_PPIN_CTL_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_PPIN_CTL_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 PowerUnits:4
UINT32 Reserved1:4
UINT32 EnergyStatusUnits:5
UINT32 Reserved2:3
UINT32 TimeUnits:4
UINT32 Reserved3:12
UINT32 Reserved4:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT

Field Documentation

struct { ... } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER::EnergyStatusUnits

[Bits 12:8] Package. Energy Status Units Energy related information (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an unsigned integer represented by bits 12:8. Default value is 0EH (or 61 micro-joules).

UINT32 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER::PowerUnits

[Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER::TimeUnits

[Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL Interfaces.".

UINT32 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_SMI_COUNT_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_SMI_COUNT_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 SMICount:32
UINT32 Reserved:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT

Field Documentation

struct { ... } MSR_XEON_PHI_SMI_COUNT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_SMI_COUNT_REGISTER::SMICount

[Bits 31:0] SMI Count (R/O).

UINT32 MSR_XEON_PHI_SMI_COUNT_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_SMI_COUNT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 BankSupport:32
UINT32 Reserved4:24
UINT32 TargetedSMI:1
UINT32 SMM_CPU_SVRSTR:1
UINT32 SMM_Code_Access_Chk:1
UINT32 Long_Flow_Indication:1
UINT32 Reserved3:4
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP

Field Documentation

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::BankSupport

[Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is set, that bank supports Enhanced MCA (Default all 0; does not support EMCA).

struct { ... } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Long_Flow_Indication

[Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the SMM long flow indicator is supported and a host-space interface available to SMM handler.

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::SMM_Code_Access_Chk

[Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the SMM code access restriction is supported and a host-space interface available to SMM handler.

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::SMM_CPU_SVRSTR

[Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature is supported.

UINT32 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::TargetedSMI

[Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.

UINT64 MSR_XEON_PHI_SMM_MCA_CAP_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 Reserved1:16
UINT32 TemperatureTarget:8
UINT32 TargetOffset:6
UINT32 Reserved2:2
UINT32 Reserved3:32
} Bits
UINT32 | Uint32
UINT64 | Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET

Field Documentation

struct { ... } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::TargetOffset

[Bits 29:24] Target Offset (R/W).

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::TemperatureTarget

[Bits 23:16] Temperature Target (R).

UINT32 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Uint32

All bit fields as a 32-bit value

UINT64 MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Union Reference

Data Fields
MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Union Reference

#include <XeonPhiMsr.h>

Data Fields

struct {
UINT32 Reserved:1
UINT32 MaxCoresGroup0:7
UINT32 MaxRatioLimitGroup0:8
UINT32 MaxIncrementalCoresGroup1:5
UINT32 DeltaRatioGroup1:3
UINT32 MaxIncrementalCoresGroup2:5
UINT32 DeltaRatioGroup2:3
UINT32 MaxIncrementalCoresGroup3:5
UINT32 DeltaRatioGroup3:3
UINT32 MaxIncrementalCoresGroup4:5
UINT32 DeltaRatioGroup4:3
UINT32 MaxIncrementalCoresGroup5:5
UINT32 DeltaRatioGroup5:3
UINT32 MaxIncrementalCoresGroup6:5
UINT32 DeltaRatioGroup6:3
} Bits
UINT64 Uint64

Detailed Description

MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT

Field Documentation

struct { ... } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::Bits

Individual bit fields

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::DeltaRatioGroup1

[Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned integer specifying the ratio decrement relative to the Max ratio limit to Group 0.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::DeltaRatioGroup2

[Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 1.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::DeltaRatioGroup3

[Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 2.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::DeltaRatioGroup4

[Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 3.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::DeltaRatioGroup5

[Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 4.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::DeltaRatioGroup6

[Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned integer specifying the ratio decrement relative to the Max ratio limit for Group 5.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxCoresGroup0

[Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active processor cores which operates under the maximum ratio limit for group 0.

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxIncrementalCoresGroup1

[Bits 20:16] Package. Number of Incremental Cores Added to Group 1 Group 1, which includes the specified number of additional cores plus the cores in group 0, operates under the group 1 turbo max ratio limit = "group 0 Max ratio limit" - "group ratio delta for group 1".

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxIncrementalCoresGroup2

[Bits 28:24] Package. Number of Incremental Cores Added to Group 2 Group 2, which includes the specified number of additional cores plus all the cores in group 1, operates under the group 2 turbo max ratio limit = "group 1 Max ratio limit" - "group ratio delta for group 2".

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxIncrementalCoresGroup3

[Bits 36:32] Package. Number of Incremental Cores Added to Group 3 Group 3, which includes the specified number of additional cores plus all the cores in group 2, operates under the group 3 turbo max ratio limit = "group 2 Max ratio limit" - "group ratio delta for group 3".

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxIncrementalCoresGroup4

[Bits 44:40] Package. Number of Incremental Cores Added to Group 4 Group 4, which includes the specified number of additional cores plus all the cores in group 3, operates under the group 4 turbo max ratio limit = "group 3 Max ratio limit" - "group ratio delta for group 4".

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxIncrementalCoresGroup5

[Bits 52:48] Package. Number of Incremental Cores Added to Group 5 Group 5, which includes the specified number of additional cores plus all the cores in group 4, operates under the group 5 turbo max ratio limit = "group 4 Max ratio limit" - "group ratio delta for group 5".

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxIncrementalCoresGroup6

[Bits 60:56] Package. Number of Incremental Cores Added to Group 6 Group 6, which includes the specified number of additional cores plus all the cores in group 5, operates under the group 6 turbo max ratio limit = "group 5 Max ratio limit" - "group ratio delta for group 6".

UINT32 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::MaxRatioLimitGroup0

[Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo ratio limit when the number of active cores are not more than the group 0 maximum core count.

UINT64 MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MTRR_CONTEXT Struct Reference

Data Fields
MTRR_CONTEXT Struct Reference

Data Fields

UINTN | Cr4
BOOLEAN | InterruptState
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MtrrLib/MtrrLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MTRR_LIB_ADDRESS Struct Reference

Data Fields
MTRR_LIB_ADDRESS Struct Reference

Data Fields

UINT64 | Address
UINT64 | Alignment
UINT64 | Length
MTRR_MEMORY_CACHE_TYPE | Type: 7
BOOLEAN | Visited: 1
UINT8 | Weight
UINT16 | Previous
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/MtrrLib/MtrrLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: MTRR_MEMORY_RANGE Struct Reference

Data Fields
MTRR_MEMORY_RANGE Struct Reference

Data Fields

UINT64 | BaseAddress
UINT64 | Length
MTRR_MEMORY_CACHE_TYPE | Type
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_ATTRIBUTE_TABLE Struct Reference

Data Fields
PAGE_ATTRIBUTE_TABLE Struct Reference

Data Fields

PAGE_ATTRIBUTE | Attribute
UINT64 | Length
UINT64 | AddressMask
UINTN | AddressBitOffset
UINTN | AddressBitLength
The documentation for this struct was generated from the following files:
  • UefiCpuPkg/CpuDxe/CpuPageTable.c
  • UefiCpuPkg/CpuMpPei/CpuPaging.c
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_MAP_AND_DIRECTORY_POINTER Union Reference

Data Fields
PAGE_MAP_AND_DIRECTORY_POINTER Union Reference

Data Fields

struct {
UINT64 Present:1
UINT64 ReadWrite:1
UINT64 UserSupervisor:1
UINT64 WriteThrough:1
UINT64 CacheDisabled:1
UINT64 Accessed:1
UINT64 Reserved:1
UINT64 MustBeZero:2
UINT64 Available:3
UINT64 PageTableBaseAddress:40
UINT64 AvabilableHigh:11
UINT64 Nx:1
} Bits
UINT64 Uint64
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_1G_ENTRY Union Reference

Data Fields
PAGE_TABLE_1G_ENTRY Union Reference

Data Fields

struct {
UINT64 Present:1
UINT64 ReadWrite:1
UINT64 UserSupervisor:1
UINT64 WriteThrough:1
UINT64 CacheDisabled:1
UINT64 Accessed:1
UINT64 Dirty:1
UINT64 MustBe1:1
UINT64 Global:1
UINT64 Available:3
UINT64 PAT:1
UINT64 MustBeZero:17
UINT64 PageTableBaseAddress:22
UINT64 AvabilableHigh:11
UINT64 Nx:1
} Bits
UINT64 Uint64
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_ENTRY Union Reference

Data Fields
PAGE_TABLE_ENTRY Union Reference

Data Fields

struct {
UINT64 Present:1
UINT64 ReadWrite:1
UINT64 UserSupervisor:1
UINT64 WriteThrough:1
UINT64 CacheDisabled:1
UINT64 Accessed:1
UINT64 Dirty:1
UINT64 MustBe1:1
UINT64 Global:1
UINT64 Available:3
UINT64 PAT:1
UINT64 MustBeZero:8
UINT64 PageTableBaseAddress:31
UINT64 AvabilableHigh:11
UINT64 Nx:1
} Bits
UINT64 Uint64
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_LIB_PAGING_CONTEXT Struct Reference

Data Fields
PAGE_TABLE_LIB_PAGING_CONTEXT Struct Reference

Data Fields

UINT16 | MachineType
PAGE_TABLE_LIB_PAGING_CONTEXT_DATA | ContextData
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_LIB_PAGING_CONTEXT_DATA Union Reference

Data Fields
PAGE_TABLE_LIB_PAGING_CONTEXT_DATA Union Reference

Data Fields

PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 | Ia32
PAGE_TABLE_LIB_PAGING_CONTEXT_X64 | X64
The documentation for this union was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Struct Reference

Data Fields
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32 Struct Reference

Data Fields

UINT32 | PageTableBase
UINT32 | Reserved
UINT32 | Attributes
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_LIB_PAGING_CONTEXT_X64 Struct Reference

Data Fields
PAGE_TABLE_LIB_PAGING_CONTEXT_X64 Struct Reference

Data Fields

UINT64 | PageTableBase
UINT32 | Attributes
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PAGE_TABLE_POOL Struct Reference

Data Fields
PAGE_TABLE_POOL Struct Reference

Data Fields

VOID * | NextPool
UINTN | Offset
UINTN | FreePages
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/CpuDxe/CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PROC_TRACE_DATA Struct Reference

Data Fields
PROC_TRACE_DATA Struct Reference

Data Fields

UINT32 | NumberOfProcessors
UINT8 | ProcTraceOutputScheme
UINT32 | ProcTraceMemSize
UINTN * | ThreadMemRegionTable
UINTN | AllocatedThreads
UINTN * | TopaMemArray
UINTN | TopaMemArrayCount
PROC_TRACE_PROCESSOR_DATA * | ProcessorData
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PROC_TRACE_PROCESSOR_DATA Struct Reference

Data Fields
PROC_TRACE_PROCESSOR_DATA Struct Reference

Data Fields

BOOLEAN | ProcTraceSupported
BOOLEAN | TopaSupported
BOOLEAN | SingleRangeSupported
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PROC_TRACE_TOPA_TABLE Struct Reference

Data Fields
PROC_TRACE_TOPA_TABLE Struct Reference

Data Fields

RTIT_TOPA_TABLE_ENTRY TopaEntry [MAX_TOPA_ENTRY_COUNT]
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PROCESSOR_SMM_DESCRIPTOR Struct Reference

Data Fields
PROCESSOR_SMM_DESCRIPTOR Struct Reference

Data Fields

UINT64 | Signature
UINT16 | Reserved1
UINT16 | Reserved2
UINT16 | Reserved3
UINT16 | SmmCs
UINT16 | SmmDs
UINT16 | SmmSs
UINT16 | SmmOtherSegment
UINT16 | Reserved4
UINT64 | Reserved5
UINT64 | Reserved6
UINT64 | Reserved7
UINT64 | SmmGdtPtr
UINT32 | SmmGdtSize
UINT32 | Reserved8
UINT64 | Reserved9
UINT64 | Reserved10
UINT16 | Reserved11
UINT16 | Reserved12
UINT32 | Reserved13
UINT64 | Reserved14
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: PROGRAM_CPU_REGISTER_FLAGS Struct Reference

Data Fields
PROGRAM_CPU_REGISTER_FLAGS Struct Reference

Data Fields

volatile UINTN | ConsoleLogLock
volatile UINTN | MemoryMappedLock
volatile UINT32 * | CoreSemaphoreCount
volatile UINT32 * | PackageSemaphoreCount
The documentation for this struct was generated from the following files:
  • UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h
  • UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: REGISTER_CPU_FEATURE_INFORMATION Struct Reference

Data Fields
REGISTER_CPU_FEATURE_INFORMATION Struct Reference

#include <RegisterCpuFeaturesLib.h>

Data Fields

EFI_PROCESSOR_INFORMATION | ProcessorInfo
UINT32 | DisplayFamily
UINT32 | DisplayModel
UINT32 | SteppingId
UINT32 | ProcessorType
CPUID_VERSION_INFO_ECX CpuIdVersionInfoEcx
CPUID_VERSION_INFO_EDX CpuIdVersionInfoEdx

Detailed Description

CPU Information passed into the SupportFunc and InitializeFunc of the RegisterCpuFeature() library function. This structure contains information that is commonly used during CPU feature detection and initialization.

Field Documentation

CPUID_VERSION_INFO_ECX REGISTER_CPU_FEATURE_INFORMATION::CpuIdVersionInfoEcx

Bit field structured returned in ECX from CPUID leaf CPUID_VERSION_INFO

CPUID_VERSION_INFO_EDX REGISTER_CPU_FEATURE_INFORMATION::CpuIdVersionInfoEdx

Bit field structured returned in EDX from CPUID leaf CPUID_VERSION_INFO

UINT32 REGISTER_CPU_FEATURE_INFORMATION::DisplayFamily

The Display Family of the CPU computed from CPUID leaf CPUID_VERSION_INFO

UINT32 REGISTER_CPU_FEATURE_INFORMATION::DisplayModel

The Display Model of the CPU computed from CPUID leaf CPUID_VERSION_INFO

EFI_PROCESSOR_INFORMATION REGISTER_CPU_FEATURE_INFORMATION::ProcessorInfo

The package that the CPU resides

UINT32 REGISTER_CPU_FEATURE_INFORMATION::ProcessorType

The Processor Type of the CPU computed from CPUID leaf CPUID_VERSION_INFO

UINT32 REGISTER_CPU_FEATURE_INFORMATION::SteppingId

The Stepping ID of the CPU computed from CPUID leaf CPUID_VERSION_INFO

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: RESERVED_VECTORS_DATA Struct Reference

Data Fields
RESERVED_VECTORS_DATA Struct Reference

Data Fields

SPIN_LOCK | SpinLock
UINT32 | ApicId
UINT32 | Attribute
UINTN | ExceptonHandler
UINTN | OldFlags
UINTN | OldCs
UINTN | OldIp
UINTN | ExceptionData
UINT8 | HookAfterStubHeaderCode [HOOKAFTER_STUB_SIZE]
UINTN | OldSs
UINTN | OldSp
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: RTIT_TOPA_TABLE_ENTRY Union Reference

Data Fields
RTIT_TOPA_TABLE_ENTRY Union Reference

#include <ArchitecturalMsr.h>

Data Fields

struct {
UINT32 END:1
UINT32 Reserved1:1
UINT32 INT:1
UINT32 Reserved2:1
UINT32 STOP:1
UINT32 Reserved3:1
UINT32 Size:4
UINT32 Reserved4:2
UINT32 Base:20
UINT32 BaseHi:32
} Bits
UINT64 Uint64

Detailed Description

Format of ToPA table entries.

Field Documentation

UINT32 RTIT_TOPA_TABLE_ENTRY::Base

[Bit 12:31] Output Region Base Physical Address low part. [Bit 12:31] Output Region Base Physical Address [12:63] value to match. ATTENTION: The size of the address field is determined by the processor's physical-address width (MAXPHYADDR) in bits, as reported in CPUID.80000008H:EAX[7:0]. the above part of address reserved. True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part. Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".

UINT32 RTIT_TOPA_TABLE_ENTRY::BaseHi

[Bit 32:63] Output Region Base Physical Address high part. [Bit 32:63] Output Region Base Physical Address [12:63] value to match. ATTENTION: The size of the address field is determined by the processor's physical-address width (MAXPHYADDR) in bits, as reported in CPUID.80000008H:EAX[7:0]. the above part of address reserved. True address field is [12:MAXPHYADDR-1], [MAXPHYADDR:63] is reserved part. Detail see Section 35.2.6.2, "Table of Physical Addresses (ToPA)".

struct { ... } RTIT_TOPA_TABLE_ENTRY::Bits

Individual bit fields

UINT32 RTIT_TOPA_TABLE_ENTRY::END

[Bit 0] END. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".

UINT32 RTIT_TOPA_TABLE_ENTRY::INT

[Bit 2] INT. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".

UINT32 RTIT_TOPA_TABLE_ENTRY::Size

[Bit 6:9] Indicates the size of the associated output region. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".

UINT32 RTIT_TOPA_TABLE_ENTRY::STOP

[Bit 4] STOP. See Section 35.2.6.2, "Table of Physical Addresses (ToPA)".

UINT64 RTIT_TOPA_TABLE_ENTRY::Uint64

All bit fields as a 64-bit value

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_COMMUNICATE_HEADER_32 Struct Reference

Data Fields
SMM_COMMUNICATE_HEADER_32 Struct Reference

Data Fields

EFI_GUID | HeaderGuid
UINT32 | MessageLength
UINT8 | Data [1]
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_COMMUNICATE_HEADER_64 Struct Reference

Data Fields
SMM_COMMUNICATE_HEADER_64 Struct Reference

Data Fields

EFI_GUID | HeaderGuid
UINT64 | MessageLength
UINT8 | Data [1]
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_CPU_DATA_BLOCK Struct Reference

Data Fields
SMM_CPU_DATA_BLOCK Struct Reference

#include <PiSmmCpuDxeSmm.h>

Data Fields

SPIN_LOCK * | Busy
volatile EFI_AP_PROCEDURE | Procedure
volatile VOID * | Parameter
volatile UINT32 * | Run
volatile BOOLEAN * | Present

Detailed Description

The type of SMM CPU Information

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_CPU_PRIVATE_DATA Struct Reference

Data Fields
SMM_CPU_PRIVATE_DATA Struct Reference

Data Fields

UINTN | Signature
EFI_HANDLE | SmmCpuHandle
EFI_PROCESSOR_INFORMATION * | ProcessorInfo
SMM_CPU_OPERATION * | Operation
UINTN * | CpuSaveStateSize
VOID ** | CpuSaveState
EFI_SMM_RESERVED_SMRAM_REGION | SmmReservedSmramRegion [1]
EFI_SMM_ENTRY_CONTEXT | SmmCoreEntryContext
EFI_SMM_ENTRY_POINT | SmmCoreEntry
EFI_SMM_CONFIGURATION_PROTOCOL | SmmConfiguration
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_CPU_SEMAPHORE_CPU Struct Reference

Data Fields
SMM_CPU_SEMAPHORE_CPU Struct Reference

#include <PiSmmCpuDxeSmm.h>

Data Fields

SPIN_LOCK * | Busy
volatile UINT32 * | Run
volatile BOOLEAN * | Present

Detailed Description

All semaphores for each processor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_CPU_SEMAPHORE_GLOBAL Struct Reference

Data Fields
SMM_CPU_SEMAPHORE_GLOBAL Struct Reference

#include <PiSmmCpuDxeSmm.h>

Data Fields

volatile UINT32 * | Counter
volatile BOOLEAN * | InsideSmm
volatile BOOLEAN * | AllCpusInSync
SPIN_LOCK * | PFLock
SPIN_LOCK * | CodeAccessCheckLock

Detailed Description

All global semaphores' pointer

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_CPU_SEMAPHORES Struct Reference

Data Fields
SMM_CPU_SEMAPHORES Struct Reference

#include <PiSmmCpuDxeSmm.h>

Data Fields

SMM_CPU_SEMAPHORE_GLOBAL | SemaphoreGlobal
SMM_CPU_SEMAPHORE_CPU | SemaphoreCpu

Detailed Description

All semaphores' information

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_DISPATCHER_MP_SYNC_DATA Struct Reference

Data Fields
SMM_DISPATCHER_MP_SYNC_DATA Struct Reference

Data Fields

SMM_CPU_DATA_BLOCK * | CpuData
volatile UINT32 * | Counter
volatile UINT32 | BspIndex
volatile BOOLEAN * | InsideSmm
volatile BOOLEAN * | AllCpusInSync
volatile SMM_CPU_SYNC_MODE | EffectiveSyncMode
volatile BOOLEAN | SwitchBsp
volatile BOOLEAN * | CandidateBsp
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_PROFILE_ENTRY Struct Reference

Data Fields
SMM_PROFILE_ENTRY Struct Reference

Data Fields

UINT64 | SmiNum
UINT64 | CpuNum
UINT64 | ApicId
UINT64 | ErrorCode
UINT64 | Instruction
UINT64 | Address
UINT64 | SmiCmd
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMM_PROFILE_HEADER Struct Reference

Data Fields
SMM_PROFILE_HEADER Struct Reference

Data Fields

UINT64 | HeaderSize
UINT64 | MaxDataEntries
UINT64 | MaxDataSize
UINT64 | CurDataEntries
UINT64 | CurDataSize
UINT64 | TsegStart
UINT64 | TsegSize
UINT64 | NumSmis
UINT64 | NumCpus
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMRAM_SAVE_STATE_IOMISC Union Reference

Data Fields
SMRAM_SAVE_STATE_IOMISC Union Reference

#include <SmramSaveStateMap.h>

Data Fields

struct {
UINT32 SmiFlag:1
UINT32 Length:3
UINT32 Type:4
UINT32 Reserved1:8
UINT32 Port:16
} Bits
UINT32 Uint32

Detailed Description

SMRAM Save State Map IOMisc structure

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/SmramSaveStateMap.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMRAM_SAVE_STATE_MAP Union Reference

Data Fields
SMRAM_SAVE_STATE_MAP Union Reference

#include <SmramSaveStateMap.h>

Data Fields

SMRAM_SAVE_STATE_MAP32 | x86
SMRAM_SAVE_STATE_MAP64 | x64

Detailed Description

Union of 32-bit and 64-bit SMRAM Save State Maps

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/SmramSaveStateMap.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMRAM_SAVE_STATE_MAP32 Struct Reference

Data Fields
SMRAM_SAVE_STATE_MAP32 Struct Reference

#include <SmramSaveStateMap.h>

Data Fields

UINT16 | _ES
UINT8 | Reserved [14]
UINT16 | _CS
UINT8 | Reserved1 [14]
UINT16 | _SS
UINT8 | Reserved2 [14]
UINT16 | _DS
UINT8 | Reserved3 [14]
UINT16 | _FS
UINT8 | Reserved4 [14]
UINT16 | _GS
UINT8 | Reserved5 [14]
UINT8 | Reserved6 [16]
UINT16 | _LDTR
UINT16 | _LDTR_ATTRIBUTE
UINT32 | _LDTR_LIMIT
UINT64 | _LDTR_BASE
UINT8 | Reserved7 [4]
UINT16 | _IDTR_LIMIT
UINT8 | Reserved8 [2]
UINT64 | _IDTR_BASE
UINT16 | _TR
UINT16 | _TR_ATTRIBUTE
UINT32 | _TR_LIMIT
UINT64 | _TR_BASE
UINT64 | IoRestartRip
UINT64 | IoRestartRcx
UINT64 | IoRestartRsi
UINT64 | IoRestartRdi
UINT32 | IoTrapOffset
UINT32 | LocalSmiStatus
UINT8 | IORestart
UINT8 | AutoHALTRestart
UINT8 | NmiMask
UINT8 | Reserved9 [5]
UINT64 | IA32_EFER
UINT64 | SvmState
UINT64 | GVmcbPA
UINT64 | SvmVIC
UINT8 | Reserved10 [12]
UINT32 | SMMRevId
UINT32 | SMBASE
UINT8 | Reserved11 [28]
UINT64 | GPAT
UINT64 | HEFER
UINT64 | HCR4
UINT64 | NCR3
UINT64 | HCR0
UINT64 | _CR4
UINT64 | _CR3
UINT64 | _CR0
UINT64 | _DR7
UINT64 | _DR6
UINT64 | _EFLAGS
UINT64 | _EIP
UINT64 | _R15
UINT64 | _R14
UINT64 | _R13
UINT64 | _R12
UINT64 | _R11
UINT64 | _R10
UINT64 | _R9
UINT64 | _R8
UINT64 | _EDI
UINT64 | _ESI
UINT64 | _EBP
UINT64 | _ESP
UINT64 | _EBX
UINT64 | _EDX
UINT64 | _ECX
UINT64 | _EAX

Detailed Description

32-bit SMRAM Save State Map

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/SmramSaveStateMap.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SMRAM_SAVE_STATE_MAP64 Struct Reference

Data Fields
SMRAM_SAVE_STATE_MAP64 Struct Reference

Data Fields

UINT16 | _ES
UINT8 | Reserved [14]
UINT16 | _CS
UINT8 | Reserved1 [14]
UINT16 | _SS
UINT8 | Reserved2 [14]
UINT16 | _DS
UINT8 | Reserved3 [14]
UINT16 | _FS
UINT8 | Reserved4 [14]
UINT16 | _GS
UINT8 | Reserved5 [14]
UINT8 | Reserved6 [16]
UINT16 | _LDTR
UINT16 | _LDTR_ATTRIBUTE
UINT32 | _LDTR_LIMIT
UINT64 | _LDTR_BASE
UINT8 | Reserved7 [4]
UINT16 | _IDTR_LIMIT
UINT8 | Reserved8 [2]
UINT64 | _IDTR_BASE
UINT16 | _TR
UINT16 | _TR_ATTRIBUTE
UINT32 | _TR_LIMIT
UINT64 | _TR_BASE
UINT64 | IoRestartRip
UINT64 | IoRestartRcx
UINT64 | IoRestartRsi
UINT64 | IoRestartRdi
UINT32 | IoTrapOffset
UINT32 | LocalSmiStatus
UINT8 | IORestart
UINT8 | AutoHALTRestart
UINT8 | NmiMask
UINT8 | Reserved9 [5]
UINT64 | IA32_EFER
UINT64 | SvmState
UINT64 | GVmcbPA
UINT64 | SvmVIC
UINT8 | Reserved10 [12]
UINT32 | SMMRevId
UINT32 | SMBASE
UINT8 | Reserved11 [28]
UINT64 | GPAT
UINT64 | HEFER
UINT64 | HCR4
UINT64 | NCR3
UINT64 | HCR0
UINT64 | _CR4
UINT64 | _CR3
UINT64 | _CR0
UINT64 | _DR7
UINT64 | _DR6
UINT64 | _RFLAGS
UINT64 | _RIP
UINT64 | _R15
UINT64 | _R14
UINT64 | _R13
UINT64 | _R12
UINT64 | _R11
UINT64 | _R10
UINT64 | _R9
UINT64 | _R8
UINT64 | _RDI
UINT64 | _RSI
UINT64 | _RBP
UINT64 | _RSP
UINT64 | _RBX
UINT64 | _RDX
UINT64 | _RCX
UINT64 | _RAX
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/SmramSaveStateMap.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: SOFTWARE_STM_HEADER Struct Reference

Data Fields
SOFTWARE_STM_HEADER Struct Reference

Data Fields

UINT8 | StmSpecVerMajor
UINT8 | StmSpecVerMinor
UINT16 | Reserved
UINT32 | StaticImageSize
UINT32 | PerProcDynamicMemorySize
UINT32 | AdditionalDynamicMemorySize
STM_FEAT | StmFeatures
UINT32 | NumberOfRevIDs
UINT32 | StmSmmRevID [1]

Field Documentation

UINT16 SOFTWARE_STM_HEADER::Reserved

Must be zero

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_ADDRESS_LOOKUP_DESCRIPTOR Struct Reference

Data Fields
STM_ADDRESS_LOOKUP_DESCRIPTOR Struct Reference

#include <StmApi.h>

Data Fields

UINT64 | InterruptedGuestVirtualAddress
UINT32 | Length
UINT64 | InterruptedCr3
UINT64 | InterruptedEptp
UINT32 | MapToSmmGuest:2
UINT32 | InterruptedCr4Pae:1
UINT32 | InterruptedCr4Pse:1
UINT32 | InterruptedIa32eMode:1
UINT32 | Reserved1:27
UINT32 | Reserved2
UINT64 | PhysicalAddress
UINT64 | SmmGuestVirtualAddress

Detailed Description

STM Lookup Address Range Descriptor for #STM_API_ADDRESS_LOOKUP VMCALL

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_EVENT_LOG_MANAGEMENT_REQUEST Struct Reference

Data Fields
STM_EVENT_LOG_MANAGEMENT_REQUEST Struct Reference

#include <StmApi.h>

Data Fields

UINT32 SubFunctionIndex
union {
struct {
UINT32 PageCount
UINT64 Pages []
} LogBuffer
UINT32 EventEnableBitmap
} Data

Detailed Description

STM Event Log Management Request for #STM_API_MANAGE_EVENT_LOG VMCALL

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_FEAT Struct Reference

Data Fields
STM_FEAT Struct Reference

#include <StmApi.h>

Data Fields

UINT32 | Intel64ModeSupported:1
UINT32 | EptSupported:1

bitfield

UINT32 | Reserved:30

bitfield

Detailed Description

STM Header Structures

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_HEADER Struct Reference

Data Fields
STM_HEADER Struct Reference

Data Fields

MSEG_HEADER | HwStmHdr
SOFTWARE_STM_HEADER | SwStmHdr
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_LOG_ENTRY Struct Reference

Data Fields
STM_LOG_ENTRY Struct Reference

Data Fields

LOG_ENTRY_HEADER | Hdr
LOG_ENTRY_DATA | Data
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_MAP_ADDRESS_RANGE_DESCRIPTOR Struct Reference

Data Fields
STM_MAP_ADDRESS_RANGE_DESCRIPTOR Struct Reference

#include <StmApi.h>

Data Fields

UINT64 | PhysicalAddress
UINT64 | VirtualAddress
UINT32 | PageCount
UINT32 | PatCacheType

Detailed Description

STM Map Address Range Descriptor for #STM_API_MAP_ADDRESS_RANGE VMCALL

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_PCI_DEVICE_PATH_NODE Struct Reference

Data Fields
STM_PCI_DEVICE_PATH_NODE Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

UINT8 | Type
UINT8 | Subtype
UINT16 | Length
UINT8 | PciFunction
UINT8 | PciDevice

Detailed Description

STM PCI Device Path node used for the PciDevicePath field of STM_RSC_PCI_CFG_DESC

Field Documentation

UINT16 STM_PCI_DEVICE_PATH_NODE::Length

sizeof(STM_PCI_DEVICE_PATH_NODE) which is 6

UINT8 STM_PCI_DEVICE_PATH_NODE::Subtype

Must be 1, indicating PCI

UINT8 STM_PCI_DEVICE_PATH_NODE::Type

Must be 1, indicating Hardware Device Path

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_PROTECTION_EXCEPTION_HANDLER Struct Reference

Data Fields
STM_PROTECTION_EXCEPTION_HANDLER Struct Reference

#include <StmApi.h>

Data Fields

UINT64 | SpeRip
UINT64 | SpeRsp
UINT16 | SpeSs
UINT16 | PageViolationException:1
UINT16 | MsrViolationException:1
UINT16 | RegisterViolationException:1
UINT16 | IoViolationException:1
UINT16 | PciViolationException:1
UINT16 | Reserved1:11
UINT32 | Reserved2

Detailed Description

TXT Pocessor SMM Descriptor (PSD) structures

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_PROTECTION_EXCEPTION_STACK_FRAME Union Reference

Data Fields
STM_PROTECTION_EXCEPTION_STACK_FRAME Union Reference

Data Fields

STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 * | Ia32StackFrame
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 * | X64StackFrame
The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 Struct Reference

Data Fields
STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 Struct Reference

#include <StmApi.h>

Data Fields

UINT32 | Rdi
UINT32 | Rsi
UINT32 | Rbp
UINT32 | Rdx
UINT32 | Rcx
UINT32 | Rbx
UINT32 | Rax
UINT32 | Cr3
UINT32 | Cr2
UINT32 | Cr0
UINT32 | VmcsExitInstructionInfo
UINT32 | VmcsExitInstructionLength
UINT64 | VmcsExitQualification
UINT32 | ErrorCode
UINT32 | Rip
UINT32 | Cs
UINT32 | Rflags
UINT32 | Rsp
UINT32 | Ss

Detailed Description

STM Protection Exception Stack Frame Structures

Field Documentation

UINT32 STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32::ErrorCode

An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 Struct Reference

Data Fields
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64 Struct Reference

Data Fields

UINT64 | R15
UINT64 | R14
UINT64 | R13
UINT64 | R12
UINT64 | R11
UINT64 | R10
UINT64 | R9
UINT64 | R8
UINT64 | Rdi
UINT64 | Rsi
UINT64 | Rbp
UINT64 | Rdx
UINT64 | Rcx
UINT64 | Rbx
UINT64 | Rax
UINT64 | Cr8
UINT64 | Cr3
UINT64 | Cr2
UINT64 | Cr0
UINT64 | VmcsExitInstructionInfo
UINT64 | VmcsExitInstructionLength
UINT64 | VmcsExitQualification
UINT64 | ErrorCode
UINT64 | Rip
UINT64 | Cs
UINT64 | Rflags
UINT64 | Rsp
UINT64 | Ss

Field Documentation

UINT64 STM_PROTECTION_EXCEPTION_STACK_FRAME_X64::ErrorCode

An TXT_SMM_PROTECTION_EXCEPTION_TYPE num value

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_REGISTER_VIOLATION_DESC Struct Reference

Data Fields
STM_REGISTER_VIOLATION_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT32 | RegisterType
UINT32 | Reserved
UINT64 | ReadMask
UINT64 | WriteMask

Detailed Description

STM Register Volation Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC Union Reference

Data Fields
STM_RSC Union Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Header
STM_RSC_END | End
STM_RSC_MEM_DESC | Mem
STM_RSC_IO_DESC | Io
STM_RSC_MMIO_DESC | Mmio
STM_RSC_MSR_DESC | Msr
STM_RSC_PCI_CFG_DESC | PciCfg
STM_RSC_TRAPPED_IO_DESC | TrappedIo
STM_RSC_ALL_RESOURCES_DESC | All
STM_REGISTER_VIOLATION_DESC | RegisterViolation

Detailed Description

Union of all STM resource types

The documentation for this union was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_ALL_RESOURCES_DESC Struct Reference

Data Fields
STM_RSC_ALL_RESOURCES_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER Hdr

Detailed Description

STM Resource All Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_DESC_HEADER Struct Reference

Data Fields
STM_RSC_DESC_HEADER Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

UINT32 | RscType
UINT16 | Length
UINT16 | ReturnStatus:1
UINT16 | Reserved:14
UINT16 | IgnoreResource:1

Detailed Description

STM Resource Descriptor Header

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_END Struct Reference

Data Fields
STM_RSC_END Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT64 | ResourceListContinuation

Detailed Description

STM Resource End Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_IO_DESC Struct Reference

Data Fields
STM_RSC_IO_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT16 | Base
UINT16 | Length
UINT32 | Reserved

Detailed Description

STM Resource I/O Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_MEM_DESC Struct Reference

Data Fields
STM_RSC_MEM_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT64 | Base
UINT64 | Length
UINT32 | RWXAttributes:3
UINT32 | Reserved:29
UINT32 | Reserved_2

Detailed Description

STM Resource Memory Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_MMIO_DESC Struct Reference

Data Fields
STM_RSC_MMIO_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT64 | Base
UINT64 | Length
UINT32 | RWXAttributes:3
UINT32 | Reserved:29
UINT32 | Reserved_2

Detailed Description

STM Resource MMIO Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_MSR_DESC Struct Reference

Data Fields
STM_RSC_MSR_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT32 | MsrIndex
UINT32 | KernelModeProcessing:1
UINT32 | Reserved:31
UINT64 | ReadMask
UINT64 | WriteMask

Detailed Description

STM Resource MSR Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_PCI_CFG_DESC Struct Reference

Data Fields
STM_RSC_PCI_CFG_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT16 | RWAttributes:2
UINT16 | Reserved:14
UINT16 | Base
UINT16 | Length
UINT8 | OriginatingBusNumber
UINT8 | LastNodeIndex
STM_PCI_DEVICE_PATH_NODE | PciDevicePath [1]

Detailed Description

STM Resource PCI Configuration Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_RSC_TRAPPED_IO_DESC Struct Reference

Data Fields
STM_RSC_TRAPPED_IO_DESC Struct Reference

#include <StmResourceDescriptor.h>

Data Fields

STM_RSC_DESC_HEADER | Hdr
UINT16 | Base
UINT16 | Length
UINT16 | In:1
UINT16 | Out:1
UINT16 | Api:1
UINT16 | Reserved1:13
UINT16 | Reserved2

Detailed Description

STM Resource Trapped I/O Descriptor

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmResourceDescriptor.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_SMM_ENTRY_STATE Struct Reference

Data Fields
STM_SMM_ENTRY_STATE Struct Reference

Data Fields

UINT8 | ExecutionDisableOutsideSmrr:1
UINT8 | Intel64Mode:1
UINT8 | Cr4Pae: 1
UINT8 | Cr4Pse: 1
UINT8 | Reserved1: 4
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_SMM_RESUME_STATE Struct Reference

Data Fields
STM_SMM_RESUME_STATE Struct Reference

Data Fields

UINT8 | SmramToVmcsRestoreRequired: 1
UINT8 | ReinitializeVmcsRequired: 1

BIOS restore hint

UINT8 | Reserved2: 6

BIOS request

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_SMM_STATE Struct Reference

Data Fields
STM_SMM_STATE Struct Reference

Data Fields

UINT8 | DomainType: 4
UINT8 | XStatePolicy: 2

STM input to BIOS on each SMI

UINT8 | EptEnabled: 1

STM input to BIOS on each SMI

UINT8 | Reserved3: 1
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR Struct Reference

Data Fields
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR Struct Reference

#include <StmApi.h>

Data Fields

UINT64 | VirtualAddress
UINT32 | Length

Detailed Description

STM Unmap Address Range Descriptor for #STM_API_UNMAP_ADDRESS_RANGE VMCALL

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: STM_VMCS_DATABASE_REQUEST Struct Reference

Data Fields
STM_VMCS_DATABASE_REQUEST Struct Reference

#include <StmApi.h>

Data Fields

UINT64 | VmcsPhysPointer
UINT32 | DomainType:4
UINT32 | XStatePolicy:2
UINT32 | DegradationPolicy:4
UINT32 | Reserved1:22
UINT32 | AddOrRemove

Detailed Description

STM VMCS Database Request for #STM_API_MANAGE_VMCS_DATABASE VMCALL

Field Documentation

UINT32 STM_VMCS_DATABASE_REQUEST::Reserved1

Must be 0

UINT64 STM_VMCS_DATABASE_REQUEST::VmcsPhysPointer

bits 11:0 are reserved and must be 0

The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: TXT_PROCESSOR_SMM_DESCRIPTOR Struct Reference

Data Fields
TXT_PROCESSOR_SMM_DESCRIPTOR Struct Reference

Data Fields

UINT64 | Signature
UINT16 | Size
UINT8 | SmmDescriptorVerMajor
UINT8 | SmmDescriptorVerMinor
UINT32 | LocalApicId
STM_SMM_ENTRY_STATE | SmmEntryState
STM_SMM_RESUME_STATE | SmmResumeState
STM_SMM_STATE | StmSmmState
UINT8 | Reserved4
UINT16 | SmmCs
UINT16 | SmmDs
UINT16 | SmmSs
UINT16 | SmmOtherSegment
UINT16 | SmmTr
UINT16 | Reserved5
UINT64 | SmmCr3
UINT64 | SmmStmSetupRip
UINT64 | SmmStmTeardownRip
UINT64 | SmmSmiHandlerRip
UINT64 | SmmSmiHandlerRsp
UINT64 | SmmGdtPtr
UINT32 | SmmGdtSize
UINT32 | RequiredStmSmmRevId
STM_PROTECTION_EXCEPTION_HANDLER | StmProtectionExceptionHandler
UINT64 | Reserved6
UINT64 | BiosHwResourceRequirementsPtr
UINT64 | AcpiRsdp
UINT8 | PhysicalAddressBits
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Register/StmApi.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: VARIABLE_MTRR Struct Reference

Data Fields
VARIABLE_MTRR Struct Reference

Data Fields

UINT64 | BaseAddress
UINT64 | Length
UINT64 | Type
UINT32 | Msr
BOOLEAN | Valid
BOOLEAN | Used
The documentation for this struct was generated from the following file:
  • UefiCpuPkg/Include/Library/MtrrLib.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Structure Index

Data Structure Index
A | C | E | F | I | L | M | P | R | S | T | V | _
A
ACPI_CPU_DATA
ACPI_CPU_DATA_EX
AMD_X64_FORMAT
C
CPU_AP_DATA
CPU_EXCHANGE_ROLE_INFO
CPU_FEATURES_DATA
CPU_FEATURES_ENTRY
CPU_FEATURES_INIT_ORDER
CPU_HOT_PLUG_DATA
CPU_INFO_IN_HOB
CPU_MICROCODE_DATE
CPU_MICROCODE_EXTENDED_TABLE
CPU_MICROCODE_EXTENDED_TABLE_HEADER
CPU_MICROCODE_HEADER
CPU_MICROCODE_PROCESSOR_SIGNATURE
CPU_REGISTER_TABLE
CPU_REGISTER_TABLE_ENTRY
CPU_SMM_SAVE_STATE_IO_WIDTH
CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
CPU_SMM_SAVE_STATE_REGISTER_RANGE
CPU_STATUS_CODE_TEMPLATE
CPU_STATUS_INFORMATION
CPU_VOLATILE_REGISTERS
CPUID_AMD_EXTENDED_CPU_SIG_EAX
CPUID_AMD_EXTENDED_CPU_SIG_EBX
CPUID_AMD_EXTENDED_CPU_SIG_ECX
CPUID_AMD_EXTENDED_CPU_SIG_EDX
CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
CPUID_BRAND_STRING_DATA
CPUID_CACHE_INFO_CACHE_TLB
CPUID_CACHE_PARAMS_EAX
CPUID_CACHE_PARAMS_EBX
CPUID_CACHE_PARAMS_EDX
CPUID_EXTENDED_CACHE_INFO_ECX
CPUID_EXTENDED_CPU_SIG_ECX
CPUID_EXTENDED_CPU_SIG_EDX
CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
CPUID_EXTENDED_STATE_SUB_LEAF_EAX
CPUID_EXTENDED_STATE_SUB_LEAF_ECX
CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
CPUID_EXTENDED_TOPOLOGY_EAX
CPUID_EXTENDED_TOPOLOGY_EBX
CPUID_EXTENDED_TOPOLOGY_ECX
CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
CPUID_MEMORY_ENCRYPTION_INFO_EAX
CPUID_MEMORY_ENCRYPTION_INFO_EBX
CPUID_MEMORY_ENCRYPTION_INFO_ECX
CPUID_MEMORY_ENCRYPTION_INFO_EDX
CPUID_MONITOR_MWAIT_EAX
CPUID_MONITOR_MWAIT_EBX
CPUID_MONITOR_MWAIT_ECX
CPUID_MONITOR_MWAIT_EDX
CPUID_PROCESSOR_FREQUENCY_EAX
CPUID_PROCESSOR_FREQUENCY_EBX
CPUID_PROCESSOR_FREQUENCY_ECX
CPUID_SOC_VENDOR_BRAND_STRING_DATA
CPUID_SOC_VENDOR_MAIN_LEAF_EBX
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
CPUID_THERMAL_POWER_MANAGEMENT_EAX
CPUID_THERMAL_POWER_MANAGEMENT_EBX
CPUID_THERMAL_POWER_MANAGEMENT_ECX
CPUID_VERSION_INFO_EAX
CPUID_VERSION_INFO_EBX
CPUID_VERSION_INFO_ECX
CPUID_VERSION_INFO_EDX
CPUID_VIR_PHY_ADDRESS_SIZE_EAX
E
EFI_CONFIGURATION_TABLE64
EFI_SMM_COMMUNICATION_CONTEXT
EFI_SMM_SYSTEM_TABLE2_64
ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC
ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION
ENTRY_EVT_LOG_INVALID_PARAM
ENTRY_EVT_LOG_STARTED
ENTRY_EVT_LOG_STOPPED
ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED
ENTRY_EVT_MLE_RSC_PROT_DENIED
ENTRY_EVT_MLE_RSC_PROT_GRANTED
ENTRY_EVT_MLE_RSC_UNPROT
ENTRY_EVT_MLE_RSC_UNPROT_ERROR
EXCEPTION0_STUB_HEADER
EXCEPTION_HANDLER_CONTEXT
EXCEPTION_HANDLER_DATA
EXCEPTION_HANDLER_TEMPLATE_MAP
F
FIXED_MTRR
I
IA32_GDT
IA32_VMX_MISC_REGISTER
L
LOCAL_APIC_DCR
LOCAL_APIC_ICR_HIGH
LOCAL_APIC_ICR_LOW
LOCAL_APIC_LVT_LINT
LOCAL_APIC_LVT_TIMER
LOCAL_APIC_MSI_ADDRESS
LOCAL_APIC_MSI_DATA
LOCAL_APIC_SVR
LOCAL_APIC_VERSION
LOG_ENTRY_DATA
LOG_ENTRY_HEADER
M
MEMORY_PROTECTION_RANGE
MEMORY_RANGE
MP_ASSEMBLY_ADDRESS_MAP
MP_CPU_EXCHANGE_INFO
MSEG_HEADER
MSR_ATOM_BBL_CR_CTL3_REGISTER
MSR_ATOM_EBL_CR_POWERON_REGISTER
MSR_ATOM_FSB_FREQ_REGISTER
MSR_ATOM_IA32_MISC_ENABLE_REGISTER
MSR_ATOM_PEBS_ENABLE_REGISTER
MSR_ATOM_PERF_STATUS_REGISTER
MSR_ATOM_PLATFORM_ID_REGISTER
MSR_ATOM_THERM2_CTL_REGISTER
MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER
MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER
MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER
MSR_CORE2_EBL_CR_POWERON_REGISTER
MSR_CORE2_FEATURE_CONTROL_REGISTER
MSR_CORE2_FSB_FREQ_REGISTER
MSR_CORE2_IA32_MISC_ENABLE_REGISTER
MSR_CORE2_PEBS_ENABLE_REGISTER
MSR_CORE2_PERF_CAPABILITIES_REGISTER
MSR_CORE2_PERF_STATUS_REGISTER
MSR_CORE2_PLATFORM_ID_REGISTER
MSR_CORE2_SMRR_PHYSBASE_REGISTER
MSR_CORE2_SMRR_PHYSMASK_REGISTER
MSR_CORE2_THERM2_CTL_REGISTER
MSR_CORE_BBL_CR_CTL3_REGISTER
MSR_CORE_EBL_CR_POWERON_REGISTER
MSR_CORE_FSB_FREQ_REGISTER
MSR_CORE_IA32_EFER_REGISTER
MSR_CORE_IA32_MISC_ENABLE_REGISTER
MSR_CORE_THERM2_CTL_REGISTER
MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
MSR_GOLDMONT_FEATURE_CONTROL_REGISTER
MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER
MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER
MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER
MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER
MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
MSR_GOLDMONT_LBR_SELECT_REGISTER
MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER
MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
MSR_GOLDMONT_PEBS_ENABLE_REGISTER
MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
MSR_GOLDMONT_PKGC3_IRTL_REGISTER
MSR_GOLDMONT_PKGC_IRTL1_REGISTER
MSR_GOLDMONT_PKGC_IRTL2_REGISTER
MSR_GOLDMONT_PLATFORM_INFO_REGISTER
MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
MSR_GOLDMONT_POWER_CTL_REGISTER
MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER
MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER
MSR_GOLDMONT_SMM_MCA_CAP_REGISTER
MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER
MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
MSR_HASWELL_E_ERROR_CONTROL_REGISTER
MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER
MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
MSR_HASWELL_LBR_SELECT_REGISTER
MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_HASWELL_PKGC_IRTL1_REGISTER
MSR_HASWELL_PKGC_IRTL2_REGISTER
MSR_HASWELL_PLATFORM_INFO_REGISTER
MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
MSR_HASWELL_SMM_MCA_CAP_REGISTER
MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
MSR_IA32_APIC_BASE_REGISTER
MSR_IA32_BIOS_SIGN_ID_REGISTER
MSR_IA32_BNDCFGS_REGISTER
MSR_IA32_CLOCK_MODULATION_REGISTER
MSR_IA32_DCA_0_CAP_REGISTER
MSR_IA32_DEBUG_INTERFACE_REGISTER
MSR_IA32_DEBUGCTL_REGISTER
MSR_IA32_EFER_REGISTER
MSR_IA32_ENERGY_PERF_BIAS_REGISTER
MSR_IA32_FEATURE_CONTROL_REGISTER
MSR_IA32_FIXED_CTR_CTRL_REGISTER
MSR_IA32_HWP_CAPABILITIES_REGISTER
MSR_IA32_HWP_INTERRUPT_REGISTER
MSR_IA32_HWP_REQUEST_PKG_REGISTER
MSR_IA32_HWP_REQUEST_REGISTER
MSR_IA32_HWP_STATUS_REGISTER
MSR_IA32_L2_QOS_CFG_REGISTER
MSR_IA32_L3_QOS_CFG_REGISTER
MSR_IA32_MC_CTL2_REGISTER
MSR_IA32_MCG_CAP_REGISTER
MSR_IA32_MCG_EXT_CTL_REGISTER
MSR_IA32_MCG_STATUS_REGISTER
MSR_IA32_MISC_ENABLE_REGISTER
MSR_IA32_MTRR_DEF_TYPE_REGISTER
MSR_IA32_MTRR_PHYSBASE_REGISTER
MSR_IA32_MTRR_PHYSMASK_REGISTER
MSR_IA32_MTRRCAP_REGISTER
MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
MSR_IA32_PAT_REGISTER
MSR_IA32_PEBS_ENABLE_REGISTER
MSR_IA32_PERF_CAPABILITIES_REGISTER
MSR_IA32_PERF_CTL_REGISTER
MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
MSR_IA32_PERF_STATUS_REGISTER
MSR_IA32_PERFEVTSEL_REGISTER
MSR_IA32_PKG_HDC_CTL_REGISTER
MSR_IA32_PLATFORM_ID_REGISTER
MSR_IA32_PM_CTL1_REGISTER
MSR_IA32_PM_ENABLE_REGISTER
MSR_IA32_PQR_ASSOC_REGISTER
MSR_IA32_QM_CTR_REGISTER
MSR_IA32_QM_EVTSEL_REGISTER
MSR_IA32_RTIT_ADDR_REGISTER
MSR_IA32_RTIT_CR3_MATCH_REGISTER
MSR_IA32_RTIT_CTL_REGISTER
MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
MSR_IA32_RTIT_STATUS_REGISTER
MSR_IA32_SGX_SVN_STATUS_REGISTER
MSR_IA32_SMM_MONITOR_CTL_REGISTER
MSR_IA32_SMRR_PHYSBASE_REGISTER
MSR_IA32_SMRR_PHYSMASK_REGISTER
MSR_IA32_SYSENTER_CS_REGISTER
MSR_IA32_THERM_INTERRUPT_REGISTER
MSR_IA32_THERM_STATUS_REGISTER
MSR_IA32_TSC_AUX_REGISTER
MSR_IA32_VMX_BASIC_REGISTER
MSR_IA32_XSS_REGISTER
MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER
MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER
MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER
MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
MSR_IVY_BRIDGE_PPIN_CTL_REGISTER
MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER
MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER
MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
MSR_NEHALEM_LBR_SELECT_REGISTER
MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
MSR_NEHALEM_PEBS_ENABLE_REGISTER
MSR_NEHALEM_PEBS_LD_LAT_REGISTER
MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER
MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_NEHALEM_PLATFORM_ID_REGISTER
MSR_NEHALEM_PLATFORM_INFO_REGISTER
MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
MSR_NEHALEM_POWER_CTL_REGISTER
MSR_NEHALEM_SMI_COUNT_REGISTER
MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
MSR_P6_APIC_BASE_REGISTER
MSR_P6_BBL_CR_ADDR_REGISTER
MSR_P6_BBL_CR_CTL3_REGISTER
MSR_P6_BBL_CR_CTL_REGISTER
MSR_P6_DEBUGCTLMSR_REGISTER
MSR_P6_EBL_CR_POWERON_REGISTER
MSR_P6_IA32_PLATFORM_ID_REGISTER
MSR_P6_MC_STATUS_REGISTER
MSR_P6_MTRRDEFTYPE_REGISTER
MSR_P6_PERFEVTSEL_REGISTER
MSR_P6_TEST_CTL_REGISTER
MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER
MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
MSR_PENTIUM_4_MCG_MISC_REGISTER
MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
MSR_PENTIUM_M_THERM2_CTL_REGISTER
MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
MSR_SEV_STATUS_REGISTER
MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
MSR_SILVERMONT_EBL_CR_POWERON_REGISTER
MSR_SILVERMONT_FEATURE_CONFIG_REGISTER
MSR_SILVERMONT_FSB_FREQ_REGISTER
MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER
MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER
MSR_SILVERMONT_LBR_SELECT_REGISTER
MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER
MSR_SILVERMONT_PEBS_ENABLE_REGISTER
MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
MSR_SILVERMONT_PLATFORM_ID_REGISTER
MSR_SILVERMONT_PLATFORM_INFO_REGISTER
MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER
MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER
MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER
MSR_SILVERMONT_SMI_COUNT_REGISTER
MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER
MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER
MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER
MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER
MSR_SKYLAKE_IA32_MCG_CAP_REGISTER
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER
MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER
MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER
MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
MSR_SKYLAKE_PLATFORM_INFO_REGISTER
MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
MSR_SKYLAKE_POWER_CTL_REGISTER
MSR_SKYLAKE_PPIN_CTL_REGISTER
MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER
MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER
MSR_SKYLAKE_SMM_MCA_CAP_REGISTER
MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER
MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER
MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER
MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
MSR_XEON_5600_FEATURE_CONFIG_REGISTER
MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER
MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
MSR_XEON_D_IA32_MCG_CAP_REGISTER
MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER
MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_XEON_D_PLATFORM_INFO_REGISTER
MSR_XEON_D_PPIN_CTL_REGISTER
MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
MSR_XEON_D_SMM_MCA_CAP_REGISTER
MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
MSR_XEON_E7_FEATURE_CONFIG_REGISTER
MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
MSR_XEON_PHI_LBR_SELECT_REGISTER
MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
MSR_XEON_PHI_PLATFORM_INFO_REGISTER
MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
MSR_XEON_PHI_PPIN_CTL_REGISTER
MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
MSR_XEON_PHI_SMI_COUNT_REGISTER
MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
MTRR_CONTEXT
MTRR_LIB_ADDRESS
MTRR_MEMORY_RANGE
P
PAGE_ATTRIBUTE_TABLE
PAGE_MAP_AND_DIRECTORY_POINTER
PAGE_TABLE_1G_ENTRY
PAGE_TABLE_ENTRY
PAGE_TABLE_LIB_PAGING_CONTEXT
PAGE_TABLE_LIB_PAGING_CONTEXT_DATA
PAGE_TABLE_LIB_PAGING_CONTEXT_IA32
PAGE_TABLE_LIB_PAGING_CONTEXT_X64
PAGE_TABLE_POOL
PROC_TRACE_DATA
PROC_TRACE_PROCESSOR_DATA
PROC_TRACE_TOPA_TABLE
PROCESSOR_SMM_DESCRIPTOR
PROGRAM_CPU_REGISTER_FLAGS
R
REGISTER_CPU_FEATURE_INFORMATION
RESERVED_VECTORS_DATA
RTIT_TOPA_TABLE_ENTRY
S
SMM_COMMUNICATE_HEADER_32
SMM_COMMUNICATE_HEADER_64
SMM_CPU_DATA_BLOCK
SMM_CPU_PRIVATE_DATA
SMM_CPU_SEMAPHORE_CPU
SMM_CPU_SEMAPHORE_GLOBAL
SMM_CPU_SEMAPHORES
SMM_DISPATCHER_MP_SYNC_DATA
SMM_PROFILE_ENTRY
SMM_PROFILE_HEADER
SMRAM_SAVE_STATE_IOMISC
SMRAM_SAVE_STATE_MAP
SMRAM_SAVE_STATE_MAP32
SMRAM_SAVE_STATE_MAP64
SOFTWARE_STM_HEADER
STM_ADDRESS_LOOKUP_DESCRIPTOR
STM_EVENT_LOG_MANAGEMENT_REQUEST
STM_FEAT
STM_HEADER
STM_LOG_ENTRY
STM_MAP_ADDRESS_RANGE_DESCRIPTOR
STM_PCI_DEVICE_PATH_NODE
STM_PROTECTION_EXCEPTION_HANDLER
STM_PROTECTION_EXCEPTION_STACK_FRAME
STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32
STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
STM_REGISTER_VIOLATION_DESC
STM_RSC
STM_RSC_ALL_RESOURCES_DESC
STM_RSC_DESC_HEADER
STM_RSC_END
STM_RSC_IO_DESC
STM_RSC_MEM_DESC
STM_RSC_MMIO_DESC
STM_RSC_MSR_DESC
STM_RSC_PCI_CFG_DESC
STM_RSC_TRAPPED_IO_DESC
STM_SMM_ENTRY_STATE
STM_SMM_RESUME_STATE
STM_SMM_STATE
STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR
STM_VMCS_DATABASE_REQUEST
T
TXT_PROCESSOR_SMM_DESCRIPTOR
V
VARIABLE_MTRR
_
_ACPI_RESET_STRUCTURE
_BRANCH_TRACE_RECORD
_CPU_MP_DATA
_EFI_SM_MONITOR_INIT_PROTOCOL
_EFI_SMM_CPU_SERVICE_PROTOCOL
_GDT_ENTRIES
_GDT_ENTRY
_MSR_DS_AREA_STRUCT
_MTRR_FIXED_SETTINGS_
_MTRR_SETTINGS_
_MTRR_VARIABLE_SETTING_
_MTRR_VARIABLE_SETTINGS_
_PEBS_RECORD
_SEC_IDT_TABLE
_SMM_SUPERVISOR_PROTOCOL
A | C | E | F | I | L | M | P | R | S | T | V | _
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- a -

  • ACPI : CPUID_VERSION_INFO_EDX
  • ACPIBAR_BASE_ADDRESS : MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
  • Activity_Window : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • ADDR0_CFG : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • ADDR1_CFG : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • ADDR2_CFG : MSR_IA32_RTIT_CTL_REGISTER
  • ADDR3_CFG : MSR_IA32_RTIT_CTL_REGISTER
  • Address : MSR_P6_BBL_CR_ADDR_REGISTER
  • AddressMode : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • AddressParityCheckEnable : MSR_P6_BBL_CR_CTL3_REGISTER
  • AddressParityEnable : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • AddressRequestErrorCheckingDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • AdjacentCacheLinePrefetchDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • ADX : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • AERR_DriveEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER
  • AERR_ObservationEnabled : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER
  • AESConfiguration : MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
  • AESNI : CPUID_VERSION_INFO_ECX
  • AgentID : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • AllBranchMispredictRetired : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • AltMovCr8 : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • ANY : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER
  • AnyThread0 : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • AnyThread1 : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • AnyThread2 : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • APIC : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • ApicBase : MSR_IA32_APIC_BASE_REGISTER , MSR_P6_APIC_BASE_REGISTER
  • ApicBaseHi : MSR_IA32_APIC_BASE_REGISTER
  • APICClusterID : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ApicIdCoreIdSize : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
  • ApicIdShift : CPUID_EXTENDED_TOPOLOGY_EAX
  • ARAT : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • ARB : MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
  • ArchPerfMonVerID : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • ASCI : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • AutomaticC_StateConversionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • AutomaticThermalControlCircuit : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • AutonomousUtilizationBasedFrequencyControlLog : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • AutonomousUtilizationBasedFrequencyControlStatus : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • AUX : MSR_IA32_TSC_AUX_REGISTER
  • AVX : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_VERSION_INFO_ECX
  • AVX2 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • AVX_512 : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- b -

  • BankSupport : MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • Base : MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • BaseAddress : LOCAL_APIC_MSI_ADDRESS
  • BaseFamily : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • BaseHi : MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • BaseModel : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • BasePRMRRBaseAddress : MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
  • BERR_DriverEnable : MSR_P6_EBL_CR_POWERON_REGISTER
  • BERR_Enable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER
  • BINIT_DriverDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • BINIT_DriverEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • BINIT_ObservationEnabled : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • Bits : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_EBX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_PROCESSOR_TOPOLOGY_EAX , CPUID_AMD_PROCESSOR_TOPOLOGY_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_ECX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX , CPUID_CACHE_INFO_CACHE_TLB , CPUID_CACHE_PARAMS_EAX , CPUID_CACHE_PARAMS_EBX , CPUID_CACHE_PARAMS_EDX , CPUID_EXTENDED_CACHE_INFO_ECX , CPUID_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX , CPUID_EXTENDED_STATE_SUB_LEAF_EAX , CPUID_EXTENDED_STATE_SUB_LEAF_ECX , CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX , CPUID_EXTENDED_TOPOLOGY_EAX , CPUID_EXTENDED_TOPOLOGY_EBX , CPUID_EXTENDED_TOPOLOGY_ECX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX , CPUID_MEMORY_ENCRYPTION_INFO_EAX , CPUID_MEMORY_ENCRYPTION_INFO_EBX , CPUID_MEMORY_ENCRYPTION_INFO_ECX , CPUID_MEMORY_ENCRYPTION_INFO_EDX , CPUID_MONITOR_MWAIT_EAX , CPUID_MONITOR_MWAIT_EBX , CPUID_MONITOR_MWAIT_ECX , CPUID_MONITOR_MWAIT_EDX , CPUID_PROCESSOR_FREQUENCY_EAX , CPUID_PROCESSOR_FREQUENCY_EBX , CPUID_PROCESSOR_FREQUENCY_ECX , CPUID_SOC_VENDOR_MAIN_LEAF_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX , CPUID_THERMAL_POWER_MANAGEMENT_EAX , CPUID_THERMAL_POWER_MANAGEMENT_EBX , CPUID_THERMAL_POWER_MANAGEMENT_ECX , CPUID_VERSION_INFO_EAX , CPUID_VERSION_INFO_EBX , CPUID_VERSION_INFO_ECX , CPUID_VERSION_INFO_EDX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX , IA32_VMX_MISC_REGISTER , MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_ATOM_FSB_FREQ_REGISTER , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_ATOM_PERF_STATUS_REGISTER , MSR_ATOM_PLATFORM_ID_REGISTER , MSR_ATOM_THERM2_CTL_REGISTER , MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_FEATURE_CONTROL_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER , MSR_CORE2_PLATFORM_ID_REGISTER , MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_CORE_IA32_EFER_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER , MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER , MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER , MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_POWER_INFO_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER , MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER , MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_THREAD_ID_INFO_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_APIC_BASE_REGISTER , MSR_IA32_BIOS_SIGN_ID_REGISTER , MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_IA32_DCA_0_CAP_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_EFER_REGISTER , MSR_IA32_ENERGY_PERF_BIAS_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_FIXED_CTR_CTRL_REGISTER , MSR_IA32_HWP_CAPABILITIES_REGISTER , MSR_IA32_HWP_INTERRUPT_REGISTER , MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER , MSR_IA32_HWP_STATUS_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_MC_CTL2_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_EXT_CTL_REGISTER , MSR_IA32_MCG_STATUS_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_MTRR_PHYSMASK_REGISTER , MSR_IA32_MTRRCAP_REGISTER , MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_PAT_REGISTER , MSR_IA32_PEBS_ENABLE_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CTL_REGISTER , MSR_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_INUSE_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_STATUS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PKG_HDC_CTL_REGISTER , MSR_IA32_PLATFORM_ID_REGISTER , MSR_IA32_PM_CTL1_REGISTER , MSR_IA32_PM_ENABLE_REGISTER , MSR_IA32_PQR_ASSOC_REGISTER , MSR_IA32_QM_CTR_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER , MSR_IA32_RTIT_ADDR_REGISTER , MSR_IA32_RTIT_CR3_MATCH_REGISTER , MSR_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER , MSR_IA32_RTIT_STATUS_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_IA32_SYSENTER_CS_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_IA32_TSC_AUX_REGISTER , MSR_IA32_VMX_BASIC_REGISTER , MSR_IA32_XSS_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER , MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PLATFORM_ID_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_BBL_CR_ADDR_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_P6_IA32_PLATFORM_ID_REGISTER , MSR_P6_MC_STATUS_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_P6_TEST_CTL_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_MCG_MISC_REGISTER , MSR_PENTIUM_4_PEBS_ENABLE_REGISTER , MSR_PENTIUM_4_PLATFORM_BRV_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER , MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SEV_STATUS_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_EBL_CR_POWERON_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER , MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_PEBS_FRONTEND_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER , MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • BlockSmi : MSR_IA32_SMM_MONITOR_CTL_REGISTER
  • BlockSmiSupported : IA32_VMX_MISC_REGISTER
  • BMI1 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • BMI2 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • BNDPRESERVE : MSR_IA32_BNDCFGS_REGISTER
  • BranchEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • BranchInstructionsRetired : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • BranchMonitoringEventSignaled : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • BrandIndex : CPUID_VERSION_INFO_EBX
  • BrandString : CPUID_BRAND_STRING_DATA , CPUID_SOC_VENDOR_BRAND_STRING_DATA
  • BSP : MSR_IA32_APIC_BASE_REGISTER , MSR_P6_APIC_BASE_REGISTER
  • BTF : MSR_IA32_DEBUGCTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER
  • BTINT : MSR_IA32_DEBUGCTL_REGISTER
  • BTS : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • BTS_OFF_OS : MSR_IA32_DEBUGCTL_REGISTER
  • BTS_OFF_USR : MSR_IA32_DEBUGCTL_REGISTER
  • BusFrequency : CPUID_PROCESSOR_FREQUENCY_ECX
  • BusParkDisable : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- c -

  • C0States : CPUID_MONITOR_MWAIT_EDX
  • C10ResidencyCounter : MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
  • C10ResidencyCounterHi : MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
  • C1AutoDemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C1EEnable : MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER
  • C1StateAutoDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • C1StateAutoUndemotionEnable : MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • C1States : CPUID_MONITOR_MWAIT_EDX
  • C1Undemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C2States : CPUID_MONITOR_MWAIT_EDX
  • C3AutoDemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C3StateAutoDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • C3States : CPUID_MONITOR_MWAIT_EDX
  • C3Undemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C4States : CPUID_MONITOR_MWAIT_EDX
  • C5States : CPUID_MONITOR_MWAIT_EDX
  • C6States : CPUID_MONITOR_MWAIT_EDX
  • C7States : CPUID_MONITOR_MWAIT_EDX
  • C8ResidencyCounter : MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
  • C8ResidencyCounterHi : MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
  • C9ResidencyCounter : MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
  • C9ResidencyCounterHi : MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
  • C_StateLimit : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • CacheBusFraction : MSR_P6_BBL_CR_CTL3_REGISTER
  • CacheDescriptor : CPUID_CACHE_INFO_CACHE_TLB
  • CacheInclusiveness : CPUID_CACHE_PARAMS_EDX
  • CacheLevel : CPUID_CACHE_PARAMS_EAX
  • CacheLineSize : CPUID_EXTENDED_CACHE_INFO_ECX , CPUID_VERSION_INFO_EBX
  • CacheSize : CPUID_EXTENDED_CACHE_INFO_ECX
  • CacheSizePerBank : MSR_P6_BBL_CR_CTL3_REGISTER
  • CacheStateErrorEnable : MSR_P6_BBL_CR_CTL3_REGISTER
  • CacheType : CPUID_CACHE_PARAMS_EAX
  • CapacityLength : CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
  • CAT : MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
  • CBM : MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
  • CBox : MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
  • CFGLock : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • Checksum : CPU_MICROCODE_EXTENDED_TABLE , CPU_MICROCODE_HEADER
  • ClampingLimit : MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
  • CLFLUSHOPT : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • CLFSH : CPUID_VERSION_INFO_EDX
  • ClockFrequencyRatio : MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ClockFrequencyRatio1 : MSR_P6_EBL_CR_POWERON_REGISTER
  • ClockFrequencyRatioRead : MSR_P6_IA32_PLATFORM_ID_REGISTER
  • ClockRatio : MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
  • CLWB : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • CLZERO : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
  • CMASK : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • CMCI_EN : MSR_IA32_MC_CTL2_REGISTER
  • CMOV : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • CmpLegacy : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • CMPXCHG16B : CPUID_VERSION_INFO_ECX
  • CMPXCHG8B : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • CntAndMode : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • CntrHit0 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CntrHit1 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CNXT_ID : CPUID_VERSION_INFO_ECX
  • CodeDataPrioritization : CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
  • Compacted : CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
  • ComplexCacheIndexing : CPUID_CACHE_PARAMS_EDX
  • CondChgd : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
  • Config_TDP_Base : MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
  • Config_TDP_Lock : MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
  • Config_TDP_LVL1_Ratio : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • Config_TDP_LVL2_Ratio : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • ConfigTDPLevels : MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
  • ConfigurableAddressRanges : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
  • ConfigurablePsb : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • ContexEn : MSR_IA32_RTIT_STATUS_REGISTER
  • Core_Count : MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
  • CoreCountThresholdGroup0 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup1 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup2 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup3 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup4 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup5 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup6 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup7 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreFrequencyLimitingLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • CoreFrequencyP1Log : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • CoreId : CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
  • CorePowerLimitingLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
  • CoreVoltage : MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
  • CorrectedErrorCountThreshold : MSR_IA32_MC_CTL2_REGISTER
  • COS : MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER , MSR_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
  • CosUpdatesInfrequent : CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
  • Count : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • Count0 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • Count1 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CountWindow : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CPL_EQ_0 : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • CPL_NEQ_0 : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • CpuIdVersionInfoEcx : REGISTER_CPU_FEATURE_INFORMATION
  • CpuIdVersionInfoEdx : REGISTER_CPU_FEATURE_INFORMATION
  • CR3 : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
  • Cr3 : MSR_IA32_RTIT_CR3_MATCH_REGISTER
  • CR3 : MSR_IA32_RTIT_CTL_REGISTER
  • Cr3Filter : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • Cr3Hi : MSR_IA32_RTIT_CR3_MATCH_REGISTER
  • CriticalTempEnable : MSR_IA32_THERM_INTERRUPT_REGISTER
  • CriticalTempStatus : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • CriticalTempStatusLog : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • CrossDomainLimitLog : MSR_IA32_THERM_STATUS_REGISTER
  • CrossDomainLimitStatus : MSR_IA32_THERM_STATUS_REGISTER
  • CRTNParityCheckEnable : MSR_P6_BBL_CR_CTL3_REGISTER
  • CS : MSR_IA32_SYSENTER_CS_REGISTER
  • CStateAutoDemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateConversion : MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateDemotion : MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateRange : MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
  • CStateUndemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateUnDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • CTR_Frz : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • CurrentCount : MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
  • CurrentCountHi : MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
  • CurrentLimitLog : MSR_IA32_THERM_STATUS_REGISTER
  • CurrentLimitStatus : MSR_IA32_THERM_STATUS_REGISTER
  • CurrentPerformanceStateValue : MSR_ATOM_PERF_STATUS_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER
  • CX8 : CPUID_VERSION_INFO_EDX
  • CYCEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • CycleThresholdEncodings : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
  • CYCThresh : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- d -

  • DataBreakpointExtension : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • DataErrorCheckingDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • DataErrorCheckingEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • DataSize : CPU_MICROCODE_HEADER
  • Date : CPU_MICROCODE_HEADER
  • DCA : CPUID_VERSION_INFO_ECX
  • DCA_ACTIVE : MSR_IA32_DCA_0_CAP_REGISTER
  • DCA_DELAY : MSR_IA32_DCA_0_CAP_REGISTER
  • DCA_QUEUE_SIZE : MSR_IA32_DCA_0_CAP_REGISTER
  • DCA_TYPE : MSR_IA32_DCA_0_CAP_REGISTER
  • DCUHardwarePrefetcherDisable : MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
  • DCUIPPrefetcherDisable : MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
  • DCUPrefetcherDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • DE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • DebugOccurred : MSR_IA32_DEBUG_INTERFACE_REGISTER
  • DeliveryMode : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_MSI_DATA
  • DeliveryStatus : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER
  • DeltaRatioGroup1 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup2 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup3 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup4 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup5 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup6 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeprecateFpuCsDs : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • Desired_Performance : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • Destination : LOCAL_APIC_ICR_HIGH
  • DestinationId : LOCAL_APIC_MSI_ADDRESS
  • DestinationMode : LOCAL_APIC_ICR_LOW , LOCAL_APIC_MSI_ADDRESS
  • DestinationShorthand : LOCAL_APIC_ICR_LOW
  • DigitalReadout : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • DigitalTemperatureSensor : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • Disable_LOCK : MSR_P6_TEST_CTL_REGISTER
  • DisableEnergyEfficiencyOptimization : MSR_SKYLAKE_POWER_CTL_REGISTER
  • DisableInGuest : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • DisplayFamily : REGISTER_CPU_FEATURE_INFORMATION
  • DisplayModel : REGISTER_CPU_FEATURE_INFORMATION
  • DisRETC : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • DivideValue1 : LOCAL_APIC_DCR
  • DivideValue2 : LOCAL_APIC_DCR
  • DS : CPUID_VERSION_INFO_EDX , MSR_PENTIUM_4_MCG_MISC_REGISTER
  • DS_CPL : CPUID_VERSION_INFO_ECX
  • DTES64 : CPUID_VERSION_INFO_ECX
  • DualMonitor : MSR_IA32_VMX_BASIC_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- e -

  • E : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • EbxBitVectorLength : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • ECCCheckEnable : MSR_P6_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
  • ECMD : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • EIPV : MSR_IA32_MCG_STATUS_REGISTER
  • EIST : CPUID_VERSION_INFO_ECX , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • EISTHardwareCoordinationDisable : MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
  • EISTLock : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • ElapsedCycles : MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
  • ElectricalDesignPointLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • ElectricalDesignPointStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • EN : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_IA32_APIC_BASE_REGISTER , MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • EN0_OS : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN0_PMI : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN0_Usr : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN1_OS : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN1_PMI : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN1_Usr : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN2_OS : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN2_PMI : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN2_Usr : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN_CALL_STACK : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER
  • EN_Excursion_Minimum : MSR_IA32_HWP_INTERRUPT_REGISTER
  • EN_FIXED_CTRn : MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
  • EN_Guaranteed_Performance_Change : MSR_IA32_HWP_INTERRUPT_REGISTER
  • EN_PMCn : MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
  • Enable : MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER
  • ENABLE_PEBS_MY_THR : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • ENABLE_PEBS_NUM_ALT : MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
  • ENABLE_PEBS_OTH_THR : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • Enable_PPIN : MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER
  • ENABLE_UNCORE_PMI : MSR_IA32_DEBUGCTL_REGISTER
  • EnableC1Undemotion : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • EnableC3Undemotion : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • EnableCounting : MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
  • EnableOverflow : MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
  • EnablePlatformPowerLimit1 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • EnablePlatformPowerLimit2 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • EnableVmxInsideSmx : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • EnableVmxOutsideSmx : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER
  • END : RTIT_TOPA_TABLE_ENTRY
  • Energy : MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
  • Energy_Performance_Preference : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • EnergyPerformanceBiasEnable : MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
  • EnergyStatusUnits : MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
  • EnExcept : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • EnhancedRepMovsbStosb : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • EnLBRFrz : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • EnMonitoring : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • EoiBroadcastSuppression : LOCAL_APIC_SVR , LOCAL_APIC_VERSION
  • EpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
  • EptEnabled : STM_SMM_STATE
  • EptSupported : STM_FEAT
  • Error : MSR_IA32_QM_CTR_REGISTER , MSR_IA32_RTIT_STATUS_REGISTER
  • ErrorCode : STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 , STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
  • EventCodeSelect : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • EventCodeSelectHigh : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • EventID : MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
  • EventNum : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • EventSelect : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • Excursion_To_Minimum : MSR_IA32_HWP_STATUS_REGISTER
  • ExecuteBIST : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ExtApicSpace : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • EXTD : MSR_IA32_APIC_BASE_REGISTER
  • ExtendedApicId : CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
  • ExtendedChecksum : CPU_MICROCODE_EXTENDED_TABLE_HEADER
  • ExtendedFamilyId : CPUID_VERSION_INFO_EAX
  • ExtendedModelId : CPUID_VERSION_INFO_EAX
  • ExtendedOnDemandClockModulationDutyCycle : MSR_IA32_CLOCK_MODULATION_REGISTER
  • ExtendedSignatureCount : CPU_MICROCODE_EXTENDED_TABLE_HEADER
  • ExtensionsSupported : CPUID_MONITOR_MWAIT_ECX
  • ExtFamily : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • ExtModel : CPUID_AMD_EXTENDED_CPU_SIG_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- f -

  • F16C : CPUID_VERSION_INFO_ECX
  • FabricEn : MSR_IA32_RTIT_CTL_REGISTER
  • FamilyId : CPUID_VERSION_INFO_EAX
  • FAR_BRANCH : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • FastStrings : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • FDP_EXCPTN_ONLY : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • FE : MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER
  • FERR : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
  • FFSR : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • FFXSR : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • FilterEn : MSR_IA32_RTIT_STATUS_REGISTER
  • FIX : MSR_IA32_MTRRCAP_REGISTER
  • Fix_Me_1 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
  • Fix_Me_2 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
  • Fix_Me_3 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
  • Fix_Me_4 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
  • Fix_Me_5 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
  • Fix_Me_6 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
  • Fix_Me_7 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
  • Fixed : MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
  • FIXED_CTR0 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • FIXED_CTR1 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • FIXED_CTR2 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • FixedFunctionPerformanceCounters : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
  • FixedFunctionPerformanceCounterWidth : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
  • FMA : CPUID_VERSION_INFO_ECX
  • FMA4 : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • FocusProcessorChecking : LOCAL_APIC_SVR
  • FORCEPR_Enable : MSR_IA32_THERM_INTERRUPT_REGISTER
  • FPU : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • FRCModeEnable : MSR_P6_EBL_CR_POWERON_REGISTER
  • FREEZE : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • FREEZE_LBRS_ON_PMI : MSR_IA32_DEBUGCTL_REGISTER
  • FREEZE_PERFMON_ON_PMI : MSR_IA32_DEBUGCTL_REGISTER
  • FREEZE_WHILE_SMM : MSR_IA32_DEBUGCTL_REGISTER
  • FrequencyLimitingStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • FrequencyP1Status : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • FromEtoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromEtoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromFtoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromFtoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromLinearAddress : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • FromLinearAddressHi : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • FromMtoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromMtoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromStoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromStoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FSGSBASE : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • FullyAssociativeCache : CPUID_CACHE_PARAMS_EAX
  • FUPonPTW : MSR_IA32_RTIT_CTL_REGISTER
  • FW_WRITE : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • FXSR : CPUID_VERSION_INFO_EDX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- g -

  • GraphicsDriverLog : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
  • GraphicsDriverStatus : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • GraphicsPowerLimitingStatus : MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • Guaranteed_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • Guaranteed_Performance_Change : MSR_IA32_HWP_STATUS_REGISTER
  • GuestPhysAddrSize : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- h -

  • HardwareCoordinationFeedback : CPUID_THERMAL_POWER_MANAGEMENT_ECX
  • HardwarePrefetcherDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • HDC : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HDC_Allow_Block : MSR_IA32_PM_CTL1_REGISTER
  • HDC_Pkg_Enable : MSR_IA32_PKG_HDC_CTL_REGISTER
  • HeaderVersion : CPU_MICROCODE_HEADER
  • HighAddressOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
  • Highest_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • HighestCosNumber : CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
  • HighSizeOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
  • HighTempEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • HLE : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • HltActivityStateSupported : IA32_VMX_MISC_REGISTER
  • HTT : CPUID_VERSION_INFO_EDX
  • HW_BLOCK : MSR_IA32_DCA_0_CAP_REGISTER
  • HWP : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_Activity_Window : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_ENABLE : MSR_IA32_PM_ENABLE_REGISTER
  • HWP_Energy_Performance_Preference : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_Notification : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_Package_Level_Request : CPUID_THERMAL_POWER_MANAGEMENT_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- i -

  • IA32_FIXED_CTRn : MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
  • IA32_PERFEVTSELn : MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
  • IA32_TSC_ADJUST : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • IA32_XSS : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
  • IBS : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • IDA : MSR_IA32_PERF_CTL_REGISTER
  • IDADisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • IDQ_Bubble_Length : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • IDQ_Bubble_Width : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • IN_TX : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
  • IN_TXCP : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
  • InefficientOperationLog : MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • InefficientOperationStatus : MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • InitialLocalApicId : CPUID_VERSION_INFO_EBX
  • InitiatorMCERR_Disable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • InOrderQueueDepth : MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • InputPinPolarity : LOCAL_APIC_LVT_LINT
  • InsOutsReporting : MSR_IA32_VMX_BASIC_REGISTER
  • InstructionsRetired : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • INT : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • IntegerBusFrequencyRatio : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER
  • IntelProcessorTrace : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • IntelTXTCapableChipset : MSR_CORE2_EBL_CR_POWERON_REGISTER
  • InternalMCERR_Disable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • InterruptAsBreak : CPUID_MONITOR_MWAIT_ECX
  • InterruptFiltering : MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
  • InterruptResponseTimeLimit : MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER
  • InterruptThresholds : CPUID_THERMAL_POWER_MANAGEMENT_EBX
  • INV : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • Invalidate : CPUID_CACHE_PARAMS_EDX
  • InvariantTsc : CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
  • INVPCID : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • IO_MWAIT : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • IPPrefetcherDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • IpTraceStopFiltering : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • IRPerf : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
  • IsVendorScheme : CPUID_SOC_VENDOR_MAIN_LEAF_EBX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- j -

  • JCC : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
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  • h
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  • l
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  • o
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  • r
  • s
  • t
  • u
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  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- l -

  • L1DataCacheContextMode : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • L2AddressRange : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2AdjacentCacheLinePrefetcherDisable : MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
  • L2Associativity : CPUID_EXTENDED_CACHE_INFO_ECX , MSR_P6_BBL_CR_CTL3_REGISTER
  • L2Banks : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2CacheAllocation : CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
  • L2CacheLatency : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2CacheLatencyRead : MSR_P6_IA32_PLATFORM_ID_REGISTER
  • L2Command : MSR_P6_BBL_CR_CTL_REGISTER
  • L2Configured : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2Enabled : MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
  • L2HardwareDisable : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2HardwareEnabled : MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
  • L2HardwarePrefetcherDisable : MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
  • L2Hit : MSR_P6_BBL_CR_CTL_REGISTER
  • L2NotPresent : MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
  • L3CacheAllocation : CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
  • L3CacheLocalBandwidthMonitoring : CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
  • L3CacheOccupancyMonitoring : CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
  • L3CacheRDT_M : CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
  • L3CacheTotalBandwidthMonitoring : CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
  • LAHF_SAHF : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_ECX
  • LargestMonitorLineSize : CPUID_MONITOR_MWAIT_EBX
  • LastLevelCacheMisses : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • LastLevelCacheReferences : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • LBR : MSR_IA32_DEBUGCTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER
  • LBR_FMT : MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER
  • LBR_Frz : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • LBRsValid : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • Length : STM_PCI_DEVICE_PATH_NODE
  • Level : LOCAL_APIC_ICR_LOW , LOCAL_APIC_MSI_DATA
  • LevelNumber : CPUID_EXTENDED_TOPOLOGY_ECX
  • LevelType : CPUID_EXTENDED_TOPOLOGY_ECX
  • Limit : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • LimitCpuidMaxval : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • LinearAddressBits : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX
  • LinePartitions : CPUID_CACHE_PARAMS_EBX
  • LineSize : CPUID_CACHE_PARAMS_EBX
  • LIP : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • LL_EN_PMC0 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LL_EN_PMC1 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LL_EN_PMC2 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LL_EN_PMC3 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LM : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • LMA : MSR_IA32_EFER_REGISTER
  • LMCE_EN : MSR_IA32_MCG_EXT_CTL_REGISTER
  • LMCE_S : MSR_IA32_MCG_STATUS_REGISTER
  • LmceOn : MSR_IA32_FEATURE_CONTROL_REGISTER
  • LME : MSR_IA32_EFER_REGISTER
  • LoaderRevision : CPU_MICROCODE_HEADER
  • Lock : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • LockOut : MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER
  • Logical_Processor_ID : MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
  • LogicalProcessors : CPUID_EXTENDED_TOPOLOGY_EBX
  • Long_Flow_Indication : MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • LONGRESET : MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
  • LowAddressOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
  • Lowest_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • LowPowerModeEnable : MSR_P6_EBL_CR_POWERON_REGISTER
  • LowPowerModeSupport : MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
  • LowSizeOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
  • LowTempEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • LPLLSelect : MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
  • Lvl2Base : MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
  • LWP : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • LZCNT : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_ECX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- m -

  • Mask : LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER
  • MaskOrTableOffset : MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
  • MAWAU : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • MAX_NON_TURBO_RATIO : MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
  • MAX_RATIO : MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
  • MaxCoresGroup0 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxEnclaveSize_64 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
  • MaxEnclaveSize_Not64 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
  • Maximum10C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum11C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum12C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum13C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum14C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum15C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum16C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum17C : MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
  • Maximum18C : MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
  • Maximum1C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum2C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum3C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum4C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum5C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum6C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum7C : MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum8C : MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum9C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum_Performance : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • MaximumAddressableIdsForLogicalProcessors : CPUID_CACHE_PARAMS_EAX , CPUID_VERSION_INFO_EBX
  • MaximumAddressableIdsForProcessorCores : CPUID_CACHE_PARAMS_EAX
  • MaximumBusRatio : MSR_ATOM_PERF_STATUS_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER
  • MaximumEfficiencyFrequencyLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • MaximumEfficiencyFrequencyStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • MaximumEfficiencyRatio : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • MaximumFrequency : CPUID_PROCESSOR_FREQUENCY_EBX
  • MaximumNon_TurboRatio : MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • MaximumNonTurboRatio : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • MaximumPower : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
  • MaximumQualifiedRatio : MSR_ATOM_PLATFORM_ID_REGISTER , MSR_CORE2_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER
  • MaximumTimeWindow : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
  • MaxIncrementalCoresGroup1 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup2 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup3 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup4 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup5 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup6 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxLvtEntry : LOCAL_APIC_VERSION
  • MaxRatioLimitGroup0 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup1 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup2 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup3 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup4 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup5 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup6 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup7 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurboLimitLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • MaxTurboLimitStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • MC_STATUS_ADDRV : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_DAM : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_EN : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_MCACOD : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_MISCV : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_MSCOD : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_O : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_UC : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_V : MSR_P6_MC_STATUS_REGISTER
  • MCA : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MCE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MCERR_DriveEnable : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • MCERR_ObservationDisabled : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • MCERR_ObservationEnabled : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • MCG_CTL_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_ELOG_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_EM_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_EXT_CNT : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_EXT_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_LMCE_P : MSR_IA32_MCG_CAP_REGISTER
  • MCG_SER_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_TES_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCIP : MSR_IA32_MCG_STATUS_REGISTER
  • MCP_CMCI_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MemErrorLogEnable : MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
  • MemoryType : MSR_IA32_VMX_BASIC_REGISTER
  • MemTypePRMRRBASEMemType : MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
  • MESI : MSR_P6_BBL_CR_CTL_REGISTER
  • MicrocodeUpdateSignature : MSR_IA32_BIOS_SIGN_ID_REGISTER
  • MIN_RATIO : MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
  • MinAsid : CPUID_MEMORY_ENCRYPTION_INFO_EDX
  • Minimum_Performance : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • MinimumOperatingRatio : MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
  • MinimumPower : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
  • MinimumThreshold : MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
  • MisAlignSse : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • Mispred : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • MMX : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MmxExt : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • Model : CPUID_VERSION_INFO_EAX
  • MONITOR : CPUID_VERSION_INFO_ECX , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • MonitorFeatures : MSEG_HEADER
  • Most_Efficient_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • MOVBE : CPUID_VERSION_INFO_ECX
  • MPX : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • MsegBase : MSR_IA32_SMM_MONITOR_CTL_REGISTER
  • MsegHeaderRevision : MSEG_HEADER
  • MsegRevisionIdentifier : IA32_VMX_MISC_REGISTER
  • MSR : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MsrStoreListMaximum : IA32_VMX_MISC_REGISTER
  • Mtc : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • MTCEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • MTCFreq : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • MtcPeriodEncodings : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
  • MTRR : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MultiCoreTurboLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • MultiCoreTurboStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • MwaitExtended : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • MWAITRedirectionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
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  • i
  • j
  • l
  • m
  • n
  • o
  • p
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  • s
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  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- n -

  • NC : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
  • NEAR_IND_CALL : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_IND_JMP : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_REL_CALL : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_REL_JMP : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_RET : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NodeId : CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
  • NodesPerProcessor : CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
  • NonIntegerBusRatio : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER
  • NotUsed : CPUID_VERSION_INFO_ECX
  • NotValid : CPUID_CACHE_INFO_CACHE_TLB
  • NumberOfCr3TargetValues : IA32_VMX_MISC_REGISTER
  • NUMCORE_0 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_1 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_2 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_3 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_4 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_5 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_6 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_7 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NumGuests : CPUID_MEMORY_ENCRYPTION_INFO_ECX
  • NX : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • NXE : MSR_CORE_IA32_EFER_REGISTER , MSR_IA32_EFER_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- o -

  • OnDemandClockModulationDutyCycle : MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
  • OnDemandClockModulationEnable : MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
  • OS : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • OSPKE : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • OSVW : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • OSXSAVE : CPUID_VERSION_INFO_ECX
  • OtherLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • OtherStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • OutputOffset : MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
  • OutputTriStateEnable : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • OutputTriStateEnabled : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • OverheatEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
  • Ovf_BufDSSAVE : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FIXED_CTRn : MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FixedCtr0 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FixedCtr1 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FixedCtr2 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC0 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC1 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC2 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC3 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC4 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC5 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC6 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC7 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMCn : MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_Uncore : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • OvfBuf : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
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  • f
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  • n
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  • s
  • t
  • u
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  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- p -

  • PA0 : MSR_IA32_PAT_REGISTER
  • PA1 : MSR_IA32_PAT_REGISTER
  • PA2 : MSR_IA32_PAT_REGISTER
  • PA3 : MSR_IA32_PAT_REGISTER
  • PA4 : MSR_IA32_PAT_REGISTER
  • PA5 : MSR_IA32_PAT_REGISTER
  • PA6 : MSR_IA32_PAT_REGISTER
  • PA7 : MSR_IA32_PAT_REGISTER
  • Package_Control : MSR_IA32_HWP_REQUEST_REGISTER
  • PacketByteCnt : MSR_IA32_RTIT_STATUS_REGISTER
  • PAE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • Page1GB : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • PageFlushMsrBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX
  • PAT : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • PB0 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PB1 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PB2 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PB3 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PBE : CPUID_VERSION_INFO_EDX
  • PC : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • PCID : CPUID_VERSION_INFO_ECX
  • PCIERatio : MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
  • PCIExpressRequestorID : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • PCIExpressSegmentNumber : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • PCLMULQDQ : CPUID_VERSION_INFO_ECX
  • PCM0_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM1_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM2_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM3_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM4_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM5_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM6_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM7_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCUControllerError : MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
  • PCUFirmwareError : MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
  • PCUHardwareError : MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
  • PDCM : CPUID_VERSION_INFO_ECX
  • PEBS : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • PEBS_ARCH_REG : MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER
  • PEBS_EN_PMC0 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_EN_PMC1 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_EN_PMC2 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_EN_PMC3 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_FMT : MSR_CORE2_PERF_CAPABILITIES_REGISTER
  • PEBS_REC_FMT : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • PEBS_TRAP : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • PerfCtrExtCore : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • PerfCtrExtL3 : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • PerformanceEnergyBias : CPUID_THERMAL_POWER_MANAGEMENT_ECX
  • PerformanceMonitorCounters : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • PerformanceMonitorCounterWidth : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • PerformanceMonitoring : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • PerfTsc : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • PerfTscSize : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
  • PGE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • PhysBase : MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER
  • PhysBaseHi : MSR_IA32_MTRR_PHYSBASE_REGISTER
  • PhysicalAddressBits : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX
  • PhysMask : MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_IA32_MTRR_PHYSMASK_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER
  • PhysMaskHi : MSR_IA32_MTRR_PHYSMASK_REGISTER
  • PKG_Cx_Monitor : MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
  • PKG_MAX_PWR_LVL1 : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • PKG_MAX_PWR_LVL2 : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • PKG_MIN_PWR_LVL1 : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • PKG_MIN_PWR_LVL2 : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • PKG_TDP_LVL1 : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • PKG_TDP_LVL2 : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • PKGC_StateAutoDemotionEnable : MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • PkgType : CPUID_AMD_EXTENDED_CPU_SIG_EBX
  • PKRU : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
  • PKU : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • PL1Log : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PL1Status : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
  • PL1STatus : MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
  • PL1Status : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PL2Log : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PL2Status : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PLATFORM : MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
  • PlatformClampingLimitation1 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PlatformClampingLimitation2 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PlatformConfigurationServicesLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PlatformConfigurationServicesStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PlatformId : MSR_CORE2_PLATFORM_ID_REGISTER , MSR_IA32_PLATFORM_ID_REGISTER , MSR_NEHALEM_PLATFORM_ID_REGISTER , MSR_P6_IA32_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER
  • PlatformPowerLimit1 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PlatformPowerLimit2 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PLLog : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
  • PLN : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • PLStatus : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
  • PMI : MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
  • PMI_Sel_Core0 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Core1 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Core2 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Core3 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice0 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice1 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice2 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice3 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice4 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • POPCNT : CPUID_VERSION_INFO_ECX
  • PowerBudgetManagementLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PowerBudgetManagementStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PowerEventTrace : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • PowerLimitingStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • PowerLimitLog : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • PowerLimitNotificationEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • PowerLimitStatus : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • PowerPolicyPreference : MSR_IA32_ENERGY_PERF_BIAS_REGISTER
  • PowerUnits : MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
  • PPIN_CAP : MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER
  • PrefetchQueueDisable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • PREFETCHW : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_ECX
  • PREFETCHWT1 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • ProcessorBaseFrequency : CPUID_PROCESSOR_FREQUENCY_EAX
  • ProcessorFlag : CPU_MICROCODE_EXTENDED_TABLE
  • ProcessorFlags : CPU_MICROCODE_HEADER
  • ProcessorInfo : REGISTER_CPU_FEATURE_INFORMATION
  • ProcessorNumber : MSR_P6_BBL_CR_CTL_REGISTER
  • ProcessorSignature : CPU_MICROCODE_EXTENDED_TABLE , CPU_MICROCODE_HEADER
  • ProcessorTraceSupported : IA32_VMX_MISC_REGISTER
  • ProcessorType : CPUID_VERSION_INFO_EAX , REGISTER_CPU_FEATURE_INFORMATION
  • PROCHOT : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • PROCHOT_Enable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • PROCHOT_Event : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
  • PROCHOT_FORCEPR_Event : MSR_IA32_THERM_STATUS_REGISTER
  • PROCHOT_FORCEPR_Log : MSR_IA32_THERM_STATUS_REGISTER
  • PROCHOT_Log : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PROCHOT_Status : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • PROCHOTStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • ProgrammableRatioLimit : MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • ProgrammableTDPLimit : MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • ProgrammableTJOFFSET : MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • PS_EN : MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PSBFreq : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • PsbFrequencyEncodings : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
  • PSE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • PSE36 : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • PSE_36 : CPUID_VERSION_INFO_EDX
  • PSN : CPUID_VERSION_INFO_EDX
  • PT : CPUID_EXTENDED_STATE_SUB_LEAF_ECX
  • PtePosBits : CPUID_MEMORY_ENCRYPTION_INFO_EBX
  • PTM : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • PTWEn : MSR_IA32_RTIT_CTL_REGISTER
  • PTWrite : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • PwrEvtEn : MSR_IA32_RTIT_CTL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- r -

  • RatioLimit : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • RCNT_SCNT : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • RDPID : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • RDRAND : CPUID_VERSION_INFO_ECX
  • RDSEED : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RDT_A : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RDT_M : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RDTSCP : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • ReadingValid : MSR_IA32_THERM_STATUS_REGISTER
  • RecoverableAddressLSB : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • RedirectionHint : LOCAL_APIC_MSI_ADDRESS
  • ReducedPhysBits : CPUID_MEMORY_ENCRYPTION_INFO_EBX
  • ReinitializeVmcsRequired : STM_SMM_RESUME_STATE
  • RemoteIrr : LOCAL_APIC_LVT_LINT
  • Reserved : CPU_MICROCODE_EXTENDED_TABLE_HEADER , CPU_MICROCODE_HEADER , CPUID_AMD_EXTENDED_CPU_SIG_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_ECX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX , CPUID_CACHE_PARAMS_EAX , MSEG_HEADER , SOFTWARE_STM_HEADER , STM_FEAT
  • Reserved0 : LOCAL_APIC_DCR , LOCAL_APIC_ICR_HIGH , LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_ADDRESS , LOCAL_APIC_MSI_DATA , LOCAL_APIC_SVR , LOCAL_APIC_VERSION
  • Reserved1 : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_VERSION_INFO_EAX , LOCAL_APIC_DCR , LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_ADDRESS , LOCAL_APIC_MSI_DATA , LOCAL_APIC_SVR , LOCAL_APIC_VERSION , MSR_IA32_PEBS_ENABLE_REGISTER , STM_VMCS_DATABASE_REQUEST
  • Reserved2 : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_VERSION_INFO_EAX , LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_DATA , STM_SMM_RESUME_STATE
  • Reserved3 : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , MSR_IA32_PEBS_ENABLE_REGISTER
  • Reserved4 : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • ReservedBits : CPUID_MEMORY_ENCRYPTION_INFO_EAX , CPUID_MEMORY_ENCRYPTION_INFO_EBX
  • ResetVector : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ResidencyStateRegulationLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • ResidencyStateRegulationStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • ResolutionInDegreesCelsius : MSR_IA32_THERM_STATUS_REGISTER
  • ResourceMonitoredData : MSR_IA32_QM_CTR_REGISTER
  • ResourceMonitoredDataHi : MSR_IA32_QM_CTR_REGISTER
  • ResourceMonitoringID : MSR_IA32_PQR_ASSOC_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER
  • ResponseErrorCheckingDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • ResponseErrorCheckingEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • RIPV : MSR_IA32_MCG_STATUS_REGISTER
  • RMID : MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
  • RTIT : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • RTM : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RTM_DEBUG : MSR_IA32_DEBUGCTL_REGISTER
  • RunningAverageThermalLimitLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • RunningAverageThermalLimitStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- s -

  • ScalableBusSpeed : MSR_ATOM_FSB_FREQ_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER
  • SCE : MSR_IA32_EFER_REGISTER
  • SDBG : CPUID_VERSION_INFO_ECX
  • SelfInitializingCache : CPUID_CACHE_PARAMS_EAX
  • SenterGlobalEnable : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • SenterLocalFunctionEnables : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • SEP : CPUID_VERSION_INFO_EDX
  • SevBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX , MSR_SEV_STATUS_REGISTER
  • SevEsBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX , MSR_SEV_STATUS_REGISTER
  • SGX : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • SGX1 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
  • SGX2 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
  • SGX_LC : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • SGX_SVN_SINIT : MSR_IA32_SGX_SVN_STATUS_REGISTER
  • SgxEnable : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • SgxLaunchControlEnable : MSR_IA32_FEATURE_CONTROL_REGISTER
  • SHA : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • ShutdownActivityStateSupported : IA32_VMX_MISC_REGISTER
  • SignedExtension : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • SignExt_VA : MSR_IA32_RTIT_ADDR_REGISTER
  • SingleRangeOutput : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • Size : RTIT_TOPA_TABLE_ENTRY
  • SKINIT : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • SmallestMonitorLineSize : CPUID_MONITOR_MWAIT_EAX
  • SMAP : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • SmBaseMsrSupported : IA32_VMX_MISC_REGISTER
  • SmeBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX
  • SMEP : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • SMICount : MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER
  • SMM_Code_Access_Chk : MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • SMM_Code_Chk_En : MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
  • SMM_CPU_SVRSTR : MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • SMM_FREEZE : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • SMRR : MSR_IA32_MTRRCAP_REGISTER
  • SMRREnable : MSR_CORE2_FEATURE_CONTROL_REGISTER
  • SMX : CPUID_VERSION_INFO_ECX
  • SocVendorId : CPUID_SOC_VENDOR_MAIN_LEAF_EBX
  • SoftwareEnable : LOCAL_APIC_SVR
  • SplitLockDisable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • SpuriousVector : LOCAL_APIC_SVR
  • SS : CPUID_VERSION_INFO_EDX
  • SSE : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_VERSION_INFO_EDX
  • SSE2 : CPUID_VERSION_INFO_EDX
  • SSE3 : CPUID_VERSION_INFO_ECX
  • SSE4_1 : CPUID_VERSION_INFO_ECX
  • SSE4_2 : CPUID_VERSION_INFO_ECX
  • SSE4A : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • SSSE3 : CPUID_VERSION_INFO_ECX
  • State : MSR_IA32_PERF_STATUS_REGISTER
  • StateFromL2 : MSR_P6_BBL_CR_CTL_REGISTER
  • StateToL2 : MSR_P6_BBL_CR_CTL_REGISTER
  • Stepping : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • SteppingId : CPUID_VERSION_INFO_EAX , REGISTER_CPU_FEATURE_INFORMATION
  • STOP : RTIT_TOPA_TABLE_ENTRY
  • Stopped : MSR_IA32_RTIT_STATUS_REGISTER
  • StreamingBufferDisable : MSR_P6_TEST_CTL_REGISTER
  • SubLeafType : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
  • Subtype : STM_PCI_DEVICE_PATH_NODE
  • SuppressLockEnable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • SVM : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • SW_BLOCK : MSR_IA32_DCA_0_CAP_REGISTER
  • SymmetricArbitrationID : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • SYSCALL_SYSRET : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • SystemBusFrequency : MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- t -

  • TargetedSMI : MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • TargetLinearAddress : MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
  • TargetLinearAddressHi : MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
  • TargetOffset : MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
  • TargetState : MSR_IA32_PERF_CTL_REGISTER
  • TCCActivationOffset : MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
  • TCE : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • TDC_TDPLimit : MSR_NEHALEM_PLATFORM_INFO_REGISTER
  • TDCLimit : MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
  • TDCLimitOverrideEnable : MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
  • TDP_LEVEL : MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
  • TDPLimit : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • TDPLimitOverrideEnable : MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
  • TemperatureTarget : MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
  • ThermalInterruptCoordinationEnable : MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
  • ThermalLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • ThermalSpecPower : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
  • ThermalStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • ThermalStatusLog : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold1Log : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold1Status : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold2Log : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold2Status : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThirdLevelCacheDisable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • Thread_Count : MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
  • ThreadsPerCore : CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
  • ThreeDNow : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • ThreeDNowExt : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • Threshold1 : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Threshold1Enable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Threshold2 : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Threshold2Enable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Time : MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • TimeLimit : MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
  • TimerMode : LOCAL_APIC_LVT_TIMER
  • TimeUnit : MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
  • TimeUnits : MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
  • TJOFFSET : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER
  • TM : CPUID_VERSION_INFO_EDX
  • TM1 : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • TM2 : CPUID_VERSION_INFO_ECX , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • TM_SELECT : MSR_ATOM_THERM2_CTL_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER
  • ToPA : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX , MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • TopologyExtensions : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • TotalEnergy : MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
  • TotalSize : CPU_MICROCODE_HEADER
  • TR : MSR_IA32_DEBUGCTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER
  • Trace_ToPA_PMI : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • TraceEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • TracePacketConfigurationState : MSR_IA32_XSS_REGISTER
  • TraceTransportSubsystem : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • TRANSACTION : MSR_IA32_DCA_0_CAP_REGISTER
  • TriggerEn : MSR_IA32_RTIT_STATUS_REGISTER
  • TriggerMode : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_MSI_DATA
  • TSC : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • TSC_Deadline : CPUID_VERSION_INFO_ECX
  • TSCEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • TURBO_ACTIVATION_RATIO_Lock : MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
  • TurboBoostTechnology : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • TurboFrequencyLimitingLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • TurboFrequencyLimitingStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • TurboModeDisable : MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • TurboRatioLimitConfigurationSemaphore : MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
  • TurboTransitionAttenuationLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • TurboTransitionAttenuationStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • Type : MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , STM_PCI_DEVICE_PATH_NODE
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- u -

  • Uint32 : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_EBX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_PROCESSOR_TOPOLOGY_EAX , CPUID_AMD_PROCESSOR_TOPOLOGY_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_ECX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX , CPUID_BRAND_STRING_DATA , CPUID_CACHE_INFO_CACHE_TLB , CPUID_CACHE_PARAMS_EAX , CPUID_CACHE_PARAMS_EBX , CPUID_CACHE_PARAMS_EDX , CPUID_EXTENDED_CACHE_INFO_ECX , CPUID_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX , CPUID_EXTENDED_STATE_SUB_LEAF_EAX , CPUID_EXTENDED_STATE_SUB_LEAF_ECX , CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX , CPUID_EXTENDED_TOPOLOGY_EAX , CPUID_EXTENDED_TOPOLOGY_EBX , CPUID_EXTENDED_TOPOLOGY_ECX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX , CPUID_MEMORY_ENCRYPTION_INFO_EAX , CPUID_MEMORY_ENCRYPTION_INFO_EBX , CPUID_MEMORY_ENCRYPTION_INFO_ECX , CPUID_MEMORY_ENCRYPTION_INFO_EDX , CPUID_MONITOR_MWAIT_EAX , CPUID_MONITOR_MWAIT_EBX , CPUID_MONITOR_MWAIT_ECX , CPUID_MONITOR_MWAIT_EDX , CPUID_PROCESSOR_FREQUENCY_EAX , CPUID_PROCESSOR_FREQUENCY_EBX , CPUID_PROCESSOR_FREQUENCY_ECX , CPUID_SOC_VENDOR_BRAND_STRING_DATA , CPUID_SOC_VENDOR_MAIN_LEAF_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX , CPUID_THERMAL_POWER_MANAGEMENT_EAX , CPUID_THERMAL_POWER_MANAGEMENT_EBX , CPUID_THERMAL_POWER_MANAGEMENT_ECX , CPUID_VERSION_INFO_EAX , CPUID_VERSION_INFO_EBX , CPUID_VERSION_INFO_ECX , CPUID_VERSION_INFO_EDX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX , LOCAL_APIC_ICR_HIGH , MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_ATOM_FSB_FREQ_REGISTER , MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_ATOM_PLATFORM_ID_REGISTER , MSR_ATOM_THERM2_CTL_REGISTER , MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_FEATURE_CONTROL_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_CORE_IA32_EFER_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER , MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER , MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER , MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_THREAD_ID_INFO_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_IA32_DCA_0_CAP_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_EFER_REGISTER , MSR_IA32_ENERGY_PERF_BIAS_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_FIXED_CTR_CTRL_REGISTER , MSR_IA32_HWP_CAPABILITIES_REGISTER , MSR_IA32_HWP_INTERRUPT_REGISTER , MSR_IA32_HWP_STATUS_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_MC_CTL2_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_EXT_CTL_REGISTER , MSR_IA32_MCG_STATUS_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRRCAP_REGISTER , MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_STATUS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PKG_HDC_CTL_REGISTER , MSR_IA32_PM_CTL1_REGISTER , MSR_IA32_PM_ENABLE_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_IA32_SYSENTER_CS_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_IA32_TSC_AUX_REGISTER , MSR_IA32_XSS_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER , MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_BBL_CR_ADDR_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_P6_TEST_CTL_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER , MSR_PENTIUM_4_MCG_MISC_REGISTER , MSR_PENTIUM_4_PEBS_ENABLE_REGISTER , MSR_PENTIUM_4_PLATFORM_BRV_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SEV_STATUS_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_EBL_CR_POWERON_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER , MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_PEBS_FRONTEND_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER , MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
  • Uint64 : IA32_VMX_MISC_REGISTER , MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_ATOM_FSB_FREQ_REGISTER , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_ATOM_PERF_STATUS_REGISTER , MSR_ATOM_PLATFORM_ID_REGISTER , MSR_ATOM_THERM2_CTL_REGISTER , MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_FEATURE_CONTROL_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER , MSR_CORE2_PLATFORM_ID_REGISTER , MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_CORE_IA32_EFER_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER , MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER , MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER , MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_POWER_INFO_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER , MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER , MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_THREAD_ID_INFO_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_APIC_BASE_REGISTER , MSR_IA32_BIOS_SIGN_ID_REGISTER , MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_IA32_DCA_0_CAP_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_EFER_REGISTER , MSR_IA32_ENERGY_PERF_BIAS_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_FIXED_CTR_CTRL_REGISTER , MSR_IA32_HWP_CAPABILITIES_REGISTER , MSR_IA32_HWP_INTERRUPT_REGISTER , MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER , MSR_IA32_HWP_STATUS_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_MC_CTL2_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_EXT_CTL_REGISTER , MSR_IA32_MCG_STATUS_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_MTRR_PHYSMASK_REGISTER , MSR_IA32_MTRRCAP_REGISTER , MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_PAT_REGISTER , MSR_IA32_PEBS_ENABLE_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CTL_REGISTER , MSR_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_INUSE_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_STATUS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PKG_HDC_CTL_REGISTER , MSR_IA32_PLATFORM_ID_REGISTER , MSR_IA32_PM_CTL1_REGISTER , MSR_IA32_PM_ENABLE_REGISTER , MSR_IA32_PQR_ASSOC_REGISTER , MSR_IA32_QM_CTR_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER , MSR_IA32_RTIT_ADDR_REGISTER , MSR_IA32_RTIT_CR3_MATCH_REGISTER , MSR_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER , MSR_IA32_RTIT_STATUS_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_IA32_SYSENTER_CS_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_IA32_TSC_AUX_REGISTER , MSR_IA32_VMX_BASIC_REGISTER , MSR_IA32_XSS_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER , MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PLATFORM_ID_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_BBL_CR_ADDR_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_P6_IA32_PLATFORM_ID_REGISTER , MSR_P6_MC_STATUS_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_P6_TEST_CTL_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_MCG_MISC_REGISTER , MSR_PENTIUM_4_PEBS_ENABLE_REGISTER , MSR_PENTIUM_4_PLATFORM_BRV_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER , MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SEV_STATUS_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_EBL_CR_POWERON_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER , MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_PEBS_FRONTEND_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER , MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • UMASK : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • UMIP : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • Unavailable : MSR_IA32_QM_CTR_REGISTER
  • UnhaltedCoreCycles : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • UnhaltedReferenceCycles : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • UOP : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • UpdateRevision : CPU_MICROCODE_HEADER
  • User : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • UserEcc : MSR_P6_BBL_CR_CTL_REGISTER
  • UserModeMonitorAndMwait : MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
  • USR : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x
Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

- v -

  • V : MSR_IA32_MTRR_PHYSMASK_REGISTER
  • Valid : MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
  • VCNT : MSR_IA32_MTRRCAP_REGISTER
  • Vector : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_DATA
  • Version : LOCAL_APIC_VERSION
  • VirtualAddress : MSR_IA32_RTIT_ADDR_REGISTER
  • VirtualAddressHi : MSR_IA32_RTIT_ADDR_REGISTER
  • VLD : MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
  • VmcsAddressWidth : MSR_IA32_VMX_BASIC_REGISTER
  • VmcsPhysPointer : STM_VMCS_DATABASE_REQUEST
  • VmcsRevisonId : MSR_IA32_VMX_BASIC_REGISTER
  • VmcsSize : MSR_IA32_VMX_BASIC_REGISTER
  • VME : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • VmExitEferLma : IA32_VMX_MISC_REGISTER
  • VmInjectSupported : IA32_VMX_MISC_REGISTER
  • VmWriteSupported : IA32_VMX_MISC_REGISTER
  • VMX : CPUID_VERSION_INFO_ECX
  • VmxControls : MSR_IA32_VMX_BASIC_REGISTER
  • VmxTimerRatio : IA32_VMX_MISC_REGISTER
  • VRThermalDesignCurrentLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • VRThermalDesignCurrentStatus : MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • VRThermAlertLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • VRThermAlertStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • VRThermDesignCurrentStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

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  • WaitForSipiActivityStateSupported : IA32_VMX_MISC_REGISTER
  • WakePMI : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • Way : MSR_P6_BBL_CR_CTL_REGISTER
  • Ways : CPUID_CACHE_PARAMS_EBX
  • WayToL2 : MSR_P6_BBL_CR_CTL_REGISTER
  • WC : MSR_IA32_MTRRCAP_REGISTER
  • WDT : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • WindowCntSel : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • WindowSize : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields

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Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:

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  • x2APIC : CPUID_VERSION_INFO_ECX
  • x87 : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
  • XCR0 : CPUID_EXTENDED_STATE_SUB_LEAF_ECX
  • XCR0_1 : CPUID_EXTENDED_STATE_SUB_LEAF_ECX
  • XD : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • XEOperation : MSR_CORE2_PERF_STATUS_REGISTER
  • XGETBV : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XOP : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • XSAVE : CPUID_VERSION_INFO_ECX
  • XSAVEC : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XSaveErPtr : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
  • XSAVEOPT : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XSAVES : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XSS : CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
  • XStatePolicy : STM_SMM_STATE
  • xTPR_Message_Disable : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • xTPR_Update_Control : CPUID_VERSION_INFO_ECX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • ACPI : CPUID_VERSION_INFO_EDX
  • ACPIBAR_BASE_ADDRESS : MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
  • Activity_Window : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • ADDR0_CFG : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • ADDR1_CFG : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • ADDR2_CFG : MSR_IA32_RTIT_CTL_REGISTER
  • ADDR3_CFG : MSR_IA32_RTIT_CTL_REGISTER
  • Address : MSR_P6_BBL_CR_ADDR_REGISTER
  • AddressMode : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • AddressParityCheckEnable : MSR_P6_BBL_CR_CTL3_REGISTER
  • AddressParityEnable : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • AddressRequestErrorCheckingDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • AdjacentCacheLinePrefetchDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • ADX : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • AERR_DriveEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER
  • AERR_ObservationEnabled : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER
  • AESConfiguration : MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
  • AESNI : CPUID_VERSION_INFO_ECX
  • AgentID : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • AllBranchMispredictRetired : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • AltMovCr8 : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • ANY : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER
  • AnyThread0 : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • AnyThread1 : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • AnyThread2 : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • APIC : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • ApicBase : MSR_IA32_APIC_BASE_REGISTER , MSR_P6_APIC_BASE_REGISTER
  • ApicBaseHi : MSR_IA32_APIC_BASE_REGISTER
  • APICClusterID : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ApicIdCoreIdSize : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
  • ApicIdShift : CPUID_EXTENDED_TOPOLOGY_EAX
  • ARAT : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • ARB : MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
  • ArchPerfMonVerID : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • ASCI : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • AutomaticC_StateConversionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • AutomaticThermalControlCircuit : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • AutonomousUtilizationBasedFrequencyControlLog : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • AutonomousUtilizationBasedFrequencyControlStatus : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • AUX : MSR_IA32_TSC_AUX_REGISTER
  • AVX : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_VERSION_INFO_ECX
  • AVX2 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • AVX_512 : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • BankSupport : MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • Base : MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • BaseAddress : LOCAL_APIC_MSI_ADDRESS
  • BaseFamily : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • BaseHi : MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • BaseModel : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • BasePRMRRBaseAddress : MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
  • BERR_DriverEnable : MSR_P6_EBL_CR_POWERON_REGISTER
  • BERR_Enable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER
  • BINIT_DriverDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • BINIT_DriverEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • BINIT_ObservationEnabled : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • Bits : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_EBX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_PROCESSOR_TOPOLOGY_EAX , CPUID_AMD_PROCESSOR_TOPOLOGY_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_ECX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX , CPUID_CACHE_INFO_CACHE_TLB , CPUID_CACHE_PARAMS_EAX , CPUID_CACHE_PARAMS_EBX , CPUID_CACHE_PARAMS_EDX , CPUID_EXTENDED_CACHE_INFO_ECX , CPUID_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX , CPUID_EXTENDED_STATE_SUB_LEAF_EAX , CPUID_EXTENDED_STATE_SUB_LEAF_ECX , CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX , CPUID_EXTENDED_TOPOLOGY_EAX , CPUID_EXTENDED_TOPOLOGY_EBX , CPUID_EXTENDED_TOPOLOGY_ECX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX , CPUID_MEMORY_ENCRYPTION_INFO_EAX , CPUID_MEMORY_ENCRYPTION_INFO_EBX , CPUID_MEMORY_ENCRYPTION_INFO_ECX , CPUID_MEMORY_ENCRYPTION_INFO_EDX , CPUID_MONITOR_MWAIT_EAX , CPUID_MONITOR_MWAIT_EBX , CPUID_MONITOR_MWAIT_ECX , CPUID_MONITOR_MWAIT_EDX , CPUID_PROCESSOR_FREQUENCY_EAX , CPUID_PROCESSOR_FREQUENCY_EBX , CPUID_PROCESSOR_FREQUENCY_ECX , CPUID_SOC_VENDOR_MAIN_LEAF_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX , CPUID_THERMAL_POWER_MANAGEMENT_EAX , CPUID_THERMAL_POWER_MANAGEMENT_EBX , CPUID_THERMAL_POWER_MANAGEMENT_ECX , CPUID_VERSION_INFO_EAX , CPUID_VERSION_INFO_EBX , CPUID_VERSION_INFO_ECX , CPUID_VERSION_INFO_EDX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX , IA32_VMX_MISC_REGISTER , MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_ATOM_FSB_FREQ_REGISTER , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_ATOM_PERF_STATUS_REGISTER , MSR_ATOM_PLATFORM_ID_REGISTER , MSR_ATOM_THERM2_CTL_REGISTER , MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_FEATURE_CONTROL_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER , MSR_CORE2_PLATFORM_ID_REGISTER , MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_CORE_IA32_EFER_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER , MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER , MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER , MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_POWER_INFO_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER , MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER , MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_THREAD_ID_INFO_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_APIC_BASE_REGISTER , MSR_IA32_BIOS_SIGN_ID_REGISTER , MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_IA32_DCA_0_CAP_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_EFER_REGISTER , MSR_IA32_ENERGY_PERF_BIAS_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_FIXED_CTR_CTRL_REGISTER , MSR_IA32_HWP_CAPABILITIES_REGISTER , MSR_IA32_HWP_INTERRUPT_REGISTER , MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER , MSR_IA32_HWP_STATUS_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_MC_CTL2_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_EXT_CTL_REGISTER , MSR_IA32_MCG_STATUS_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_MTRR_PHYSMASK_REGISTER , MSR_IA32_MTRRCAP_REGISTER , MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_PAT_REGISTER , MSR_IA32_PEBS_ENABLE_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CTL_REGISTER , MSR_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_INUSE_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_STATUS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PKG_HDC_CTL_REGISTER , MSR_IA32_PLATFORM_ID_REGISTER , MSR_IA32_PM_CTL1_REGISTER , MSR_IA32_PM_ENABLE_REGISTER , MSR_IA32_PQR_ASSOC_REGISTER , MSR_IA32_QM_CTR_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER , MSR_IA32_RTIT_ADDR_REGISTER , MSR_IA32_RTIT_CR3_MATCH_REGISTER , MSR_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER , MSR_IA32_RTIT_STATUS_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_IA32_SYSENTER_CS_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_IA32_TSC_AUX_REGISTER , MSR_IA32_VMX_BASIC_REGISTER , MSR_IA32_XSS_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER , MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PLATFORM_ID_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_BBL_CR_ADDR_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_P6_IA32_PLATFORM_ID_REGISTER , MSR_P6_MC_STATUS_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_P6_TEST_CTL_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_MCG_MISC_REGISTER , MSR_PENTIUM_4_PEBS_ENABLE_REGISTER , MSR_PENTIUM_4_PLATFORM_BRV_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER , MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SEV_STATUS_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_EBL_CR_POWERON_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER , MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_PEBS_FRONTEND_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER , MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • BlockSmi : MSR_IA32_SMM_MONITOR_CTL_REGISTER
  • BlockSmiSupported : IA32_VMX_MISC_REGISTER
  • BMI1 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • BMI2 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • BNDPRESERVE : MSR_IA32_BNDCFGS_REGISTER
  • BranchEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • BranchInstructionsRetired : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • BranchMonitoringEventSignaled : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • BrandIndex : CPUID_VERSION_INFO_EBX
  • BrandString : CPUID_BRAND_STRING_DATA , CPUID_SOC_VENDOR_BRAND_STRING_DATA
  • BSP : MSR_IA32_APIC_BASE_REGISTER , MSR_P6_APIC_BASE_REGISTER
  • BTF : MSR_IA32_DEBUGCTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER
  • BTINT : MSR_IA32_DEBUGCTL_REGISTER
  • BTS : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • BTS_OFF_OS : MSR_IA32_DEBUGCTL_REGISTER
  • BTS_OFF_USR : MSR_IA32_DEBUGCTL_REGISTER
  • BusFrequency : CPUID_PROCESSOR_FREQUENCY_ECX
  • BusParkDisable : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x

- c -

  • C0States : CPUID_MONITOR_MWAIT_EDX
  • C10ResidencyCounter : MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
  • C10ResidencyCounterHi : MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER
  • C1AutoDemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C1EEnable : MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER
  • C1StateAutoDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • C1StateAutoUndemotionEnable : MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • C1States : CPUID_MONITOR_MWAIT_EDX
  • C1Undemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C2States : CPUID_MONITOR_MWAIT_EDX
  • C3AutoDemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C3StateAutoDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • C3States : CPUID_MONITOR_MWAIT_EDX
  • C3Undemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • C4States : CPUID_MONITOR_MWAIT_EDX
  • C5States : CPUID_MONITOR_MWAIT_EDX
  • C6States : CPUID_MONITOR_MWAIT_EDX
  • C7States : CPUID_MONITOR_MWAIT_EDX
  • C8ResidencyCounter : MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
  • C8ResidencyCounterHi : MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
  • C9ResidencyCounter : MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
  • C9ResidencyCounterHi : MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
  • C_StateLimit : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • CacheBusFraction : MSR_P6_BBL_CR_CTL3_REGISTER
  • CacheDescriptor : CPUID_CACHE_INFO_CACHE_TLB
  • CacheInclusiveness : CPUID_CACHE_PARAMS_EDX
  • CacheLevel : CPUID_CACHE_PARAMS_EAX
  • CacheLineSize : CPUID_EXTENDED_CACHE_INFO_ECX , CPUID_VERSION_INFO_EBX
  • CacheSize : CPUID_EXTENDED_CACHE_INFO_ECX
  • CacheSizePerBank : MSR_P6_BBL_CR_CTL3_REGISTER
  • CacheStateErrorEnable : MSR_P6_BBL_CR_CTL3_REGISTER
  • CacheType : CPUID_CACHE_PARAMS_EAX
  • CapacityLength : CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
  • CAT : MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER
  • CBM : MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
  • CBox : MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
  • CFGLock : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • Checksum : CPU_MICROCODE_EXTENDED_TABLE , CPU_MICROCODE_HEADER
  • ClampingLimit : MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
  • CLFLUSHOPT : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • CLFSH : CPUID_VERSION_INFO_EDX
  • ClockFrequencyRatio : MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ClockFrequencyRatio1 : MSR_P6_EBL_CR_POWERON_REGISTER
  • ClockFrequencyRatioRead : MSR_P6_IA32_PLATFORM_ID_REGISTER
  • ClockRatio : MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
  • CLWB : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • CLZERO : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
  • CMASK : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • CMCI_EN : MSR_IA32_MC_CTL2_REGISTER
  • CMOV : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • CmpLegacy : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • CMPXCHG16B : CPUID_VERSION_INFO_ECX
  • CMPXCHG8B : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • CntAndMode : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • CntrHit0 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CntrHit1 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CNXT_ID : CPUID_VERSION_INFO_ECX
  • CodeDataPrioritization : CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
  • Compacted : CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
  • ComplexCacheIndexing : CPUID_CACHE_PARAMS_EDX
  • CondChgd : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
  • Config_TDP_Base : MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
  • Config_TDP_Lock : MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
  • Config_TDP_LVL1_Ratio : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • Config_TDP_LVL2_Ratio : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • ConfigTDPLevels : MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
  • ConfigurableAddressRanges : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
  • ConfigurablePsb : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • ContexEn : MSR_IA32_RTIT_STATUS_REGISTER
  • Core_Count : MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
  • CoreCountThresholdGroup0 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup1 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup2 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup3 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup4 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup5 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup6 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreCountThresholdGroup7 : MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
  • CoreFrequencyLimitingLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • CoreFrequencyP1Log : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • CoreId : CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
  • CorePowerLimitingLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
  • CoreVoltage : MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
  • CorrectedErrorCountThreshold : MSR_IA32_MC_CTL2_REGISTER
  • COS : MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER , MSR_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
  • CosUpdatesInfrequent : CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
  • Count : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • Count0 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • Count1 : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CountWindow : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • CPL_EQ_0 : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • CPL_NEQ_0 : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • CpuIdVersionInfoEcx : REGISTER_CPU_FEATURE_INFORMATION
  • CpuIdVersionInfoEdx : REGISTER_CPU_FEATURE_INFORMATION
  • CR3 : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
  • Cr3 : MSR_IA32_RTIT_CR3_MATCH_REGISTER
  • CR3 : MSR_IA32_RTIT_CTL_REGISTER
  • Cr3Filter : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • Cr3Hi : MSR_IA32_RTIT_CR3_MATCH_REGISTER
  • CriticalTempEnable : MSR_IA32_THERM_INTERRUPT_REGISTER
  • CriticalTempStatus : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • CriticalTempStatusLog : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • CrossDomainLimitLog : MSR_IA32_THERM_STATUS_REGISTER
  • CrossDomainLimitStatus : MSR_IA32_THERM_STATUS_REGISTER
  • CRTNParityCheckEnable : MSR_P6_BBL_CR_CTL3_REGISTER
  • CS : MSR_IA32_SYSENTER_CS_REGISTER
  • CStateAutoDemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateConversion : MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateDemotion : MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateRange : MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
  • CStateUndemotion : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
  • CStateUnDemotionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • CTR_Frz : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • CurrentCount : MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
  • CurrentCountHi : MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
  • CurrentLimitLog : MSR_IA32_THERM_STATUS_REGISTER
  • CurrentLimitStatus : MSR_IA32_THERM_STATUS_REGISTER
  • CurrentPerformanceStateValue : MSR_ATOM_PERF_STATUS_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER
  • CX8 : CPUID_VERSION_INFO_EDX
  • CYCEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • CycleThresholdEncodings : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
  • CYCThresh : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- d -

  • DataBreakpointExtension : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • DataErrorCheckingDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • DataErrorCheckingEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • DataSize : CPU_MICROCODE_HEADER
  • Date : CPU_MICROCODE_HEADER
  • DCA : CPUID_VERSION_INFO_ECX
  • DCA_ACTIVE : MSR_IA32_DCA_0_CAP_REGISTER
  • DCA_DELAY : MSR_IA32_DCA_0_CAP_REGISTER
  • DCA_QUEUE_SIZE : MSR_IA32_DCA_0_CAP_REGISTER
  • DCA_TYPE : MSR_IA32_DCA_0_CAP_REGISTER
  • DCUHardwarePrefetcherDisable : MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
  • DCUIPPrefetcherDisable : MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
  • DCUPrefetcherDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • DE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • DebugOccurred : MSR_IA32_DEBUG_INTERFACE_REGISTER
  • DeliveryMode : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_MSI_DATA
  • DeliveryStatus : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER
  • DeltaRatioGroup1 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup2 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup3 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup4 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup5 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeltaRatioGroup6 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • DeprecateFpuCsDs : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • Desired_Performance : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • Destination : LOCAL_APIC_ICR_HIGH
  • DestinationId : LOCAL_APIC_MSI_ADDRESS
  • DestinationMode : LOCAL_APIC_ICR_LOW , LOCAL_APIC_MSI_ADDRESS
  • DestinationShorthand : LOCAL_APIC_ICR_LOW
  • DigitalReadout : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • DigitalTemperatureSensor : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • Disable_LOCK : MSR_P6_TEST_CTL_REGISTER
  • DisableEnergyEfficiencyOptimization : MSR_SKYLAKE_POWER_CTL_REGISTER
  • DisableInGuest : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • DisplayFamily : REGISTER_CPU_FEATURE_INFORMATION
  • DisplayModel : REGISTER_CPU_FEATURE_INFORMATION
  • DisRETC : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • DivideValue1 : LOCAL_APIC_DCR
  • DivideValue2 : LOCAL_APIC_DCR
  • DS : CPUID_VERSION_INFO_EDX , MSR_PENTIUM_4_MCG_MISC_REGISTER
  • DS_CPL : CPUID_VERSION_INFO_ECX
  • DTES64 : CPUID_VERSION_INFO_ECX
  • DualMonitor : MSR_IA32_VMX_BASIC_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- e -

  • E : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • EbxBitVectorLength : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • ECCCheckEnable : MSR_P6_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
  • ECMD : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • EIPV : MSR_IA32_MCG_STATUS_REGISTER
  • EIST : CPUID_VERSION_INFO_ECX , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • EISTHardwareCoordinationDisable : MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
  • EISTLock : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • ElapsedCycles : MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
  • ElectricalDesignPointLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • ElectricalDesignPointStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • EN : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_IA32_APIC_BASE_REGISTER , MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • EN0_OS : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN0_PMI : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN0_Usr : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN1_OS : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN1_PMI : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN1_Usr : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN2_OS : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN2_PMI : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN2_Usr : MSR_IA32_FIXED_CTR_CTRL_REGISTER
  • EN_CALL_STACK : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER
  • EN_Excursion_Minimum : MSR_IA32_HWP_INTERRUPT_REGISTER
  • EN_FIXED_CTRn : MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
  • EN_Guaranteed_Performance_Change : MSR_IA32_HWP_INTERRUPT_REGISTER
  • EN_PMCn : MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
  • Enable : MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER
  • ENABLE_PEBS_MY_THR : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • ENABLE_PEBS_NUM_ALT : MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER
  • ENABLE_PEBS_OTH_THR : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • Enable_PPIN : MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER
  • ENABLE_UNCORE_PMI : MSR_IA32_DEBUGCTL_REGISTER
  • EnableC1Undemotion : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • EnableC3Undemotion : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
  • EnableCounting : MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
  • EnableOverflow : MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
  • EnablePlatformPowerLimit1 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • EnablePlatformPowerLimit2 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • EnableVmxInsideSmx : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • EnableVmxOutsideSmx : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER
  • END : RTIT_TOPA_TABLE_ENTRY
  • Energy : MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
  • Energy_Performance_Preference : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • EnergyPerformanceBiasEnable : MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
  • EnergyStatusUnits : MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
  • EnExcept : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • EnhancedRepMovsbStosb : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • EnLBRFrz : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • EnMonitoring : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • EoiBroadcastSuppression : LOCAL_APIC_SVR , LOCAL_APIC_VERSION
  • EpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
  • EptEnabled : STM_SMM_STATE
  • EptSupported : STM_FEAT
  • Error : MSR_IA32_QM_CTR_REGISTER , MSR_IA32_RTIT_STATUS_REGISTER
  • ErrorCode : STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 , STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
  • EventCodeSelect : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • EventCodeSelectHigh : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • EventID : MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
  • EventNum : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • EventSelect : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • Excursion_To_Minimum : MSR_IA32_HWP_STATUS_REGISTER
  • ExecuteBIST : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ExtApicSpace : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • EXTD : MSR_IA32_APIC_BASE_REGISTER
  • ExtendedApicId : CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
  • ExtendedChecksum : CPU_MICROCODE_EXTENDED_TABLE_HEADER
  • ExtendedFamilyId : CPUID_VERSION_INFO_EAX
  • ExtendedModelId : CPUID_VERSION_INFO_EAX
  • ExtendedOnDemandClockModulationDutyCycle : MSR_IA32_CLOCK_MODULATION_REGISTER
  • ExtendedSignatureCount : CPU_MICROCODE_EXTENDED_TABLE_HEADER
  • ExtensionsSupported : CPUID_MONITOR_MWAIT_ECX
  • ExtFamily : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • ExtModel : CPUID_AMD_EXTENDED_CPU_SIG_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • F16C : CPUID_VERSION_INFO_ECX
  • FabricEn : MSR_IA32_RTIT_CTL_REGISTER
  • FamilyId : CPUID_VERSION_INFO_EAX
  • FAR_BRANCH : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • FastStrings : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • FDP_EXCPTN_ONLY : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • FE : MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER
  • FERR : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER
  • FFSR : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • FFXSR : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • FilterEn : MSR_IA32_RTIT_STATUS_REGISTER
  • FIX : MSR_IA32_MTRRCAP_REGISTER
  • Fix_Me_1 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
  • Fix_Me_2 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
  • Fix_Me_3 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
  • Fix_Me_4 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
  • Fix_Me_5 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
  • Fix_Me_6 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
  • Fix_Me_7 : MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER
  • Fixed : MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
  • FIXED_CTR0 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • FIXED_CTR1 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • FIXED_CTR2 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • FixedFunctionPerformanceCounters : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
  • FixedFunctionPerformanceCounterWidth : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
  • FMA : CPUID_VERSION_INFO_ECX
  • FMA4 : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • FocusProcessorChecking : LOCAL_APIC_SVR
  • FORCEPR_Enable : MSR_IA32_THERM_INTERRUPT_REGISTER
  • FPU : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • FRCModeEnable : MSR_P6_EBL_CR_POWERON_REGISTER
  • FREEZE : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • FREEZE_LBRS_ON_PMI : MSR_IA32_DEBUGCTL_REGISTER
  • FREEZE_PERFMON_ON_PMI : MSR_IA32_DEBUGCTL_REGISTER
  • FREEZE_WHILE_SMM : MSR_IA32_DEBUGCTL_REGISTER
  • FrequencyLimitingStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • FrequencyP1Status : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • FromEtoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromEtoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromFtoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromFtoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromLinearAddress : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • FromLinearAddressHi : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • FromMtoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromMtoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromStoI : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FromStoS : MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER
  • FSGSBASE : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • FullyAssociativeCache : CPUID_CACHE_PARAMS_EAX
  • FUPonPTW : MSR_IA32_RTIT_CTL_REGISTER
  • FW_WRITE : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • FXSR : CPUID_VERSION_INFO_EDX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- g -

  • GraphicsDriverLog : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
  • GraphicsDriverStatus : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • GraphicsPowerLimitingStatus : MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • Guaranteed_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • Guaranteed_Performance_Change : MSR_IA32_HWP_STATUS_REGISTER
  • GuestPhysAddrSize : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- h -

  • HardwareCoordinationFeedback : CPUID_THERMAL_POWER_MANAGEMENT_ECX
  • HardwarePrefetcherDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • HDC : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HDC_Allow_Block : MSR_IA32_PM_CTL1_REGISTER
  • HDC_Pkg_Enable : MSR_IA32_PKG_HDC_CTL_REGISTER
  • HeaderVersion : CPU_MICROCODE_HEADER
  • HighAddressOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
  • Highest_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • HighestCosNumber : CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
  • HighSizeOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
  • HighTempEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • HLE : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • HltActivityStateSupported : IA32_VMX_MISC_REGISTER
  • HTT : CPUID_VERSION_INFO_EDX
  • HW_BLOCK : MSR_IA32_DCA_0_CAP_REGISTER
  • HWP : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_Activity_Window : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_ENABLE : MSR_IA32_PM_ENABLE_REGISTER
  • HWP_Energy_Performance_Preference : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_Notification : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • HWP_Package_Level_Request : CPUID_THERMAL_POWER_MANAGEMENT_EAX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- i -

  • IA32_FIXED_CTRn : MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
  • IA32_PERFEVTSELn : MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
  • IA32_TSC_ADJUST : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • IA32_XSS : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
  • IBS : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • IDA : MSR_IA32_PERF_CTL_REGISTER
  • IDADisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • IDQ_Bubble_Length : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • IDQ_Bubble_Width : MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
  • IN_TX : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
  • IN_TXCP : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
  • InefficientOperationLog : MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • InefficientOperationStatus : MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
  • InitialLocalApicId : CPUID_VERSION_INFO_EBX
  • InitiatorMCERR_Disable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • InOrderQueueDepth : MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • InputPinPolarity : LOCAL_APIC_LVT_LINT
  • InsOutsReporting : MSR_IA32_VMX_BASIC_REGISTER
  • InstructionsRetired : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • INT : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • IntegerBusFrequencyRatio : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER
  • IntelProcessorTrace : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • IntelTXTCapableChipset : MSR_CORE2_EBL_CR_POWERON_REGISTER
  • InternalMCERR_Disable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • InterruptAsBreak : CPUID_MONITOR_MWAIT_ECX
  • InterruptFiltering : MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
  • InterruptResponseTimeLimit : MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER
  • InterruptThresholds : CPUID_THERMAL_POWER_MANAGEMENT_EBX
  • INV : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • Invalidate : CPUID_CACHE_PARAMS_EDX
  • InvariantTsc : CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
  • INVPCID : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • IO_MWAIT : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • IPPrefetcherDisable : MSR_CORE2_IA32_MISC_ENABLE_REGISTER
  • IpTraceStopFiltering : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • IRPerf : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
  • IsVendorScheme : CPUID_SOC_VENDOR_MAIN_LEAF_EBX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- j -

  • JCC : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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- l -

  • L1DataCacheContextMode : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • L2AddressRange : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2AdjacentCacheLinePrefetcherDisable : MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
  • L2Associativity : CPUID_EXTENDED_CACHE_INFO_ECX , MSR_P6_BBL_CR_CTL3_REGISTER
  • L2Banks : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2CacheAllocation : CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
  • L2CacheLatency : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2CacheLatencyRead : MSR_P6_IA32_PLATFORM_ID_REGISTER
  • L2Command : MSR_P6_BBL_CR_CTL_REGISTER
  • L2Configured : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2Enabled : MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
  • L2HardwareDisable : MSR_P6_BBL_CR_CTL3_REGISTER
  • L2HardwareEnabled : MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
  • L2HardwarePrefetcherDisable : MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
  • L2Hit : MSR_P6_BBL_CR_CTL_REGISTER
  • L2NotPresent : MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
  • L3CacheAllocation : CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
  • L3CacheLocalBandwidthMonitoring : CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
  • L3CacheOccupancyMonitoring : CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
  • L3CacheRDT_M : CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
  • L3CacheTotalBandwidthMonitoring : CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
  • LAHF_SAHF : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_ECX
  • LargestMonitorLineSize : CPUID_MONITOR_MWAIT_EBX
  • LastLevelCacheMisses : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • LastLevelCacheReferences : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • LBR : MSR_IA32_DEBUGCTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER
  • LBR_FMT : MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER
  • LBR_Frz : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • LBRsValid : MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
  • Length : STM_PCI_DEVICE_PATH_NODE
  • Level : LOCAL_APIC_ICR_LOW , LOCAL_APIC_MSI_DATA
  • LevelNumber : CPUID_EXTENDED_TOPOLOGY_ECX
  • LevelType : CPUID_EXTENDED_TOPOLOGY_ECX
  • Limit : MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • LimitCpuidMaxval : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • LinearAddressBits : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX
  • LinePartitions : CPUID_CACHE_PARAMS_EBX
  • LineSize : CPUID_CACHE_PARAMS_EBX
  • LIP : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • LL_EN_PMC0 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LL_EN_PMC1 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LL_EN_PMC2 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LL_EN_PMC3 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • LM : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • LMA : MSR_IA32_EFER_REGISTER
  • LMCE_EN : MSR_IA32_MCG_EXT_CTL_REGISTER
  • LMCE_S : MSR_IA32_MCG_STATUS_REGISTER
  • LmceOn : MSR_IA32_FEATURE_CONTROL_REGISTER
  • LME : MSR_IA32_EFER_REGISTER
  • LoaderRevision : CPU_MICROCODE_HEADER
  • Lock : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • LockOut : MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER
  • Logical_Processor_ID : MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
  • LogicalProcessors : CPUID_EXTENDED_TOPOLOGY_EBX
  • Long_Flow_Indication : MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • LONGRESET : MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
  • LowAddressOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
  • Lowest_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • LowPowerModeEnable : MSR_P6_EBL_CR_POWERON_REGISTER
  • LowPowerModeSupport : MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
  • LowSizeOfEpcSection : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
  • LowTempEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • LPLLSelect : MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
  • Lvl2Base : MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
  • LWP : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • LZCNT : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_ECX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

  • All
  • Variables
  • a
  • b
  • c
  • d
  • e
  • f
  • g
  • h
  • i
  • j
  • l
  • m
  • n
  • o
  • p
  • r
  • s
  • t
  • u
  • v
  • w
  • x

- m -

  • Mask : LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER
  • MaskOrTableOffset : MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
  • MAWAU : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • MAX_NON_TURBO_RATIO : MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
  • MAX_RATIO : MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
  • MaxCoresGroup0 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxEnclaveSize_64 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
  • MaxEnclaveSize_Not64 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
  • Maximum10C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum11C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum12C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum13C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum14C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum15C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum16C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum17C : MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
  • Maximum18C : MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
  • Maximum1C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum2C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum3C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum4C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum5C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum6C : MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum7C : MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum8C : MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
  • Maximum9C : MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
  • Maximum_Performance : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • MaximumAddressableIdsForLogicalProcessors : CPUID_CACHE_PARAMS_EAX , CPUID_VERSION_INFO_EBX
  • MaximumAddressableIdsForProcessorCores : CPUID_CACHE_PARAMS_EAX
  • MaximumBusRatio : MSR_ATOM_PERF_STATUS_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER
  • MaximumEfficiencyFrequencyLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • MaximumEfficiencyFrequencyStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • MaximumEfficiencyRatio : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • MaximumFrequency : CPUID_PROCESSOR_FREQUENCY_EBX
  • MaximumNon_TurboRatio : MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • MaximumNonTurboRatio : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • MaximumPower : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
  • MaximumQualifiedRatio : MSR_ATOM_PLATFORM_ID_REGISTER , MSR_CORE2_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER
  • MaximumTimeWindow : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
  • MaxIncrementalCoresGroup1 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup2 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup3 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup4 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup5 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxIncrementalCoresGroup6 : MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxLvtEntry : LOCAL_APIC_VERSION
  • MaxRatioLimitGroup0 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup1 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup2 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup3 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup4 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup5 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup6 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxRatioLimitGroup7 : MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
  • MaxTurboLimitLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • MaxTurboLimitStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • MC_STATUS_ADDRV : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_DAM : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_EN : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_MCACOD : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_MISCV : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_MSCOD : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_O : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_UC : MSR_P6_MC_STATUS_REGISTER
  • MC_STATUS_V : MSR_P6_MC_STATUS_REGISTER
  • MCA : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MCE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MCERR_DriveEnable : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • MCERR_ObservationDisabled : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • MCERR_ObservationEnabled : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • MCG_CTL_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_ELOG_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_EM_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_EXT_CNT : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_EXT_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_LMCE_P : MSR_IA32_MCG_CAP_REGISTER
  • MCG_SER_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCG_TES_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MCIP : MSR_IA32_MCG_STATUS_REGISTER
  • MCP_CMCI_P : MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER
  • MemErrorLogEnable : MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
  • MemoryType : MSR_IA32_VMX_BASIC_REGISTER
  • MemTypePRMRRBASEMemType : MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
  • MESI : MSR_P6_BBL_CR_CTL_REGISTER
  • MicrocodeUpdateSignature : MSR_IA32_BIOS_SIGN_ID_REGISTER
  • MIN_RATIO : MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
  • MinAsid : CPUID_MEMORY_ENCRYPTION_INFO_EDX
  • Minimum_Performance : MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER
  • MinimumOperatingRatio : MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
  • MinimumPower : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
  • MinimumThreshold : MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
  • MisAlignSse : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • Mispred : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • MMX : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MmxExt : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • Model : CPUID_VERSION_INFO_EAX
  • MONITOR : CPUID_VERSION_INFO_ECX , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • MonitorFeatures : MSEG_HEADER
  • Most_Efficient_Performance : MSR_IA32_HWP_CAPABILITIES_REGISTER
  • MOVBE : CPUID_VERSION_INFO_ECX
  • MPX : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • MsegBase : MSR_IA32_SMM_MONITOR_CTL_REGISTER
  • MsegHeaderRevision : MSEG_HEADER
  • MsegRevisionIdentifier : IA32_VMX_MISC_REGISTER
  • MSR : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MsrStoreListMaximum : IA32_VMX_MISC_REGISTER
  • Mtc : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • MTCEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • MTCFreq : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • MtcPeriodEncodings : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
  • MTRR : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • MultiCoreTurboLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • MultiCoreTurboStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • MwaitExtended : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • MWAITRedirectionEnable : MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • Variables
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- n -

  • NC : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
  • NEAR_IND_CALL : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_IND_JMP : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_REL_CALL : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_REL_JMP : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NEAR_RET : MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER
  • NodeId : CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
  • NodesPerProcessor : CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
  • NonIntegerBusRatio : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER
  • NotUsed : CPUID_VERSION_INFO_ECX
  • NotValid : CPUID_CACHE_INFO_CACHE_TLB
  • NumberOfCr3TargetValues : IA32_VMX_MISC_REGISTER
  • NUMCORE_0 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_1 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_2 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_3 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_4 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_5 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_6 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NUMCORE_7 : MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
  • NumGuests : CPUID_MEMORY_ENCRYPTION_INFO_ECX
  • NX : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • NXE : MSR_CORE_IA32_EFER_REGISTER , MSR_IA32_EFER_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • Variables
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  • OnDemandClockModulationDutyCycle : MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
  • OnDemandClockModulationEnable : MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
  • OS : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • OSPKE : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • OSVW : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • OSXSAVE : CPUID_VERSION_INFO_ECX
  • OtherLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • OtherStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • OutputOffset : MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
  • OutputTriStateEnable : MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • OutputTriStateEnabled : MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
  • OverheatEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
  • Ovf_BufDSSAVE : MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FIXED_CTRn : MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FixedCtr0 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FixedCtr1 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_FixedCtr2 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC0 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC1 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC2 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC3 : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC4 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC5 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC6 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMC7 : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_PMCn : MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • Ovf_Uncore : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • OvfBuf : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • Variables
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  • PA0 : MSR_IA32_PAT_REGISTER
  • PA1 : MSR_IA32_PAT_REGISTER
  • PA2 : MSR_IA32_PAT_REGISTER
  • PA3 : MSR_IA32_PAT_REGISTER
  • PA4 : MSR_IA32_PAT_REGISTER
  • PA5 : MSR_IA32_PAT_REGISTER
  • PA6 : MSR_IA32_PAT_REGISTER
  • PA7 : MSR_IA32_PAT_REGISTER
  • Package_Control : MSR_IA32_HWP_REQUEST_REGISTER
  • PacketByteCnt : MSR_IA32_RTIT_STATUS_REGISTER
  • PAE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • Page1GB : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • PageFlushMsrBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX
  • PAT : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • PB0 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PB1 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PB2 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PB3 : MSR_P6_DEBUGCTLMSR_REGISTER
  • PBE : CPUID_VERSION_INFO_EDX
  • PC : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • PCID : CPUID_VERSION_INFO_ECX
  • PCIERatio : MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
  • PCIExpressRequestorID : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • PCIExpressSegmentNumber : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • PCLMULQDQ : CPUID_VERSION_INFO_ECX
  • PCM0_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM1_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM2_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM3_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM4_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM5_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM6_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCM7_EN : MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
  • PCUControllerError : MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
  • PCUFirmwareError : MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
  • PCUHardwareError : MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
  • PDCM : CPUID_VERSION_INFO_ECX
  • PEBS : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • PEBS_ARCH_REG : MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER
  • PEBS_EN_PMC0 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_EN_PMC1 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_EN_PMC2 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_EN_PMC3 : MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PEBS_FMT : MSR_CORE2_PERF_CAPABILITIES_REGISTER
  • PEBS_REC_FMT : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • PEBS_TRAP : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • PerfCtrExtCore : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • PerfCtrExtL3 : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • PerformanceEnergyBias : CPUID_THERMAL_POWER_MANAGEMENT_ECX
  • PerformanceMonitorCounters : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • PerformanceMonitorCounterWidth : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
  • PerformanceMonitoring : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • PerfTsc : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • PerfTscSize : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
  • PGE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • PhysBase : MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER
  • PhysBaseHi : MSR_IA32_MTRR_PHYSBASE_REGISTER
  • PhysicalAddressBits : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX
  • PhysMask : MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_IA32_MTRR_PHYSMASK_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER
  • PhysMaskHi : MSR_IA32_MTRR_PHYSMASK_REGISTER
  • PKG_Cx_Monitor : MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
  • PKG_MAX_PWR_LVL1 : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • PKG_MAX_PWR_LVL2 : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • PKG_MIN_PWR_LVL1 : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • PKG_MIN_PWR_LVL2 : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • PKG_TDP_LVL1 : MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
  • PKG_TDP_LVL2 : MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
  • PKGC_StateAutoDemotionEnable : MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
  • PkgType : CPUID_AMD_EXTENDED_CPU_SIG_EBX
  • PKRU : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
  • PKU : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • PL1Log : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PL1Status : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
  • PL1STatus : MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
  • PL1Status : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PL2Log : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PL2Status : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • PLATFORM : MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
  • PlatformClampingLimitation1 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PlatformClampingLimitation2 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PlatformConfigurationServicesLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PlatformConfigurationServicesStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PlatformId : MSR_CORE2_PLATFORM_ID_REGISTER , MSR_IA32_PLATFORM_ID_REGISTER , MSR_NEHALEM_PLATFORM_ID_REGISTER , MSR_P6_IA32_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER
  • PlatformPowerLimit1 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PlatformPowerLimit2 : MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • PLLog : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
  • PLN : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • PLStatus : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
  • PMI : MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
  • PMI_Sel_Core0 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Core1 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Core2 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Core3 : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice0 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice1 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice2 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice3 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • PMI_Sel_Slice4 : MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • POPCNT : CPUID_VERSION_INFO_ECX
  • PowerBudgetManagementLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PowerBudgetManagementStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PowerEventTrace : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • PowerLimitingStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • PowerLimitLog : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • PowerLimitNotificationEnable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • PowerLimitStatus : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • PowerPolicyPreference : MSR_IA32_ENERGY_PERF_BIAS_REGISTER
  • PowerUnits : MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
  • PPIN_CAP : MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER
  • PrefetchQueueDisable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • PREFETCHW : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_ECX
  • PREFETCHWT1 : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • ProcessorBaseFrequency : CPUID_PROCESSOR_FREQUENCY_EAX
  • ProcessorFlag : CPU_MICROCODE_EXTENDED_TABLE
  • ProcessorFlags : CPU_MICROCODE_HEADER
  • ProcessorInfo : REGISTER_CPU_FEATURE_INFORMATION
  • ProcessorNumber : MSR_P6_BBL_CR_CTL_REGISTER
  • ProcessorSignature : CPU_MICROCODE_EXTENDED_TABLE , CPU_MICROCODE_HEADER
  • ProcessorTraceSupported : IA32_VMX_MISC_REGISTER
  • ProcessorType : CPUID_VERSION_INFO_EAX , REGISTER_CPU_FEATURE_INFORMATION
  • PROCHOT : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • PROCHOT_Enable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • PROCHOT_Event : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
  • PROCHOT_FORCEPR_Event : MSR_IA32_THERM_STATUS_REGISTER
  • PROCHOT_FORCEPR_Log : MSR_IA32_THERM_STATUS_REGISTER
  • PROCHOT_Log : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • PROCHOT_Status : MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • PROCHOTStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
  • ProgrammableRatioLimit : MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • ProgrammableTDPLimit : MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • ProgrammableTJOFFSET : MSR_SKYLAKE_PLATFORM_INFO_REGISTER
  • PS_EN : MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
  • PSBFreq : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • PsbFrequencyEncodings : CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
  • PSE : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • PSE36 : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • PSE_36 : CPUID_VERSION_INFO_EDX
  • PSN : CPUID_VERSION_INFO_EDX
  • PT : CPUID_EXTENDED_STATE_SUB_LEAF_ECX
  • PtePosBits : CPUID_MEMORY_ENCRYPTION_INFO_EBX
  • PTM : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • PTWEn : MSR_IA32_RTIT_CTL_REGISTER
  • PTWrite : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
  • PwrEvtEn : MSR_IA32_RTIT_CTL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • Variables
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  • RatioLimit : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • RCNT_SCNT : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • RDPID : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • RDRAND : CPUID_VERSION_INFO_ECX
  • RDSEED : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RDT_A : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RDT_M : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RDTSCP : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • ReadingValid : MSR_IA32_THERM_STATUS_REGISTER
  • RecoverableAddressLSB : MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
  • RedirectionHint : LOCAL_APIC_MSI_ADDRESS
  • ReducedPhysBits : CPUID_MEMORY_ENCRYPTION_INFO_EBX
  • ReinitializeVmcsRequired : STM_SMM_RESUME_STATE
  • RemoteIrr : LOCAL_APIC_LVT_LINT
  • Reserved : CPU_MICROCODE_EXTENDED_TABLE_HEADER , CPU_MICROCODE_HEADER , CPUID_AMD_EXTENDED_CPU_SIG_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_ECX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX , CPUID_CACHE_PARAMS_EAX , MSEG_HEADER , SOFTWARE_STM_HEADER , STM_FEAT
  • Reserved0 : LOCAL_APIC_DCR , LOCAL_APIC_ICR_HIGH , LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_ADDRESS , LOCAL_APIC_MSI_DATA , LOCAL_APIC_SVR , LOCAL_APIC_VERSION
  • Reserved1 : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_VERSION_INFO_EAX , LOCAL_APIC_DCR , LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_ADDRESS , LOCAL_APIC_MSI_DATA , LOCAL_APIC_SVR , LOCAL_APIC_VERSION , MSR_IA32_PEBS_ENABLE_REGISTER , STM_VMCS_DATABASE_REQUEST
  • Reserved2 : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_VERSION_INFO_EAX , LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_DATA , STM_SMM_RESUME_STATE
  • Reserved3 : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , MSR_IA32_PEBS_ENABLE_REGISTER
  • Reserved4 : CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • ReservedBits : CPUID_MEMORY_ENCRYPTION_INFO_EAX , CPUID_MEMORY_ENCRYPTION_INFO_EBX
  • ResetVector : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • ResidencyStateRegulationLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • ResidencyStateRegulationStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • ResolutionInDegreesCelsius : MSR_IA32_THERM_STATUS_REGISTER
  • ResourceMonitoredData : MSR_IA32_QM_CTR_REGISTER
  • ResourceMonitoredDataHi : MSR_IA32_QM_CTR_REGISTER
  • ResourceMonitoringID : MSR_IA32_PQR_ASSOC_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER
  • ResponseErrorCheckingDisable : MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
  • ResponseErrorCheckingEnable : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • RIPV : MSR_IA32_MCG_STATUS_REGISTER
  • RMID : MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
  • RTIT : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • RTM : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • RTM_DEBUG : MSR_IA32_DEBUGCTL_REGISTER
  • RunningAverageThermalLimitLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • RunningAverageThermalLimitStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • ScalableBusSpeed : MSR_ATOM_FSB_FREQ_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER
  • SCE : MSR_IA32_EFER_REGISTER
  • SDBG : CPUID_VERSION_INFO_ECX
  • SelfInitializingCache : CPUID_CACHE_PARAMS_EAX
  • SenterGlobalEnable : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • SenterLocalFunctionEnables : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • SEP : CPUID_VERSION_INFO_EDX
  • SevBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX , MSR_SEV_STATUS_REGISTER
  • SevEsBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX , MSR_SEV_STATUS_REGISTER
  • SGX : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • SGX1 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
  • SGX2 : CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
  • SGX_LC : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • SGX_SVN_SINIT : MSR_IA32_SGX_SVN_STATUS_REGISTER
  • SgxEnable : MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER
  • SgxLaunchControlEnable : MSR_IA32_FEATURE_CONTROL_REGISTER
  • SHA : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • ShutdownActivityStateSupported : IA32_VMX_MISC_REGISTER
  • SignedExtension : MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
  • SignExt_VA : MSR_IA32_RTIT_ADDR_REGISTER
  • SingleRangeOutput : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • Size : RTIT_TOPA_TABLE_ENTRY
  • SKINIT : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • SmallestMonitorLineSize : CPUID_MONITOR_MWAIT_EAX
  • SMAP : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • SmBaseMsrSupported : IA32_VMX_MISC_REGISTER
  • SmeBit : CPUID_MEMORY_ENCRYPTION_INFO_EAX
  • SMEP : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
  • SMICount : MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER
  • SMM_Code_Access_Chk : MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • SMM_Code_Chk_En : MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
  • SMM_CPU_SVRSTR : MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • SMM_FREEZE : MSR_IA32_PERF_CAPABILITIES_REGISTER
  • SMRR : MSR_IA32_MTRRCAP_REGISTER
  • SMRREnable : MSR_CORE2_FEATURE_CONTROL_REGISTER
  • SMX : CPUID_VERSION_INFO_ECX
  • SocVendorId : CPUID_SOC_VENDOR_MAIN_LEAF_EBX
  • SoftwareEnable : LOCAL_APIC_SVR
  • SplitLockDisable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • SpuriousVector : LOCAL_APIC_SVR
  • SS : CPUID_VERSION_INFO_EDX
  • SSE : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_VERSION_INFO_EDX
  • SSE2 : CPUID_VERSION_INFO_EDX
  • SSE3 : CPUID_VERSION_INFO_ECX
  • SSE4_1 : CPUID_VERSION_INFO_ECX
  • SSE4_2 : CPUID_VERSION_INFO_ECX
  • SSE4A : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • SSSE3 : CPUID_VERSION_INFO_ECX
  • State : MSR_IA32_PERF_STATUS_REGISTER
  • StateFromL2 : MSR_P6_BBL_CR_CTL_REGISTER
  • StateToL2 : MSR_P6_BBL_CR_CTL_REGISTER
  • Stepping : CPUID_AMD_EXTENDED_CPU_SIG_EAX
  • SteppingId : CPUID_VERSION_INFO_EAX , REGISTER_CPU_FEATURE_INFORMATION
  • STOP : RTIT_TOPA_TABLE_ENTRY
  • Stopped : MSR_IA32_RTIT_STATUS_REGISTER
  • StreamingBufferDisable : MSR_P6_TEST_CTL_REGISTER
  • SubLeafType : CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
  • Subtype : STM_PCI_DEVICE_PATH_NODE
  • SuppressLockEnable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • SVM : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • SW_BLOCK : MSR_IA32_DCA_0_CAP_REGISTER
  • SymmetricArbitrationID : MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
  • SYSCALL_SYSRET : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_CPU_SIG_EDX
  • SystemBusFrequency : MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • TargetedSMI : MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
  • TargetLinearAddress : MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
  • TargetLinearAddressHi : MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
  • TargetOffset : MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
  • TargetState : MSR_IA32_PERF_CTL_REGISTER
  • TCCActivationOffset : MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
  • TCE : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • TDC_TDPLimit : MSR_NEHALEM_PLATFORM_INFO_REGISTER
  • TDCLimit : MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
  • TDCLimitOverrideEnable : MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
  • TDP_LEVEL : MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
  • TDPLimit : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER
  • TDPLimitOverrideEnable : MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
  • TemperatureTarget : MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
  • ThermalInterruptCoordinationEnable : MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
  • ThermalLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • ThermalSpecPower : MSR_GOLDMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
  • ThermalStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • ThermalStatusLog : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold1Log : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold1Status : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold2Log : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThermalThreshold2Status : MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_THERM_STATUS_REGISTER
  • ThirdLevelCacheDisable : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • Thread_Count : MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
  • ThreadsPerCore : CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
  • ThreeDNow : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • ThreeDNowExt : CPUID_AMD_EXTENDED_CPU_SIG_EDX
  • Threshold1 : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Threshold1Enable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Threshold2 : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Threshold2Enable : MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER
  • Time : MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
  • TimeLimit : MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
  • TimerMode : LOCAL_APIC_LVT_TIMER
  • TimeUnit : MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
  • TimeUnits : MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
  • TJOFFSET : MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER
  • TM : CPUID_VERSION_INFO_EDX
  • TM1 : MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • TM2 : CPUID_VERSION_INFO_ECX , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
  • TM_SELECT : MSR_ATOM_THERM2_CTL_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER
  • ToPA : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX , MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • TopologyExtensions : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • TotalEnergy : MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
  • TotalSize : CPU_MICROCODE_HEADER
  • TR : MSR_IA32_DEBUGCTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER
  • Trace_ToPA_PMI : MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
  • TraceEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • TracePacketConfigurationState : MSR_IA32_XSS_REGISTER
  • TraceTransportSubsystem : CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
  • TRANSACTION : MSR_IA32_DCA_0_CAP_REGISTER
  • TriggerEn : MSR_IA32_RTIT_STATUS_REGISTER
  • TriggerMode : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_MSI_DATA
  • TSC : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • TSC_Deadline : CPUID_VERSION_INFO_ECX
  • TSCEn : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • TURBO_ACTIVATION_RATIO_Lock : MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
  • TurboBoostTechnology : CPUID_THERMAL_POWER_MANAGEMENT_EAX
  • TurboFrequencyLimitingLog : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • TurboFrequencyLimitingStatus : MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • TurboModeDisable : MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • TurboRatioLimitConfigurationSemaphore : MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
  • TurboTransitionAttenuationLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • TurboTransitionAttenuationStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
  • Type : MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , STM_PCI_DEVICE_PATH_NODE
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

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  • Variables
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- u -

  • Uint32 : CPUID_AMD_EXTENDED_CPU_SIG_EAX , CPUID_AMD_EXTENDED_CPU_SIG_EBX , CPUID_AMD_EXTENDED_CPU_SIG_ECX , CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_AMD_PROCESSOR_TOPOLOGY_EAX , CPUID_AMD_PROCESSOR_TOPOLOGY_EBX , CPUID_AMD_PROCESSOR_TOPOLOGY_ECX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX , CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX , CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX , CPUID_BRAND_STRING_DATA , CPUID_CACHE_INFO_CACHE_TLB , CPUID_CACHE_PARAMS_EAX , CPUID_CACHE_PARAMS_EBX , CPUID_CACHE_PARAMS_EDX , CPUID_EXTENDED_CACHE_INFO_ECX , CPUID_EXTENDED_CPU_SIG_ECX , CPUID_EXTENDED_CPU_SIG_EDX , CPUID_EXTENDED_STATE_MAIN_LEAF_EAX , CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX , CPUID_EXTENDED_STATE_SUB_LEAF_EAX , CPUID_EXTENDED_STATE_SUB_LEAF_ECX , CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX , CPUID_EXTENDED_TOPOLOGY_EAX , CPUID_EXTENDED_TOPOLOGY_EBX , CPUID_EXTENDED_TOPOLOGY_ECX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX , CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX , CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX , CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX , CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX , CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX , CPUID_MEMORY_ENCRYPTION_INFO_EAX , CPUID_MEMORY_ENCRYPTION_INFO_EBX , CPUID_MEMORY_ENCRYPTION_INFO_ECX , CPUID_MEMORY_ENCRYPTION_INFO_EDX , CPUID_MONITOR_MWAIT_EAX , CPUID_MONITOR_MWAIT_EBX , CPUID_MONITOR_MWAIT_ECX , CPUID_MONITOR_MWAIT_EDX , CPUID_PROCESSOR_FREQUENCY_EAX , CPUID_PROCESSOR_FREQUENCY_EBX , CPUID_PROCESSOR_FREQUENCY_ECX , CPUID_SOC_VENDOR_BRAND_STRING_DATA , CPUID_SOC_VENDOR_MAIN_LEAF_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX , CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX , CPUID_THERMAL_POWER_MANAGEMENT_EAX , CPUID_THERMAL_POWER_MANAGEMENT_EBX , CPUID_THERMAL_POWER_MANAGEMENT_ECX , CPUID_VERSION_INFO_EAX , CPUID_VERSION_INFO_EBX , CPUID_VERSION_INFO_ECX , CPUID_VERSION_INFO_EDX , CPUID_VIR_PHY_ADDRESS_SIZE_EAX , LOCAL_APIC_ICR_HIGH , MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_ATOM_FSB_FREQ_REGISTER , MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_ATOM_PLATFORM_ID_REGISTER , MSR_ATOM_THERM2_CTL_REGISTER , MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_FEATURE_CONTROL_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_CORE_IA32_EFER_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER , MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER , MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER , MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_THREAD_ID_INFO_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_IA32_DCA_0_CAP_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_EFER_REGISTER , MSR_IA32_ENERGY_PERF_BIAS_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_FIXED_CTR_CTRL_REGISTER , MSR_IA32_HWP_CAPABILITIES_REGISTER , MSR_IA32_HWP_INTERRUPT_REGISTER , MSR_IA32_HWP_STATUS_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_MC_CTL2_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_EXT_CTL_REGISTER , MSR_IA32_MCG_STATUS_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRRCAP_REGISTER , MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_STATUS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PKG_HDC_CTL_REGISTER , MSR_IA32_PM_CTL1_REGISTER , MSR_IA32_PM_ENABLE_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_IA32_SYSENTER_CS_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_IA32_TSC_AUX_REGISTER , MSR_IA32_XSS_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER , MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_BBL_CR_ADDR_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_P6_TEST_CTL_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER , MSR_PENTIUM_4_MCG_MISC_REGISTER , MSR_PENTIUM_4_PEBS_ENABLE_REGISTER , MSR_PENTIUM_4_PLATFORM_BRV_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SEV_STATUS_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_EBL_CR_POWERON_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER , MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_PEBS_FRONTEND_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER , MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
  • Uint64 : IA32_VMX_MISC_REGISTER , MSR_ATOM_BBL_CR_CTL3_REGISTER , MSR_ATOM_EBL_CR_POWERON_REGISTER , MSR_ATOM_FSB_FREQ_REGISTER , MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_ATOM_PEBS_ENABLE_REGISTER , MSR_ATOM_PERF_STATUS_REGISTER , MSR_ATOM_PLATFORM_ID_REGISTER , MSR_ATOM_THERM2_CTL_REGISTER , MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_CORE2_EBL_CR_POWERON_REGISTER , MSR_CORE2_FEATURE_CONTROL_REGISTER , MSR_CORE2_FSB_FREQ_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_PEBS_ENABLE_REGISTER , MSR_CORE2_PERF_CAPABILITIES_REGISTER , MSR_CORE2_PERF_STATUS_REGISTER , MSR_CORE2_PLATFORM_ID_REGISTER , MSR_CORE2_SMRR_PHYSBASE_REGISTER , MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_CORE2_THERM2_CTL_REGISTER , MSR_CORE_BBL_CR_CTL3_REGISTER , MSR_CORE_EBL_CR_POWERON_REGISTER , MSR_CORE_FSB_FREQ_REGISTER , MSR_CORE_IA32_EFER_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_CORE_THERM2_CTL_REGISTER , MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_GOLDMONT_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER , MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER , MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER , MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER , MSR_GOLDMONT_LBR_SELECT_REGISTER , MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER , MSR_GOLDMONT_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_GOLDMONT_PKG_POWER_INFO_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_GOLDMONT_PLATFORM_INFO_REGISTER , MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER , MSR_GOLDMONT_POWER_CTL_REGISTER , MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER , MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER , MSR_GOLDMONT_SMM_MCA_CAP_REGISTER , MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER , MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER , MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER , MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER , MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER , MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER , MSR_HASWELL_E_ERROR_CONTROL_REGISTER , MSR_HASWELL_E_IA32_MCG_CAP_REGISTER , MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER , MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER , MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER , MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_E_SMM_MCA_CAP_REGISTER , MSR_HASWELL_E_THREAD_ID_INFO_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER , MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_HASWELL_LBR_SELECT_REGISTER , MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER , MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER , MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_HASWELL_PLATFORM_INFO_REGISTER , MSR_HASWELL_RAPL_POWER_UNIT_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER , MSR_HASWELL_SMM_MCA_CAP_REGISTER , MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER , MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER , MSR_HASWELL_UNC_CBO_CONFIG_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER , MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_APIC_BASE_REGISTER , MSR_IA32_BIOS_SIGN_ID_REGISTER , MSR_IA32_BNDCFGS_REGISTER , MSR_IA32_CLOCK_MODULATION_REGISTER , MSR_IA32_DCA_0_CAP_REGISTER , MSR_IA32_DEBUG_INTERFACE_REGISTER , MSR_IA32_DEBUGCTL_REGISTER , MSR_IA32_EFER_REGISTER , MSR_IA32_ENERGY_PERF_BIAS_REGISTER , MSR_IA32_FEATURE_CONTROL_REGISTER , MSR_IA32_FIXED_CTR_CTRL_REGISTER , MSR_IA32_HWP_CAPABILITIES_REGISTER , MSR_IA32_HWP_INTERRUPT_REGISTER , MSR_IA32_HWP_REQUEST_PKG_REGISTER , MSR_IA32_HWP_REQUEST_REGISTER , MSR_IA32_HWP_STATUS_REGISTER , MSR_IA32_L2_QOS_CFG_REGISTER , MSR_IA32_L3_QOS_CFG_REGISTER , MSR_IA32_MC_CTL2_REGISTER , MSR_IA32_MCG_CAP_REGISTER , MSR_IA32_MCG_EXT_CTL_REGISTER , MSR_IA32_MCG_STATUS_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MTRR_DEF_TYPE_REGISTER , MSR_IA32_MTRR_PHYSBASE_REGISTER , MSR_IA32_MTRR_PHYSMASK_REGISTER , MSR_IA32_MTRRCAP_REGISTER , MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER , MSR_IA32_PACKAGE_THERM_STATUS_REGISTER , MSR_IA32_PAT_REGISTER , MSR_IA32_PEBS_ENABLE_REGISTER , MSR_IA32_PERF_CAPABILITIES_REGISTER , MSR_IA32_PERF_CTL_REGISTER , MSR_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_INUSE_REGISTER , MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_IA32_PERF_STATUS_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PKG_HDC_CTL_REGISTER , MSR_IA32_PLATFORM_ID_REGISTER , MSR_IA32_PM_CTL1_REGISTER , MSR_IA32_PM_ENABLE_REGISTER , MSR_IA32_PQR_ASSOC_REGISTER , MSR_IA32_QM_CTR_REGISTER , MSR_IA32_QM_EVTSEL_REGISTER , MSR_IA32_RTIT_ADDR_REGISTER , MSR_IA32_RTIT_CR3_MATCH_REGISTER , MSR_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_OUTPUT_BASE_REGISTER , MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER , MSR_IA32_RTIT_STATUS_REGISTER , MSR_IA32_SGX_SVN_STATUS_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSBASE_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_IA32_SYSENTER_CS_REGISTER , MSR_IA32_THERM_INTERRUPT_REGISTER , MSR_IA32_THERM_STATUS_REGISTER , MSR_IA32_TSC_AUX_REGISTER , MSR_IA32_VMX_BASIC_REGISTER , MSR_IA32_XSS_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER , MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER , MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER , MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER , MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_IVY_BRIDGE_PPIN_CTL_REGISTER , MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER , MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER , MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_LBR_SELECT_REGISTER , MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER , MSR_NEHALEM_MISC_PWR_MGMT_REGISTER , MSR_NEHALEM_PEBS_ENABLE_REGISTER , MSR_NEHALEM_PEBS_LD_LAT_REGISTER , MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER , MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_NEHALEM_PLATFORM_ID_REGISTER , MSR_NEHALEM_PLATFORM_INFO_REGISTER , MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER , MSR_NEHALEM_POWER_CTL_REGISTER , MSR_NEHALEM_SMI_COUNT_REGISTER , MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER , MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER , MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER , MSR_P6_APIC_BASE_REGISTER , MSR_P6_BBL_CR_ADDR_REGISTER , MSR_P6_BBL_CR_CTL3_REGISTER , MSR_P6_BBL_CR_CTL_REGISTER , MSR_P6_DEBUGCTLMSR_REGISTER , MSR_P6_EBL_CR_POWERON_REGISTER , MSR_P6_IA32_PLATFORM_ID_REGISTER , MSR_P6_MC_STATUS_REGISTER , MSR_P6_MTRRDEFTYPE_REGISTER , MSR_P6_PERFEVTSEL_REGISTER , MSR_P6_TEST_CTL_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER , MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER , MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER , MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_MCG_MISC_REGISTER , MSR_PENTIUM_4_PEBS_ENABLE_REGISTER , MSR_PENTIUM_4_PLATFORM_BRV_REGISTER , MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER , MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_THERM2_CTL_REGISTER , MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER , MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER , MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER , MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER , MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER , MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER , MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER , MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER , MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER , MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER , MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER , MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER , MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER , MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER , MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SEV_STATUS_REGISTER , MSR_SILVERMONT_BBL_CR_CTL3_REGISTER , MSR_SILVERMONT_EBL_CR_POWERON_REGISTER , MSR_SILVERMONT_FEATURE_CONFIG_REGISTER , MSR_SILVERMONT_FSB_FREQ_REGISTER , MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_LBR_SELECT_REGISTER , MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER , MSR_SILVERMONT_PEBS_ENABLE_REGISTER , MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SILVERMONT_PKG_POWER_INFO_REGISTER , MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER , MSR_SILVERMONT_PLATFORM_ID_REGISTER , MSR_SILVERMONT_PLATFORM_INFO_REGISTER , MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER , MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER , MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER , MSR_SILVERMONT_SMI_COUNT_REGISTER , MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER , MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER , MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER , MSR_SKYLAKE_IA32_MCG_CAP_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER , MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER , MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER , MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER , MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_PEBS_FRONTEND_REGISTER , MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER , MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER , MSR_SKYLAKE_PLATFORM_INFO_REGISTER , MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER , MSR_SKYLAKE_POWER_CTL_REGISTER , MSR_SKYLAKE_PPIN_CTL_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER , MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER , MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_SMM_MCA_CAP_REGISTER , MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER , MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER , MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER , MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER , MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER , MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER , MSR_XEON_5600_FEATURE_CONFIG_REGISTER , MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER , MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER , MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER , MSR_XEON_D_IA32_MCG_CAP_REGISTER , MSR_XEON_D_IA32_PQR_ASSOC_REGISTER , MSR_XEON_D_IA32_QM_EVTSEL_REGISTER , MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_D_PLATFORM_INFO_REGISTER , MSR_XEON_D_PPIN_CTL_REGISTER , MSR_XEON_D_RAPL_POWER_UNIT_REGISTER , MSR_XEON_D_SMM_MCA_CAP_REGISTER , MSR_XEON_D_TEMPERATURE_TARGET_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER , MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER , MSR_XEON_E7_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_FEATURE_CONFIG_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_LBR_SELECT_REGISTER , MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER , MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER , MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER , MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER , MSR_XEON_PHI_PLATFORM_INFO_REGISTER , MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER , MSR_XEON_PHI_PPIN_CTL_REGISTER , MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER , MSR_XEON_PHI_SMI_COUNT_REGISTER , MSR_XEON_PHI_SMM_MCA_CAP_REGISTER , MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER , MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER , RTIT_TOPA_TABLE_ENTRY
  • UMASK : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
  • UMIP : CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
  • Unavailable : MSR_IA32_QM_CTR_REGISTER
  • UnhaltedCoreCycles : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • UnhaltedReferenceCycles : CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
  • UOP : MSR_PENTIUM_4_PEBS_ENABLE_REGISTER
  • UpdateRevision : CPU_MICROCODE_HEADER
  • User : MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER , MSR_IA32_RTIT_CTL_REGISTER
  • UserEcc : MSR_P6_BBL_CR_CTL_REGISTER
  • UserModeMonitorAndMwait : MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
  • USR : MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER , MSR_HASWELL_IA32_PERFEVTSEL_REGISTER , MSR_IA32_PERFEVTSEL_REGISTER , MSR_P6_PERFEVTSEL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

  • All
  • Variables
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  • V : MSR_IA32_MTRR_PHYSMASK_REGISTER
  • Valid : MSR_CORE2_SMRR_PHYSMASK_REGISTER , MSR_GOLDMONT_PKGC3_IRTL_REGISTER , MSR_GOLDMONT_PKGC_IRTL1_REGISTER , MSR_GOLDMONT_PKGC_IRTL2_REGISTER , MSR_HASWELL_PKGC_IRTL1_REGISTER , MSR_HASWELL_PKGC_IRTL2_REGISTER , MSR_IA32_SMM_MONITOR_CTL_REGISTER , MSR_IA32_SMRR_PHYSMASK_REGISTER , MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER , MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
  • VCNT : MSR_IA32_MTRRCAP_REGISTER
  • Vector : LOCAL_APIC_ICR_LOW , LOCAL_APIC_LVT_LINT , LOCAL_APIC_LVT_TIMER , LOCAL_APIC_MSI_DATA
  • Version : LOCAL_APIC_VERSION
  • VirtualAddress : MSR_IA32_RTIT_ADDR_REGISTER
  • VirtualAddressHi : MSR_IA32_RTIT_ADDR_REGISTER
  • VLD : MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
  • VmcsAddressWidth : MSR_IA32_VMX_BASIC_REGISTER
  • VmcsPhysPointer : STM_VMCS_DATABASE_REQUEST
  • VmcsRevisonId : MSR_IA32_VMX_BASIC_REGISTER
  • VmcsSize : MSR_IA32_VMX_BASIC_REGISTER
  • VME : CPUID_AMD_EXTENDED_CPU_SIG_EDX , CPUID_VERSION_INFO_EDX
  • VmExitEferLma : IA32_VMX_MISC_REGISTER
  • VmInjectSupported : IA32_VMX_MISC_REGISTER
  • VmWriteSupported : IA32_VMX_MISC_REGISTER
  • VMX : CPUID_VERSION_INFO_ECX
  • VmxControls : MSR_IA32_VMX_BASIC_REGISTER
  • VmxTimerRatio : IA32_VMX_MISC_REGISTER
  • VRThermalDesignCurrentLog : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • VRThermalDesignCurrentStatus : MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
  • VRThermAlertLog : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
  • VRThermAlertStatus : MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER , MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER , MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER
  • VRThermDesignCurrentStatus : MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

  • All
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- w -

  • WaitForSipiActivityStateSupported : IA32_VMX_MISC_REGISTER
  • WakePMI : MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER , MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
  • Way : MSR_P6_BBL_CR_CTL_REGISTER
  • Ways : CPUID_CACHE_PARAMS_EBX
  • WayToL2 : MSR_P6_BBL_CR_CTL_REGISTER
  • WC : MSR_IA32_MTRRCAP_REGISTER
  • WDT : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • WindowCntSel : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
  • WindowSize : MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Data Fields - Variables

  • All
  • Variables
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- x -

  • x2APIC : CPUID_VERSION_INFO_ECX
  • x87 : CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
  • XCR0 : CPUID_EXTENDED_STATE_SUB_LEAF_ECX
  • XCR0_1 : CPUID_EXTENDED_STATE_SUB_LEAF_ECX
  • XD : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_CORE_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • XEOperation : MSR_CORE2_PERF_STATUS_REGISTER
  • XGETBV : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XOP : CPUID_AMD_EXTENDED_CPU_SIG_ECX
  • XSAVE : CPUID_VERSION_INFO_ECX
  • XSAVEC : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XSaveErPtr : CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
  • XSAVEOPT : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XSAVES : CPUID_EXTENDED_STATE_SUB_LEAF_EAX
  • XSS : CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
  • XStatePolicy : STM_SMM_STATE
  • xTPR_Message_Disable : MSR_ATOM_IA32_MISC_ENABLE_REGISTER , MSR_CORE2_IA32_MISC_ENABLE_REGISTER , MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER , MSR_IA32_MISC_ENABLE_REGISTER , MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER , MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER , MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER , MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER , MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
  • xTPR_Update_Control : CPUID_VERSION_INFO_ECX
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: File List

  • File List
  • Globals
File List
Here is a list of all documented files with brief descriptions:
[detail level 12345]
\ - UefiCpuPkg |
o + AmiCpuPeiPreMem |
| \ * AmiCpuPeiPreMem.c |
o + CpuDxe |
| o * CpuDxe.c |
| o * CpuDxe.h |
| o * CpuDxe.uni |
| o * CpuDxeExtra.uni |
| o * CpuGdt.c |
| o * CpuGdt.h |
| o * CpuMp.c |
| o * CpuMp.h |
| o * CpuPageTable.c |
| \ * CpuPageTable.h |
o + CpuFeatures |
| o * CpuFeaturesDxe.c |
| o * CpuFeaturesDxe.uni |
| o * CpuFeaturesDxeExtra.uni |
| o * CpuFeaturesPei.c |
| o * CpuFeaturesPei.uni |
| \ * CpuFeaturesPeiExtra.uni |
o + CpuIo2Dxe |
| o * CpuIo2Dxe.c |
| o * CpuIo2Dxe.h |
| o * CpuIo2Dxe.uni |
| \ * CpuIo2DxeExtra.uni |
o + CpuIo2Smm |
| o * CpuIo2Smm.c |
| o * CpuIo2Smm.h |
| o * CpuIo2Smm.uni |
| \ * CpuIo2SmmExtra.uni |
o + CpuIoPei |
| o * CpuIoPei.c |
| o * CpuIoPei.h |
| o * CpuIoPei.uni |
| \ * CpuIoPeiExtra.uni |
o + CpuMpPei |
| o * CpuBist.c |
| o * CpuMpPei.c |
| o * CpuMpPei.h |
| o * CpuMpPei.uni |
| o * CpuMpPeiExtra.uni |
| \ * CpuPaging.c |
o + CpuS3DataDxe |
| o * CpuS3Data.c |
| o * CpuS3DataDxe.uni |
| \ * CpuS3DataDxeExtra.uni |
o + Include |
| o + Guid |
| | o * CpuFeaturesInitDone.h |
| | o * CpuFeaturesSetDone.h |
| | \ * MsegSmram.h |
| o + Library |
| | o * LocalApicLib.h |
| | o * MpInitLib.h |
| | o * MtrrLib.h |
| | o * PlatformSecLib.h |
| | o * RegisterCpuFeaturesLib.h |
| | o * SmmCpuFeaturesLib.h |
| | o * SmmCpuPlatformHookLib.h |
| | \ * UefiCpuLib.h |
| o + Protocol |
| | o * SmmCpuService.h |
| | \ * SmMonitorInit.h |
| o + Register |
| | o + Amd |
| | | o * Cpuid.h |
| | | o * Fam17Msr.h |
| | | \ * Msr.h |
| | o + Msr |
| | | o * AtomMsr.h |
| | | o * BroadwellMsr.h |
| | | o * Core2Msr.h |
| | | o * CoreMsr.h |
| | | o * GoldmontMsr.h |
| | | o * GoldmontPlusMsr.h |
| | | o * HaswellEMsr.h |
| | | o * HaswellMsr.h |
| | | o * IvyBridgeMsr.h |
| | | o * NehalemMsr.h |
| | | o * P6Msr.h |
| | | o * Pentium4Msr.h |
| | | o * PentiumMMsr.h |
| | | o * PentiumMsr.h |
| | | o * SandyBridgeMsr.h |
| | | o * SilvermontMsr.h |
| | | o * SkylakeMsr.h |
| | | o * Xeon5600Msr.h |
| | | o * XeonDMsr.h |
| | | o * XeonE7Msr.h |
| | | \ * XeonPhiMsr.h |
| | o * ArchitecturalMsr.h |
| | o * Cpuid.h |
| | o * LocalApic.h |
| | o * Microcode.h |
| | o * Msr.h |
| | o * SmramSaveStateMap.h |
| | o * StmApi.h |
| | o * StmResourceDescriptor.h |
| | \ * StmStatusCode.h |
| o * AcpiCpuData.h |
| \ * CpuHotPlugData.h |
o + Library |
| o + BaseUefiCpuLib |
| | \ * BaseUefiCpuLib.uni |
| o + BaseXApicLib |
| | o * BaseXApicLib.c |
| | \ * BaseXApicLib.uni |
| o + BaseXApicX2ApicLib |
| | o * BaseXApicX2ApicLib.c |
| | \ * BaseXApicX2ApicLib.uni |
| o + CpuCommonFeaturesLib |
| | o * Aesni.c |
| | o * C1e.c |
| | o * ClockModulation.c |
| | o * CpuCommonFeatures.h |
| | o * CpuCommonFeaturesLib.c |
| | o * CpuCommonFeaturesLib.uni |
| | o * Eist.c |
| | o * ExecuteDisable.c |
| | o * FastStrings.c |
| | o * FeatureControl.c |
| | o * LimitCpuIdMaxval.c |
| | o * MachineCheck.c |
| | o * MonitorMwait.c |
| | o * PendingBreak.c |
| | o * Ppin.c |
| | o * ProcTrace.c |
| | \ * X2Apic.c |
| o + CpuExceptionHandlerLib |
| | o + Ia32 |
| | | o * ArchExceptionHandler.c |
| | | \ * ArchInterruptDefs.h |
| | o + X64 |
| | | o * ArchExceptionHandler.c |
| | | \ * ArchInterruptDefs.h |
| | o * CpuExceptionCommon.c |
| | o * CpuExceptionCommon.h |
| | o * DxeCpuExceptionHandlerLib.uni |
| | o * DxeException.c |
| | o * PeiCpuException.c |
| | o * PeiCpuExceptionHandlerLib.uni |
| | o * PeiDxeSmmCpuException.c |
| | o * SecPeiCpuException.c |
| | o * SecPeiCpuExceptionHandlerLib.uni |
| | o * SmmCpuExceptionHandlerLib.uni |
| | \ * SmmException.c |
| o + MpInitLib |
| | o * DxeMpInitLib.uni |
| | o * DxeMpLib.c |
| | o * Microcode.c |
| | o * MpLib.c |
| | o * MpLib.h |
| | o * PeiMpInitLib.uni |
| | \ * PeiMpLib.c |
| o + MtrrLib |
| | o * MtrrLib.c |
| | \ * MtrrLib.uni |
| o + PlatformSecLibNull |
| | o * PlatformSecLibNull.c |
| | \ * PlatformSecLibNull.uni |
| o + RegisterCpuFeaturesLib |
| | o * CpuFeaturesInitialize.c |
| | o * DxeRegisterCpuFeaturesLib.c |
| | o * PeiRegisterCpuFeaturesLib.c |
| | o * RegisterCpuFeatures.h |
| | o * RegisterCpuFeaturesLib.c |
| | \ * RegisterCpuFeaturesLib.uni |
| o + SecPeiDxeTimerLibUefiCpu |
| | o * SecPeiDxeTimerLibUefiCpu.uni |
| | \ * X86TimerLib.c |
| o + SmmCpuFeaturesLib |
| | o + Ia32 |
| | | \ * SmmStmSupport.c |
| | o + X64 |
| | | \ * SmmStmSupport.c |
| | o * SmmCpuFeaturesLib.c |
| | o * SmmCpuFeaturesLib.uni |
| | o * SmmCpuFeaturesLibNoStm.c |
| | o * SmmStm.c |
| | \ * SmmStm.h |
| \ + SmmCpuPlatformHookLibNull |
| o * SmmCpuPlatformHookLibNull.c |
| \ * SmmCpuPlatformHookLibNull.uni |
o + PiSmmCommunication |
| o * PiSmmCommunicationPei.c |
| o * PiSmmCommunicationPei.uni |
| o * PiSmmCommunicationPeiExtra.uni |
| o * PiSmmCommunicationPrivate.h |
| o * PiSmmCommunicationSmm.c |
| o * PiSmmCommunicationSmm.uni |
| \ * PiSmmCommunicationSmmExtra.uni |
o + PiSmmCpuDxeSmm |
| o + Ia32 |
| | o * PageTbl.c |
| | o * Semaphore.c |
| | o * SmmFuncsArch.c |
| | o * SmmProfileArch.c |
| | \ * SmmProfileArch.h |
| o + X64 |
| | o * PageTbl.c |
| | o * Semaphore.c |
| | o * SmmFuncsArch.c |
| | o * SmmProfileArch.c |
| | \ * SmmProfileArch.h |
| o * CpuS3.c |
| o * CpuService.c |
| o * CpuService.h |
| o * MpService.c |
| o * PiSmmCpuDxeSmm.c |
| o * PiSmmCpuDxeSmm.h |
| o * PiSmmCpuDxeSmm.uni |
| o * PiSmmCpuDxeSmmExtra.uni |
| o * SmmCpuMemoryManagement.c |
| o * SmmProfile.c |
| o * SmmProfile.h |
| o * SmmProfileInternal.h |
| o * SmramSaveState.c |
| \ * SyncTimer.c |
o + ResetVector |
| o + FixupVtf |
| | o * ResetVector.uni |
| | \ * ResetVectorExtra.uni |
| \ + Vtf0 |
| o + Bin |
| | o * ResetVector.uni |
| | \ * ResetVectorExtra.uni |
| o + Tools |
| | \ * FixupForRawSection.py | Apply fixup to VTF binary image for FFS Raw section
| o * Build.py | Automate the process of building the various reset vector types
| o * ResetVector.uni |
| \ * ResetVectorExtra.uni |
o + SecCore |
| o * FindPeiCore.c |
| o * SecBist.c |
| o * SecCore.uni |
| o * SecCoreExtra.uni |
| o * SecMain.c |
| \ * SecMain.h |
o + Universal |
| \ + Acpi |
| \ + S3Resume2Pei |
| o * S3Resume.c |
| o * S3Resume2Pei.uni |
| \ * S3Resume2PeiExtra.uni |
o * UefiCpuPkg.uni |
\ * UefiCpuPkgExtra.uni |
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg Directory Reference

  • UefiCpuPkg
UefiCpuPkg Directory Reference

Directories

directory | AmiCpuPeiPreMem
directory | CpuDxe
directory | CpuFeatures
directory | CpuIo2Dxe
directory | CpuIo2Smm
directory | CpuIoPei
directory | CpuMpPei
directory | CpuS3DataDxe
directory | Include
directory | Library
directory | PiSmmCommunication
directory | PiSmmCpuDxeSmm
directory | ResetVector
directory | SecCore
directory | UefiCpuSetup
directory | Universal

Files

file | CpuIo.sdl
file | doxygen_objdb_6440.tmp
file | UefiCpuPkg.chm
file | UefiCpuPkg.dec
file | UefiCpuPkg.sdl
file | UefiCpuPkg.uni
file | UefiCpuPkgExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/AmiCpuPeiPreMem Directory Reference

  • UefiCpuPkg
  • AmiCpuPeiPreMem
AmiCpuPeiPreMem Directory Reference

Files

file | AmiCpuPeiPreMem.c
file | AmiCpuPeiPreMem.inf
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/AmiCpuPeiPreMem/AmiCpuPeiPreMem.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • AmiCpuPeiPreMem
Functions
AmiCpuPeiPreMem.c File Reference

Functions

EFI_STATUS EFIAPI | FindMicrocodeInFv (IN VOID *Fv, OUT UINT64 *MicrocodePatchAddress, OUT UINT64 *MicrocodePatchRegionSize)
EFI_STATUS EFIAPI | FindMicrocode (OUT UINT64 *MicrocodePatchAddress, OUT UINT64 *MicrocodePatchRegionSize)
EFI_STATUS EFIAPI | AmiCpuPeiPreMemEntry (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

Detailed Description

Main CpuPeiEarlyInit Driver File.

Function Documentation

EFI_STATUS EFIAPI AmiCpuPeiPreMemEntry | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

CpuPei driver entry Before memory initialize

Parameters
FileHandle | Handle of the file being invoked.
PeiServices | Describes the list of possible PEI Services.
Return values
EFI_STATUS Return EFI status.
EFI_STATUS EFIAPI FindMicrocode | ( | OUT UINT64 * | MicrocodePatchAddress,
 |  | OUT UINT64 * | MicrocodePatchRegionSize
 | ) |  |

Find the microcode address.

Parameters
MicrocodePatchAddress | - If find, return microcode patch address
MicrocodePatchRegionSize | - If find, return microcode patch size
Return values
EFI_SUCCESS | - Found microcode.
EFI_NOT_FOUND | - Not found.
EFI_STATUS EFIAPI FindMicrocodeInFv | ( | IN VOID * | Fv,
 |  | OUT UINT64 * | MicrocodePatchAddress,
 |  | OUT UINT64 * | MicrocodePatchRegionSize
 | ) |  |

Find the microcode address in specific firmware volume.

Parameters
Fv | - Firmware Volume
MicrocodePatchAddress | - If find, return microcode patch address
MicrocodePatchRegionSize | - If find, return microcode patch size
Return values
EFI_SUCCESS | - Found microcode.
EFI_NOT_FOUND | - Not found.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe Directory Reference

  • UefiCpuPkg
  • CpuDxe
CpuDxe Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | CpuDxe.c
file | CpuDxe.h
file | CpuDxe.inf
file | CpuDxe.uni
file | CpuDxeExtra.uni
file | CpuGdt.c
file | CpuGdt.h
file | CpuMp.c
file | CpuMp.h
file | CpuPageTable.c
file | CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuDxe.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
Functions | Variables
CpuDxe.c File Reference

Functions

EFI_STATUS EFIAPI | CpuFlushCpuDataCache (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS Start, IN UINT64 Length, IN EFI_CPU_FLUSH_TYPE FlushType)
EFI_STATUS EFIAPI | CpuEnableInterrupt (IN EFI_CPU_ARCH_PROTOCOL *This)
EFI_STATUS EFIAPI | CpuDisableInterrupt (IN EFI_CPU_ARCH_PROTOCOL *This)
EFI_STATUS EFIAPI | CpuGetInterruptState (IN EFI_CPU_ARCH_PROTOCOL *This, OUT BOOLEAN *State)
EFI_STATUS EFIAPI | CpuInit (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_INIT_TYPE InitType)
EFI_STATUS EFIAPI | CpuRegisterInterruptHandler (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS EFIAPI | CpuGetTimerValue (IN EFI_CPU_ARCH_PROTOCOL *This, IN UINT32 TimerIndex, OUT UINT64 *TimerValue, OUT UINT64 *TimerPeriod OPTIONAL)
VOID EFIAPI | SetMtrrsFromBuffer (IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuSetMemoryAttributes (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
VOID InitializeMtrrMask (VOID)
UINT64 | GetMemorySpaceAttributeFromMtrrType (IN UINT8 MtrrAttributes)
EFI_STATUS | SearchGcdMemorySpaces (IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN UINTN NumberOfDescriptors, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, OUT UINTN *StartIndex, OUT UINTN *EndIndex)
EFI_STATUS | SetGcdMemorySpaceAttributes (IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR *MemorySpaceMap, IN UINTN NumberOfDescriptors, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
VOID RefreshMemoryAttributesFromMtrr (VOID)
BOOLEAN | IsPagingAndPageAddressExtensionsEnabled (VOID)
VOID RefreshGcdMemoryAttributes (VOID)
VOID InitInterruptDescriptorTable (VOID)
VOID EFIAPI | IdleLoopEventCallback (IN EFI_EVENT Event, IN VOID *Context)
EFI_STATUS | IntersectMemoryDescriptor (IN UINT64 Base, IN UINT64 Length, IN UINT64 Capabilities, IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor)
EFI_STATUS | AddMemoryMappedIoSpace (IN UINT64 Base, IN UINT64 Length, IN UINT64 Capabilities)
VOID | AddLocalApicMemorySpace (IN EFI_HANDLE ImageHandle)
EFI_STATUS EFIAPI | InitializeCpu (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)

Variables

BOOLEAN | InterruptState = FALSE
EFI_HANDLE | mCpuHandle = NULL
BOOLEAN | mIsFlushingGCD
BOOLEAN | mIsAllocatingPageTable = FALSE
UINT64 | mValidMtrrAddressMask
UINT64 | mValidMtrrBitsMask
UINT64 | mTimerPeriod = 0
FIXED_MTRR | mFixedMtrrTable []
EFI_CPU_ARCH_PROTOCOL | gCpu

Detailed Description

CPU DXE Module to produce CPU ARCH Protocol.

Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID AddLocalApicMemorySpace ( IN EFI_HANDLE ImageHandle )

Add and allocate CPU local APIC memory mapped space.

Parameters
[in] Image handle this driver.
EFI_STATUS AddMemoryMappedIoSpace | ( | IN UINT64 | Base,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Capabilities
 | ) |  |

Add MMIO space to GCD. The routine checks the GCD database and only adds those which are not added in the specified range to GCD.

Parameters
Base | Base address of the MMIO space.
Length | Length of the MMIO space.
Capabilities | Capabilities of the MMIO space.
Return values
EFI_SUCCES The MMIO space was added successfully.
EFI_STATUS EFIAPI CpuDisableInterrupt ( IN EFI_CPU_ARCH_PROTOCOL * This )

Disables CPU interrupts.

Parameters
This Protocol instance structure
Return values
EFI_SUCCESS | If interrupts were disabled in the CPU.
EFI_DEVICE_ERROR | If interrupts could not be disabled on the CPU.
EFI_STATUS EFIAPI CpuEnableInterrupt ( IN EFI_CPU_ARCH_PROTOCOL * This )

Enables CPU interrupts.

Parameters
This Protocol instance structure
Return values
EFI_SUCCESS | If interrupts were enabled in the CPU
EFI_DEVICE_ERROR | If interrupts could not be enabled on the CPU.
EFI_STATUS EFIAPI CpuFlushCpuDataCache | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | Start,
 |  | IN UINT64 | Length,
 |  | IN EFI_CPU_FLUSH_TYPE | FlushType
 | ) |  |

Flush CPU data cache. If the instruction cache is fully coherent with all DMA operations then function can just return EFI_SUCCESS.

Parameters
This | Protocol instance structure
Start | Physical address to start flushing from.
Length | Number of bytes to flush. Round up to chipset granularity.
FlushType | Specifies the type of flush operation to perform.
Return values
EFI_SUCCESS | If cache was flushed
EFI_UNSUPPORTED | If flush type is not supported.
EFI_DEVICE_ERROR | If requested range could not be flushed.
EFI_STATUS EFIAPI CpuGetInterruptState | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | OUT BOOLEAN * | State
 | ) |  |

Return the state of interrupts.

Parameters
This | Protocol instance structure
State | Pointer to the CPU's current interrupt state
Return values
EFI_SUCCESS | If interrupts were disabled in the CPU.
EFI_INVALID_PARAMETER | State is NULL.
EFI_STATUS EFIAPI CpuGetTimerValue | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN UINT32 | TimerIndex,
 |  | OUT UINT64 * | TimerValue,
 |  | OUT UINT64 *TimerPeriod | OPTIONAL
 | ) |  |

Returns a timer value from one of the CPU's internal timers. There is no inherent time interval between ticks but is a function of the CPU frequency.

Parameters
This | - Protocol instance structure.
TimerIndex | - Specifies which CPU timer is requested.
TimerValue | - Pointer to the returned timer value.
TimerPeriod | - A pointer to the amount of time that passes in femtoseconds (10-15) for each increment of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is returned. The amount of time that has passed between two calls to GetTimerValue() can be calculated with the formula (TimerValue2 - TimerValue1) * TimerPeriod. This parameter is optional and may be NULL.
Return values
EFI_SUCCESS | - If the CPU timer count was returned.
EFI_UNSUPPORTED | - If the CPU does not have any readable timers.
EFI_DEVICE_ERROR | - If an error occurred while reading the timer.
EFI_INVALID_PARAMETER | - TimerIndex is not valid or TimerValue is NULL.
EFI_STATUS EFIAPI CpuInit | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_CPU_INIT_TYPE | InitType
 | ) |  |

Generates an INIT to the CPU.

Parameters
This | Protocol instance structure
InitType | Type of CPU INIT to perform
Return values
EFI_SUCCESS | If CPU INIT occurred. This value should never be seen.
EFI_DEVICE_ERROR | If CPU INIT failed.
EFI_UNSUPPORTED | Requested type of CPU INIT not supported.
EFI_STATUS EFIAPI CpuRegisterInterruptHandler | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Registers a function to be called from the CPU interrupt handler.

Parameters
This | Protocol instance structure
InterruptType | Defines which interrupt to hook. IA-32 valid range is 0x00 through 0xFF
InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. A null pointer is an error condition.
Return values
EFI_SUCCESS | If handler installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported.
EFI_STATUS EFIAPI CpuSetMemoryAttributes | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.

This function modifies the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
This | The EFI_CPU_ARCH_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
UINT64 GetMemorySpaceAttributeFromMtrrType ( IN UINT8 MtrrAttributes )

Gets GCD Mem Space type from MTRR Type.

This function gets GCD Mem Space type from MTRR Type.

Parameters
MtrrAttributes MTRR memory type
Returns
GCD Mem Space type
VOID EFIAPI IdleLoopEventCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Callback function for idle events.

Parameters
Event | Event whose notification function is being invoked.
Context | The pointer to the notification function's context, which is implementation-dependent.
EFI_STATUS EFIAPI InitializeCpu | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Initialize the state information for the CPU Architectural Protocol.

Parameters
ImageHandle | Image handle this driver.
SystemTable | Pointer to the System Table.
Return values
EFI_SUCCESS | Thread can be successfully created
EFI_OUT_OF_RESOURCES | Cannot allocate protocol data structure
EFI_DEVICE_ERROR | Cannot create the thread
VOID InitializeMtrrMask ( VOID )

Initializes the valid bits mask and valid address mask for MTRRs.

This function initializes the valid bits mask and valid address mask for MTRRs.

VOID InitInterruptDescriptorTable ( VOID )

Initialize Interrupt Descriptor Table for interrupt handling.

EFI_STATUS IntersectMemoryDescriptor | ( | IN UINT64 | Base,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Capabilities,
 |  | IN CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR * | Descriptor
 | ) |  |

Ensure the compatibility of a memory space descriptor with the MMIO aperture.

The memory space descriptor can come from the GCD memory space map, or it can represent a gap between two neighboring memory space descriptors. In the latter case, the GcdMemoryType field is expected to be EfiGcdMemoryTypeNonExistent.

If the memory space descriptor already has type EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the required capabilities, then no action is taken – it is by definition compatible with the aperture.

Otherwise, the intersection of the memory space descriptor is calculated with the aperture. If the intersection is the empty set (no overlap), no action is taken; the memory space descriptor is compatible with the aperture.

Otherwise, the type of the descriptor is investigated again. If the type is EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with such a type), then an attempt is made to add the intersection as MMIO space to the GCD memory space map, with the specified capabilities. This ensures continuity for the aperture, and the descriptor is deemed compatible with the aperture.

Otherwise, the memory space descriptor is incompatible with the MMIO aperture.

Parameters
[in] | Base | Base address of the aperture.
[in] | Length | Length of the aperture.
[in] | Capabilities | Capabilities required by the aperture.
[in] | Descriptor | The descriptor to ensure compatibility with the aperture for.
Return values
EFI_SUCCESS | The descriptor is compatible. The GCD memory space map may have been updated, for continuity within the aperture.
EFI_INVALID_PARAMETER | The descriptor is incompatible.
Returns
Error codes from gDS->AddMemorySpace().
BOOLEAN IsPagingAndPageAddressExtensionsEnabled ( VOID )

Check if paging is enabled or not.

VOID RefreshGcdMemoryAttributes ( VOID )

Refreshes the GCD Memory Space attributes according to MTRRs and Paging.

This function refreshes the GCD Memory Space attributes according to MTRRs and page tables.

VOID RefreshMemoryAttributesFromMtrr ( VOID )

Refreshes the GCD Memory Space attributes according to MTRRs.

This function refreshes the GCD Memory Space attributes according to MTRRs.

EFI_STATUS SearchGcdMemorySpaces | ( | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR * | MemorySpaceMap,
 |  | IN UINTN | NumberOfDescriptors,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | OUT UINTN * | StartIndex,
 |  | OUT UINTN * | EndIndex
 | ) |  |

Searches memory descriptors covered by given memory range.

This function searches into the Gcd Memory Space for descriptors (from StartIndex to EndIndex) that contains the memory range specified by BaseAddress and Length.

Parameters
MemorySpaceMap | Gcd Memory Space Map as array.
NumberOfDescriptors | Number of descriptors in map.
BaseAddress | BaseAddress for the requested range.
Length | Length for the requested range.
StartIndex | Start index into the Gcd Memory Space Map.
EndIndex | End index into the Gcd Memory Space Map.
Return values
EFI_SUCCESS | Search successfully.
EFI_NOT_FOUND | The requested descriptors does not exist.
EFI_STATUS SetGcdMemorySpaceAttributes | ( | IN EFI_GCD_MEMORY_SPACE_DESCRIPTOR * | MemorySpaceMap,
 |  | IN UINTN | NumberOfDescriptors,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

Sets the attributes for a specified range in Gcd Memory Space Map.

This function sets the attributes for a specified range in Gcd Memory Space Map.

Parameters
MemorySpaceMap | Gcd Memory Space Map as array
NumberOfDescriptors | Number of descriptors in map
BaseAddress | BaseAddress for the range
Length | Length for the range
Attributes | Attributes to set
Return values
EFI_SUCCESS | Memory attributes set successfully
EFI_NOT_FOUND | The specified range does not exist in Gcd Memory Space
VOID EFIAPI SetMtrrsFromBuffer ( IN VOID * Buffer )

A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.

Parameters
[in] Buffer Pointer to an MTRR_SETTINGS object, to be passed to MtrrSetAllMtrrs().

Variable Documentation

EFI_CPU_ARCH_PROTOCOL gCpu
Initial value:
= {
CpuFlushCpuDataCache,
CpuEnableInterrupt,
CpuDisableInterrupt,
CpuGetInterruptState,
CpuInit,
CpuRegisterInterruptHandler,
CpuGetTimerValue,
CpuSetMemoryAttributes,
1,
4
}
CpuEnableInterrupt
EFI_STATUS EFIAPI CpuEnableInterrupt(IN EFI_CPU_ARCH_PROTOCOL *This)
Definition: CpuDxe.c:156
CpuSetMemoryAttributes
EFI_STATUS EFIAPI CpuSetMemoryAttributes(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
Definition: CpuDxe.c:384
CpuInit
EFI_STATUS EFIAPI CpuInit(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_INIT_TYPE InitType)
Definition: CpuDxe.c:229
CpuFlushCpuDataCache
EFI_STATUS EFIAPI CpuFlushCpuDataCache(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS Start, IN UINT64 Length, IN EFI_CPU_FLUSH_TYPE FlushType)
Definition: CpuDxe.c:126
CpuRegisterInterruptHandler
EFI_STATUS EFIAPI CpuRegisterInterruptHandler(IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
Definition: CpuDxe.c:260
CpuDisableInterrupt
EFI_STATUS EFIAPI CpuDisableInterrupt(IN EFI_CPU_ARCH_PROTOCOL *This)
Definition: CpuDxe.c:178
CpuGetInterruptState
EFI_STATUS EFIAPI CpuGetInterruptState(IN EFI_CPU_ARCH_PROTOCOL *This, OUT BOOLEAN *State)
Definition: CpuDxe.c:201
CpuGetTimerValue
EFI_STATUS EFIAPI CpuGetTimerValue(IN EFI_CPU_ARCH_PROTOCOL *This, IN UINT32 TimerIndex, OUT UINT64 *TimerValue, OUT UINT64 *TimerPeriod OPTIONAL)
Definition: CpuDxe.c:295
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuDxe.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
Functions | Variables
CpuDxe.h File Reference

Functions

EFI_STATUS EFIAPI | CpuFlushCpuDataCache (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS Start, IN UINT64 Length, IN EFI_CPU_FLUSH_TYPE FlushType)
EFI_STATUS EFIAPI | CpuEnableInterrupt (IN EFI_CPU_ARCH_PROTOCOL *This)
EFI_STATUS EFIAPI | CpuDisableInterrupt (IN EFI_CPU_ARCH_PROTOCOL *This)
EFI_STATUS EFIAPI | CpuGetInterruptState (IN EFI_CPU_ARCH_PROTOCOL *This, OUT BOOLEAN *State)
EFI_STATUS EFIAPI | CpuInit (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_CPU_INIT_TYPE InitType)
EFI_STATUS EFIAPI | CpuRegisterInterruptHandler (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS EFIAPI | CpuGetTimerValue (IN EFI_CPU_ARCH_PROTOCOL *This, IN UINT32 TimerIndex, OUT UINT64 *TimerValue, OUT UINT64 *TimerPeriod OPTIONAL)
EFI_STATUS EFIAPI | CpuSetMemoryAttributes (IN EFI_CPU_ARCH_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
VOID InitGlobalDescriptorTable (VOID)
VOID EFIAPI | SetCodeSelector (UINT16 Selector)
VOID EFIAPI | SetDataSelectors (UINT16 Selector)
VOID RefreshGcdMemoryAttributesFromPaging (VOID)
VOID EFIAPI | DebugExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID EFIAPI | PageFaultExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)

Variables

BOOLEAN | mIsAllocatingPageTable
UINTN | mNumberOfProcessors

Detailed Description

CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.

Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI CpuDisableInterrupt ( IN EFI_CPU_ARCH_PROTOCOL * This )

Disables CPU interrupts.

Parameters
This Protocol instance structure
Return values
EFI_SUCCESS | If interrupts were disabled in the CPU.
EFI_DEVICE_ERROR | If interrupts could not be disabled on the CPU.
EFI_STATUS EFIAPI CpuEnableInterrupt ( IN EFI_CPU_ARCH_PROTOCOL * This )

Enables CPU interrupts.

Parameters
This Protocol instance structure
Return values
EFI_SUCCESS | If interrupts were enabled in the CPU
EFI_DEVICE_ERROR | If interrupts could not be enabled on the CPU.
EFI_STATUS EFIAPI CpuFlushCpuDataCache | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | Start,
 |  | IN UINT64 | Length,
 |  | IN EFI_CPU_FLUSH_TYPE | FlushType
 | ) |  |

Flush CPU data cache. If the instruction cache is fully coherent with all DMA operations then function can just return EFI_SUCCESS.

Parameters
This | Protocol instance structure
Start | Physical address to start flushing from.
Length | Number of bytes to flush. Round up to chipset granularity.
FlushType | Specifies the type of flush operation to perform.
Return values
EFI_SUCCESS | If cache was flushed
EFI_UNSUPPORTED | If flush type is not supported.
EFI_DEVICE_ERROR | If requested range could not be flushed.
EFI_STATUS EFIAPI CpuGetInterruptState | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | OUT BOOLEAN * | State
 | ) |  |

Return the state of interrupts.

Parameters
This | Protocol instance structure
State | Pointer to the CPU's current interrupt state
Return values
EFI_SUCCESS | If interrupts were disabled in the CPU.
EFI_INVALID_PARAMETER | State is NULL.
EFI_STATUS EFIAPI CpuGetTimerValue | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN UINT32 | TimerIndex,
 |  | OUT UINT64 * | TimerValue,
 |  | OUT UINT64 *TimerPeriod | OPTIONAL
 | ) |  |

Returns a timer value from one of the CPU's internal timers. There is no inherent time interval between ticks but is a function of the CPU frequency.

Parameters
This | - Protocol instance structure.
TimerIndex | - Specifies which CPU timer is requested.
TimerValue | - Pointer to the returned timer value.
TimerPeriod | - A pointer to the amount of time that passes in femtoseconds (10-15) for each increment of TimerValue. If TimerValue does not increment at a predictable rate, then 0 is returned. The amount of time that has passed between two calls to GetTimerValue() can be calculated with the formula (TimerValue2 - TimerValue1) * TimerPeriod. This parameter is optional and may be NULL.
Return values
EFI_SUCCESS | - If the CPU timer count was returned.
EFI_UNSUPPORTED | - If the CPU does not have any readable timers.
EFI_DEVICE_ERROR | - If an error occurred while reading the timer.
EFI_INVALID_PARAMETER | - TimerIndex is not valid or TimerValue is NULL.
EFI_STATUS EFIAPI CpuInit | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_CPU_INIT_TYPE | InitType
 | ) |  |

Generates an INIT to the CPU.

Parameters
This | Protocol instance structure
InitType | Type of CPU INIT to perform
Return values
EFI_SUCCESS | If CPU INIT occurred. This value should never be seen.
EFI_DEVICE_ERROR | If CPU INIT failed.
EFI_UNSUPPORTED | Requested type of CPU INIT not supported.
EFI_STATUS EFIAPI CpuRegisterInterruptHandler | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Registers a function to be called from the CPU interrupt handler.

Parameters
This | Protocol instance structure
InterruptType | Defines which interrupt to hook. IA-32 valid range is 0x00 through 0xFF
InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. A null pointer is an error condition.
Return values
EFI_SUCCESS | If handler installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported.
EFI_STATUS EFIAPI CpuSetMemoryAttributes | ( | IN EFI_CPU_ARCH_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

Set memory cacheability attributes for given range of memeory.

Parameters
This | Protocol instance structure
BaseAddress | Specifies the start address of the memory range
Length | Specifies the length of the memory range
Attributes | The memory cacheability for the memory range
Return values
EFI_SUCCESS | If the cacheability of that memory range is set successfully
EFI_UNSUPPORTED | If the desired operation cannot be done
EFI_INVALID_PARAMETER | The input parameter is not correct, such as Length = 0

Implementation of SetMemoryAttributes() service of CPU Architecture Protocol.

This function modifies the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
This | The EFI_CPU_ARCH_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
VOID EFIAPI DebugExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Special handler for #DB exception, which will restore the page attributes (not-present). It should work with #PF handler which will set pages to 'present'.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.

SMM profile specific INT 1 (single-step) exception handler.

Parameters
InterruptType | Defines the type of interrupt or exception that occurred on the processor.This parameter is processor architecture specific.
SystemContext | A pointer to the processor context when the interrupt occurred on the processor.
VOID InitGlobalDescriptorTable ( VOID )

Initialize Global Descriptor Table.

VOID EFIAPI PageFaultExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Special handler for #PF exception, which will set the pages which caused #PF to be 'present'. The attribute of those pages should be restored in the subsequent #DB handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.

Initialize the Page Table lib.

VOID RefreshGcdMemoryAttributesFromPaging ( VOID )

Update GCD memory space attributes according to current page table setup.

VOID EFIAPI SetCodeSelector ( UINT16 Selector )

Sets the code selector (CS).

Parameters
Selector Value of code selector.
VOID EFIAPI SetDataSelectors ( UINT16 Selector )

Sets the data selector (DS).

Parameters
Selector Value of data selector.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuDxe.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
CpuDxe.uni File Reference

Detailed Description

CPU driver installs CPU Architecture Protocol and CPU MP Protocol.

CPU driver installs CPU Architecture Protocol and CPU MP Protocol.

Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuDxeExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
CpuDxeExtra.uni File Reference

Detailed Description

CpuDxe Localized Strings and Content

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuGdt.c File Reference

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  • CpuDxe
Functions | Variables
CpuGdt.c File Reference

Functions

VOID InitGlobalDescriptorTable (VOID)

Variables

STATIC GDT_ENTRIES GdtTemplate

Detailed Description

C based implemention of IA32 interrupt handling only requiring a minimal assembly interrupt entry point.

Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID InitGlobalDescriptorTable ( VOID )

Initialize Global Descriptor Table.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuGdt.h File Reference

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Data Structures | Typedefs
CpuGdt.h File Reference

Data Structures

struct | _GDT_ENTRY
struct | _GDT_ENTRIES

Typedefs

typedef struct _GDT_ENTRY | GDT_ENTRY
typedef struct _GDT_ENTRIES | GDT_ENTRIES

Detailed Description

C based implemention of IA32 interrupt handling only requiring a minimal assembly interrupt entry point.

Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuMp.c File Reference

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Functions | Variables
CpuMp.c File Reference

Functions

EFI_STATUS EFIAPI | GetNumberOfProcessors (IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
EFI_STATUS EFIAPI | GetProcessorInfo (IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
EFI_STATUS EFIAPI | StartupAllAPs (IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS EFIAPI | StartupThisAP (IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
EFI_STATUS EFIAPI | SwitchBSP (IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | EnableDisableAP (IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
EFI_STATUS EFIAPI | WhoAmI (IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *ProcessorNumber)
VOID CollectBistDataFromHob (VOID)
VOID EFIAPI | GetGdtr (IN OUT VOID *Buffer)
VOID EFIAPI | InitializeExceptionStackSwitchHandlers (IN OUT VOID *Buffer)
VOID InitializeMpExceptionStackSwitchHandlers (VOID)
VOID InitializeMpExceptionHandlers (VOID)
VOID InitializeMpSupport (VOID)

Variables

EFI_HANDLE | mMpServiceHandle = NULL
UINTN | mNumberOfProcessors = 1
EFI_MP_SERVICES_PROTOCOL | mMpServicesTemplate

Detailed Description

CPU DXE Module to produce CPU MP Protocol.

Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID CollectBistDataFromHob ( VOID )

Collects BIST data from HOB.

This function collects BIST data from HOB built from Sec Platform Information PPI or SEC Platform Information2 PPI.

EFI_STATUS EFIAPI EnableDisableAP | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the enable or disable AP operation cannot be completed prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
VOID EFIAPI GetGdtr ( IN OUT VOID * Buffer )

Get GDT register value.

This function is mainly for AP purpose because AP may have different GDT table than BSP.

Parameters
[in,out] Buffer The pointer to private data buffer.
EFI_STATUS EFIAPI GetNumberOfProcessors | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | OUT UINTN * | NumberOfProcessors,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. This service may only be called from the BSP.

This function is used to retrieve the following information:

  • The number of logical processors that are present in the system.
  • The number of enabled logical processors in the system at the instant this call is made.

Because MP Service Protocol provides services to enable and disable processors dynamically, the number of enabled logical processors may vary during the course of a boot session.

If this service is called from an AP, then EFI_DEVICE_ERROR is returned. If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors is returned in NumberOfProcessors, the number of currently enabled processor is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL.
EFI_INVALID_PARAMETER | NumberOfEnabledProcessors is NULL.
EFI_STATUS EFIAPI GetProcessorInfo | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made. This service may only be called from the BSP.

This service retrieves detailed MP-related information about any processor on the platform. Note the following:

  • The processor information may change during the course of a boot session.
  • The information presented here is entirely MP related.

Information regarding the number of caches and their sizes, frequency of operation, slot numbers is all considered platform-related information and is not provided by this service.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
VOID EFIAPI InitializeExceptionStackSwitchHandlers ( IN OUT VOID * Buffer )

Initializes CPU exceptions handlers for the sake of stack switch requirement.

This function is a wrapper of InitializeCpuExceptionHandlersEx. It's mainly for the sake of AP's init because of EFI_AP_PROCEDURE API requirement.

Parameters
[in,out] Buffer The pointer to private data buffer.
VOID InitializeMpExceptionHandlers ( VOID )

Initializes MP exceptions handlers for special features, such as Heap Guard and Stack Guard.

VOID InitializeMpExceptionStackSwitchHandlers ( VOID )

Initializes MP exceptions handlers for the sake of stack switch requirement.

This function will allocate required resources required to setup stack switch and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor.

VOID InitializeMpSupport ( VOID )

Initialize Multi-processor support.

EFI_STATUS EFIAPI StartupAllAPs | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs. APs can run either simultaneously or one at a time in sequence. This service supports both blocking and non-blocking requests. The non-blocking requests use EFI events so the BSP can detect when the APs have finished. This service may only be called from the BSP.

This function is used to dispatch all the enabled APs to the function specified by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.

If SingleThread is TRUE, all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. Otherwise, all the enabled APs execute the function specified by Procedure simultaneously.

If WaitEvent is NULL, execution is in blocking mode. The BSP waits until all APs finish or TimeoutInMicroseconds expires. Otherwise, execution is in non-blocking mode, and the BSP returns from this service without waiting for APs. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are always available for further calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If FailedCpuList is not NULL, its content points to the list of processor handle numbers in which Procedure was terminated.

Note: It is the responsibility of the consumer of the EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() to make sure that the nature of the code that is executed on the BSP and the dispatched APs is well controlled. The MP Services Protocol does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are limited to certain independent tasks and well-controlled exclusive code. EFI services and protocols may not be called by APs unless otherwise specified.

In blocking execution mode, BSP waits until all APs finish or TimeoutInMicroseconds expires.

In non-blocking execution mode, BSP is freed to return to the caller and then proceed to the next task without having to wait for APs. The following sequence needs to occur in a non-blocking execution mode:

  1. The caller that intends to use this MP Services Protocol in non-blocking mode creates WaitEvent by calling the EFI CreateEvent() service. The caller invokes EFI_MP_SERVICES_PROTOCOL.StartupAllAPs(). If the parameter WaitEvent is not NULL, then StartupAllAPs() executes in non-blocking mode. It requests the function specified by Procedure to be started on all the enabled APs, and releases the BSP to continue with other tasks.
  2. The caller can use the CheckEvent() and WaitForEvent() services to check the state of the WaitEvent created in step 1.
  3. When the APs complete their task or TimeoutInMicroSecondss expires, the MP Service signals WaitEvent by calling the EFI SignalEvent() function. If FailedCpuList is not NULL, its content is available when WaitEvent is signaled. If all APs returned from Procedure prior to the timeout, then FailedCpuList is set to NULL. If not all APs return from Procedure before the timeout, then FailedCpuList is filled in with the list of the failed APs. The buffer is allocated by MP Service Protocol using AllocatePool(). It is the caller's responsibility to free the buffer with FreePool() service.
  4. This invocation of SignalEvent() function informs the caller that invoked EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() that either all the APs completed the specified task or a timeout occurred. The contents of FailedCpuList can be examined to determine which APs did not complete the specified task prior to the timeout.
Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroseconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on all the enabled APs, and go on executing immediately. If all return from Procedure, or TimeoutInMicroseconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If NULL, this parameter is ignored. Otherwise, if all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs. The buffer is allocated by MP Service Protocol, and it's the caller's responsibility to free the buffer with FreePool() service. In blocking mode, it is ready for consumption when the call returns. In non-blocking mode, it is ready when WaitEvent is signaled. The list of failed CPU is terminated by END_OF_CPU_LIST.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI StartupThisAP | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function. The caller can request the BSP to either wait for the completion of the AP or just proceed with the next task by using the EFI event mechanism. See EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blocking execution support. This service may only be called from the BSP.

This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument specified by ProcedureArgument. If WaitEvent is NULL, execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode. BSP proceeds to the next task without waiting for the AP. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before the AP returns from Procedure, then execution of Procedure by the AP is terminated. The AP is available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_MP_SERVICES_PROTOCOL.StartupThisAP().

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | A pointer to the function to be run on the designated AP of the system. See type EFI_AP_PROCEDURE.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until this AP finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on this AP, and go on executing immediately. If this AP return from Procedure or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for this AP to finish this Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before this AP returns from Procedure, then Procedure on the AP is terminated. The AP is available for next function assigned by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure on the specified AP.
[out] | Finished | If NULL, this parameter is ignored. In blocking mode, this parameter is ignored. In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE. The caller can determine if the AP returned from Procedure by evaluating this value.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_SUCCESS | In non-blocking mode, the function has been dispatched to specified AP.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI SwitchBSP | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one left off. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_STATUS EFIAPI WhoAmI | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

This return the handle number for the calling processor. This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[out] | ProcessorNumber | Pointer to the handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

Variable Documentation

EFI_MP_SERVICES_PROTOCOL mMpServicesTemplate
Initial value:
= {
GetNumberOfProcessors,
GetProcessorInfo,
StartupAllAPs,
StartupThisAP,
SwitchBSP,
EnableDisableAP,
WhoAmI
}
StartupAllAPs
EFI_STATUS EFIAPI StartupAllAPs(IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
Definition: CpuMp.c:260
EnableDisableAP
EFI_STATUS EFIAPI EnableDisableAP(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
Definition: CpuMp.c:477
SwitchBSP
EFI_STATUS EFIAPI SwitchBSP(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
Definition: CpuMp.c:425
WhoAmI
EFI_STATUS EFIAPI WhoAmI(IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *ProcessorNumber)
Definition: CpuMp.c:513
GetProcessorInfo
EFI_STATUS EFIAPI GetProcessorInfo(IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Definition: CpuMp.c:113
GetNumberOfProcessors
EFI_STATUS EFIAPI GetNumberOfProcessors(IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
Definition: CpuMp.c:69
StartupThisAP
EFI_STATUS EFIAPI StartupThisAP(IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
Definition: CpuMp.c:368
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuMp.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
Functions
CpuMp.h File Reference

Functions

VOID InitializeMpSupport (VOID)
EFI_STATUS EFIAPI | GetNumberOfProcessors (IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
EFI_STATUS EFIAPI | GetProcessorInfo (IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
EFI_STATUS EFIAPI | StartupAllAPs (IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS EFIAPI | StartupThisAP (IN EFI_MP_SERVICES_PROTOCOL *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
EFI_STATUS EFIAPI | SwitchBSP (IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | EnableDisableAP (IN EFI_MP_SERVICES_PROTOCOL *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
EFI_STATUS EFIAPI | WhoAmI (IN EFI_MP_SERVICES_PROTOCOL *This, OUT UINTN *ProcessorNumber)

Detailed Description

CPU DXE MP support

Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI EnableDisableAP | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the enable or disable AP operation cannot be completed prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the enable or disable AP operation cannot be completed prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
EFI_STATUS EFIAPI GetNumberOfProcessors | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | OUT UINTN * | NumberOfProcessors,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. This service may only be called from the BSP.

This function is used to retrieve the following information:

  • The number of logical processors that are present in the system.
  • The number of enabled logical processors in the system at the instant this call is made.

Because MP Service Protocol provides services to enable and disable processors dynamically, the number of enabled logical processors may vary during the course of a boot session.

If this service is called from an AP, then EFI_DEVICE_ERROR is returned. If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors is returned in NumberOfProcessors, the number of currently enabled processor is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL.
EFI_INVALID_PARAMETER | NumberOfEnabledProcessors is NULL.
EFI_STATUS EFIAPI GetProcessorInfo | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made. This service may only be called from the BSP.

This service retrieves detailed MP-related information about any processor on the platform. Note the following:

  • The processor information may change during the course of a boot session.
  • The information presented here is entirely MP related.

Information regarding the number of caches and their sizes, frequency of operation, slot numbers is all considered platform-related information and is not provided by this service.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
VOID InitializeMpSupport ( VOID )

Initialize Multi-processor support.

EFI_STATUS EFIAPI StartupAllAPs | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs. APs can run either simultaneously or one at a time in sequence. This service supports both blocking and non-blocking requests. The non-blocking requests use EFI events so the BSP can detect when the APs have finished. This service may only be called from the BSP.

This function is used to dispatch all the enabled APs to the function specified by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.

If SingleThread is TRUE, all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. Otherwise, all the enabled APs execute the function specified by Procedure simultaneously.

If WaitEvent is NULL, execution is in blocking mode. The BSP waits until all APs finish or TimeoutInMicroseconds expires. Otherwise, execution is in non-blocking mode, and the BSP returns from this service without waiting for APs. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are always available for further calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If FailedCpuList is not NULL, its content points to the list of processor handle numbers in which Procedure was terminated.

Note: It is the responsibility of the consumer of the EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() to make sure that the nature of the code that is executed on the BSP and the dispatched APs is well controlled. The MP Services Protocol does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are limited to certain independent tasks and well-controlled exclusive code. EFI services and protocols may not be called by APs unless otherwise specified.

In blocking execution mode, BSP waits until all APs finish or TimeoutInMicroseconds expires.

In non-blocking execution mode, BSP is freed to return to the caller and then proceed to the next task without having to wait for APs. The following sequence needs to occur in a non-blocking execution mode:

  1. The caller that intends to use this MP Services Protocol in non-blocking mode creates WaitEvent by calling the EFI CreateEvent() service. The caller invokes EFI_MP_SERVICES_PROTOCOL.StartupAllAPs(). If the parameter WaitEvent is not NULL, then StartupAllAPs() executes in non-blocking mode. It requests the function specified by Procedure to be started on all the enabled APs, and releases the BSP to continue with other tasks.
  2. The caller can use the CheckEvent() and WaitForEvent() services to check the state of the WaitEvent created in step 1.
  3. When the APs complete their task or TimeoutInMicroSecondss expires, the MP Service signals WaitEvent by calling the EFI SignalEvent() function. If FailedCpuList is not NULL, its content is available when WaitEvent is signaled. If all APs returned from Procedure prior to the timeout, then FailedCpuList is set to NULL. If not all APs return from Procedure before the timeout, then FailedCpuList is filled in with the list of the failed APs. The buffer is allocated by MP Service Protocol using AllocatePool(). It is the caller's responsibility to free the buffer with FreePool() service.
  4. This invocation of SignalEvent() function informs the caller that invoked EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() that either all the APs completed the specified task or a timeout occurred. The contents of FailedCpuList can be examined to determine which APs did not complete the specified task prior to the timeout.
Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroseconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on all the enabled APs, and go on executing immediately. If all return from Procedure, or TimeoutInMicroseconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If NULL, this parameter is ignored. Otherwise, if all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs. The buffer is allocated by MP Service Protocol, and it's the caller's responsibility to free the buffer with FreePool() service. In blocking mode, it is ready for consumption when the call returns. In non-blocking mode, it is ready when WaitEvent is signaled. The list of failed CPU is terminated by END_OF_CPU_LIST.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI StartupThisAP | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function. The caller can request the BSP to either wait for the completion of the AP or just proceed with the next task by using the EFI event mechanism. See EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blocking execution support. This service may only be called from the BSP.

This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument specified by ProcedureArgument. If WaitEvent is NULL, execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode. BSP proceeds to the next task without waiting for the AP. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before the AP returns from Procedure, then execution of Procedure by the AP is terminated. The AP is available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_MP_SERVICES_PROTOCOL.StartupThisAP().

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroseconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on all the enabled APs, and go on executing immediately. If all return from Procedure or TimeoutInMicroseconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | Finished | If NULL, this parameter is ignored. In blocking mode, this parameter is ignored. In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE. The caller can determine if the AP returned from Procedure by evaluating this value.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_SUCCESS | In non-blocking mode, the function has been dispatched to specified AP.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.

This service lets the caller get one enabled AP to execute a caller-provided function. The caller can request the BSP to either wait for the completion of the AP or just proceed with the next task by using the EFI event mechanism. See EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() for more details on non-blocking execution support. This service may only be called from the BSP.

This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument specified by ProcedureArgument. If WaitEvent is NULL, execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires. Otherwise, execution is in non-blocking mode. BSP proceeds to the next task without waiting for the AP. If a non-blocking mode is requested after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled, then EFI_UNSUPPORTED must be returned.

If the timeout specified by TimeoutInMicroseconds expires before the AP returns from Procedure, then execution of Procedure by the AP is terminated. The AP is available for subsequent calls to EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() and EFI_MP_SERVICES_PROTOCOL.StartupThisAP().

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | Procedure | A pointer to the function to be run on the designated AP of the system. See type EFI_AP_PROCEDURE.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until this AP finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on this AP, and go on executing immediately. If this AP return from Procedure or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for this AP to finish this Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before this AP returns from Procedure, then Procedure on the AP is terminated. The AP is available for next function assigned by EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() or EFI_MP_SERVICES_PROTOCOL.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure on the specified AP.
[out] | Finished | If NULL, this parameter is ignored. In blocking mode, this parameter is ignored. In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE. The caller can determine if the AP returned from Procedure by evaluating this value.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_SUCCESS | In non-blocking mode, the function has been dispatched to specified AP.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI SwitchBSP | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one left off. This service may not be supported after the UEFI Event EFI_EVENT_GROUP_READY_TO_BOOT is signaled.

If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_STATUS EFIAPI WhoAmI | ( | IN EFI_MP_SERVICES_PROTOCOL * | This,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

This return the handle number for the calling processor. This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[out] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

This return the handle number for the calling processor. This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors(). This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters
[in] | This | A pointer to the EFI_MP_SERVICES_PROTOCOL instance.
[out] | ProcessorNumber | Pointer to the handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_MP_SERVICES_PROTOCOL.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuPageTable.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
Data Structures | Enumerations | Functions | Variables
CpuPageTable.c File Reference

Data Structures

struct PAGE_ATTRIBUTE_TABLE

Enumerations

enum PAGE_ATTRIBUTE {
PageNone, Page4K, Page2M, Page1G,
PageNone = 0, PageMin = 1, Page4K = PageMin, Page2M = 2,
Page1G = 3, Page512G = 4, PageMax = Page512G, PageNone,
Page4K, Page2M, Page1G
}
enum PAGE_ACTION { PageActionAssign, PageActionSet, PageActionClear }

Functions

BOOLEAN | IsInSmm (VOID)
VOID | GetCurrentPagingContext (IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext)
UINTN | PageAttributeToLength (IN PAGE_ATTRIBUTE PageAttribute)
UINTN | PageAttributeToMask (IN PAGE_ATTRIBUTE PageAttribute)
VOID * | GetPageTableEntry (IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, IN PHYSICAL_ADDRESS Address, OUT PAGE_ATTRIBUTE *PageAttribute)
UINT64 | GetAttributesFromPageEntry (IN UINT64 *PageEntry)
VOID | ConvertPageEntryAttribute (IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext, IN UINT64 *PageEntry, IN UINT64 Attributes, IN PAGE_ACTION PageAction, OUT BOOLEAN *IsModified)
PAGE_ATTRIBUTE | NeedSplitPage (IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 *PageEntry, IN PAGE_ATTRIBUTE PageAttribute)
RETURN_STATUS | SplitPage (IN UINT64 *PageEntry, IN PAGE_ATTRIBUTE PageAttribute, IN PAGE_ATTRIBUTE SplitAttribute, IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc)
BOOLEAN | IsReadOnlyPageWriteProtected (VOID)
VOID DisableReadOnlyPageWriteProtect (VOID)
VOID EnableReadOnlyPageWriteProtect (VOID)
RETURN_STATUS | ConvertMemoryPageAttributes (IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, IN PAGE_ACTION PageAction, IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL, OUT BOOLEAN *IsSplitted, OPTIONAL OUT BOOLEAN *IsModified OPTIONAL)
RETURN_STATUS EFIAPI | AssignMemoryPageAttributes (IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL)
BOOLEAN | IsExecuteDisableEnabled (VOID)
VOID RefreshGcdMemoryAttributesFromPaging (VOID)
BOOLEAN | InitializePageTablePool (IN UINTN PoolPages)
VOID *EFIAPI | AllocatePageTableMemory (IN UINTN Pages)
VOID EFIAPI | DebugExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID EFIAPI | PageFaultExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)

Variables

PAGE_ATTRIBUTE_TABLE | mPageAttributeTable []
PAGE_TABLE_POOL * | mPageTablePool = NULL
BOOLEAN | mPageTablePoolLock = FALSE
PAGE_TABLE_LIB_PAGING_CONTEXT | mPagingContext
EFI_SMM_BASE2_PROTOCOL * | mSmmBase2 = NULL
UINTN * | mPFEntryCount
UINT64 *(* | mLastPFEntryPointer )[MAX_PF_ENTRY_COUNT]

Detailed Description

Page table management support.

Copyright (c) 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* EFIAPI AllocatePageTableMemory ( IN UINTN Pages )

This API provides a way to allocate memory for page table.

This API can be called more than once to allocate memory for page tables.

Allocates the number of 4KB pages and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary.

If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.
RETURN_STATUS EFIAPI AssignMemoryPageAttributes | ( | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext | OPTIONAL,
 |  | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc | OPTIONAL
 | ) |  |

This function assigns the page attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Caller should make sure BaseAddress and Length is at page boundary.

Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.

Parameters
[in] | PagingContext | The paging context. NULL means get page table from current CPU context.
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
[in] | AllocatePagesFunc | If page split is needed, this function is used to allocate more pages. NULL mean page split is unsupported.
Return values
RETURN_SUCCESS | The attributes were cleared for the memory region.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_STATUS ConvertMemoryPageAttributes | ( | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext | OPTIONAL,
 |  | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | IN PAGE_ACTION | PageAction,
 |  | IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc | OPTIONAL,
 |  | OUT BOOLEAN * | IsSplitted,
 |  | OPTIONAL OUT BOOLEAN *IsModified | OPTIONAL
 | ) |  |

This function modifies the page attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Caller should make sure BaseAddress and Length is at page boundary.

Parameters
[in] | PagingContext | The paging context. NULL means get page table from current CPU context.
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to modify for the memory region.
[in] | PageAction | The page action.
[in] | AllocatePagesFunc | If page split is needed, this function is used to allocate more pages. NULL mean page split is unsupported.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
[out] | IsModified | TRUE means page table modified. FALSE means page table not modified.
Return values
RETURN_SUCCESS | The attributes were modified for the memory region.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
VOID ConvertPageEntryAttribute | ( | IN PAGE_TABLE_LIB_PAGING_CONTEXT * | PagingContext,
 |  | IN UINT64 * | PageEntry,
 |  | IN UINT64 | Attributes,
 |  | IN PAGE_ACTION | PageAction,
 |  | OUT BOOLEAN * | IsModified
 | ) |  |

Modify memory attributes of page entry.

Parameters
[in] | PagingContext | The paging context.
[in] | PageEntry | The page entry.
[in] | Attributes | The bit mask of attributes to modify for the memory region.
[in] | PageAction | The page action.
[out] | IsModified | TRUE means page table modified. FALSE means page table not modified.
VOID EFIAPI DebugExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Special handler for #DB exception, which will restore the page attributes (not-present). It should work with #PF handler which will set pages to 'present'.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
VOID DisableReadOnlyPageWriteProtect ( VOID )

Disable Write Protect on pages marked as read-only.

VOID EnableReadOnlyPageWriteProtect ( VOID )

Enable Write Protect on pages marked as read-only.

UINT64 GetAttributesFromPageEntry ( IN UINT64 * PageEntry )

Return memory attributes of page entry.

Parameters
[in] PageEntry The page entry.
Returns
Memory attributes of page entry.
VOID GetCurrentPagingContext ( IN OUT PAGE_TABLE_LIB_PAGING_CONTEXT * PagingContext )

Return current paging context.

Parameters
[in,out] PagingContext The paging context.
VOID* GetPageTableEntry | ( | IN PAGE_TABLE_LIB_PAGING_CONTEXT * | PagingContext,
 |  | IN PHYSICAL_ADDRESS | Address,
 |  | OUT PAGE_ATTRIBUTE * | PageAttribute
 | ) |  |

Return page table entry to match the address.

Parameters
[in] | PagingContext | The paging context.
[in] | Address | The address to be checked.
[out] | PageAttributes | The page attribute of the page entry.
Returns
The page entry.
BOOLEAN InitializePageTablePool ( IN UINTN PoolPages )

Initialize a buffer pool for page table use only.

To reduce the potential split operation on page table, the pages reserved for page table should be allocated in the times of PAGE_TABLE_POOL_UNIT_PAGES and at the boundary of PAGE_TABLE_POOL_ALIGNMENT. So the page pool is always initialized with number of pages greater than or equal to the given PoolPages.

Once the pages in the pool are used up, this method should be called again to reserve at least another PAGE_TABLE_POOL_UNIT_PAGES. Usually this won't happen often in practice.

Parameters
[in] PoolPages The least page number of the pool to be created.
Return values
TRUE | The pool is initialized successfully.
FALSE | The memory is out of resource.
BOOLEAN IsExecuteDisableEnabled ( VOID )

Check if Execute Disable feature is enabled or not.

BOOLEAN IsInSmm ( VOID )

Check if current execution environment is in SMM mode or not, via EFI_SMM_BASE2_PROTOCOL.

This is necessary because of the fact that MdePkg supports to free memory outside SMRAM. The library will call gBS->FreePool() or gBS->FreePages() and then SetMemorySpaceAttributes interface in turn to change memory paging attributes during free operation, if some memory related features are enabled (like Heap Guard).

This means that SetMemorySpaceAttributes() has chance to run in SMM mode. This will cause incorrect result because SMM mode always loads its own page tables, which are usually different from DXE. This function can be used to detect such situation and help to avoid further misoperations.

Return values
TRUE | In SMM mode.
FALSE | Not in SMM mode.
BOOLEAN IsReadOnlyPageWriteProtected ( VOID )

Check the WP status in CR0 register. This bit is used to lock or unlock write access to pages marked as read-only.

Return values
TRUE | Write protection is enabled.
FALSE | Write protection is disabled.
PAGE_ATTRIBUTE NeedSplitPage | ( | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 * | PageEntry,
 |  | IN PAGE_ATTRIBUTE | PageAttribute
 | ) |  |

This function returns if there is need to split page entry.

Parameters
[in] | BaseAddress | The base address to be checked.
[in] | Length | The length to be checked.
[in] | PageEntry | The page entry to be checked.
[in] | PageAttribute | The page attribute of the page entry.
Return values
SplitAttributes on if there is need to split page entry.
UINTN PageAttributeToLength ( IN PAGE_ATTRIBUTE PageAttribute )

Return length according to page attributes.

Parameters
[in] PageAttributes The page attribute of the page entry.
Returns
The length of page entry.
UINTN PageAttributeToMask ( IN PAGE_ATTRIBUTE PageAttribute )

Return address mask according to page attributes.

Parameters
[in] PageAttributes The page attribute of the page entry.
Returns
The address mask of page entry.
VOID EFIAPI PageFaultExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Special handler for #PF exception, which will set the pages which caused #PF to be 'present'. The attribute of those pages should be restored in the subsequent #DB handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.

Initialize the Page Table lib.

VOID RefreshGcdMemoryAttributesFromPaging ( VOID )

Update GCD memory space attributes according to current page table setup.

RETURN_STATUS SplitPage | ( | IN UINT64 * | PageEntry,
 |  | IN PAGE_ATTRIBUTE | PageAttribute,
 |  | IN PAGE_ATTRIBUTE | SplitAttribute,
 |  | IN PAGE_TABLE_LIB_ALLOCATE_PAGES | AllocatePagesFunc
 | ) |  |

This function splits one page entry to small page entries.

Parameters
[in] | PageEntry | The page entry to be splitted.
[in] | PageAttribute | The page attribute of the page entry.
[in] | SplitAttribute | How to split the page entry.
[in] | AllocatePagesFunc | If page split is needed, this function is used to allocate more pages.
Return values
RETURN_SUCCESS | The page entry is splitted.
RETURN_UNSUPPORTED | The page entry does not support to be splitted.
RETURN_OUT_OF_RESOURCES | No resource to split page entry.

Variable Documentation

PAGE_ATTRIBUTE_TABLE mPageAttributeTable[]
Initial value:
= {
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
}
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/CpuPageTable.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuDxe
Data Structures | Typedefs | Functions
CpuPageTable.h File Reference

Data Structures

struct | PAGE_TABLE_LIB_PAGING_CONTEXT_IA32
struct | PAGE_TABLE_LIB_PAGING_CONTEXT_X64
union | PAGE_TABLE_LIB_PAGING_CONTEXT_DATA
struct | PAGE_TABLE_LIB_PAGING_CONTEXT
struct | PAGE_TABLE_POOL

Typedefs

typedef VOID *EFIAPI * PAGE_TABLE_LIB_ALLOCATE_PAGES (IN UINTN Pages)

Functions

RETURN_STATUS EFIAPI | AssignMemoryPageAttributes (IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext OPTIONAL, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc OPTIONAL)
VOID InitializePageTableLib (VOID)
VOID *EFIAPI | AllocatePageTableMemory (IN UINTN Pages)

Detailed Description

Page table management header file.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Typedef Documentation

typedef VOID* EFIAPI* PAGE_TABLE_LIB_ALLOCATE_PAGES(IN UINTN Pages)

Allocates one or more 4KB pages for page table.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.

Function Documentation

VOID* EFIAPI AllocatePageTableMemory ( IN UINTN Pages )

This API provides a way to allocate memory for page table.

This API can be called more once to allocate memory for page tables.

Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.

This API provides a way to allocate memory for page table.

This API can be called more than once to allocate memory for page tables.

Allocates the number of 4KB pages and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary.

If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.

This API provides a way to allocate memory for page table.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.
RETURN_STATUS EFIAPI AssignMemoryPageAttributes | ( | IN PAGE_TABLE_LIB_PAGING_CONTEXT *PagingContext | OPTIONAL,
 |  | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | IN PAGE_TABLE_LIB_ALLOCATE_PAGES AllocatePagesFunc | OPTIONAL
 | ) |  |

This function assigns the page attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Caller should make sure BaseAddress and Length is at page boundary.

Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.

Parameters
PagingContext | The paging context. NULL means get page table from current CPU context.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to set for the memory region.
AllocatePagesFunc | If page split is needed, this function is used to allocate more pages. NULL mean page split is unsupported.
Return values
RETURN_SUCCESS | The attributes were cleared for the memory region.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.

This function assigns the page attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Caller should make sure BaseAddress and Length is at page boundary.

Caller need guarentee the TPL <= TPL_NOTIFY, if there is split page request.

Parameters
[in] | PagingContext | The paging context. NULL means get page table from current CPU context.
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
[in] | AllocatePagesFunc | If page split is needed, this function is used to allocate more pages. NULL mean page split is unsupported.
Return values
RETURN_SUCCESS | The attributes were cleared for the memory region.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
VOID InitializePageTableLib ( VOID )

Initialize the Page Table lib.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures Directory Reference

  • UefiCpuPkg
  • CpuFeatures
CpuFeatures Directory Reference

Files

file | CpuFeaturesDxe.c
file | CpuFeaturesDxe.inf
file | CpuFeaturesDxe.uni
file | CpuFeaturesDxeExtra.uni
file | CpuFeaturesPei.c
file | CpuFeaturesPei.inf
file | CpuFeaturesPei.uni
file | CpuFeaturesPeiExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuFeatures
Functions
CpuFeaturesDxe.c File Reference

Functions

VOID CpuFeaturesInitializeWorker (VOID)
VOID EFIAPI | SmmConfigurationEventNotify (IN EFI_EVENT Event, IN VOID *Context)
EFI_STATUS EFIAPI | CpuFeaturesDxeInitialize (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)

Detailed Description

CPU Features DXE driver to initialize CPU features.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI CpuFeaturesDxeInitialize | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

CPU Features driver entry point function.

If PcdCpuFeaturesInitAfterSmmRelocation is TRUE, it will register one SMM Configuration Protocol notify function to perform CPU features initialization. Otherwise, it will perform CPU features initialization directly.

Parameters
ImageHandle | Image handle this driver.
SystemTable | Pointer to the System Table.
Return values
EFI_SUCCESS CPU Features is initialized successfully.
VOID CpuFeaturesInitializeWorker ( VOID )

Worker function to perform CPU feature initialization.

VOID EFIAPI SmmConfigurationEventNotify | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Event notification that initialize CPU features when gEfiSmmConfigurationProtocol installs.

Parameters
[in] | Event | The Event that is being processed, not used.
[in] | Context | Event Context, not used.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures/CpuFeaturesDxe.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuFeatures
CpuFeaturesDxe.uni File Reference

Detailed Description

CPU Features DXE driver.

CPU Features DXE driver.

Copyright (c) 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures/CpuFeaturesDxeExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuFeatures
CpuFeaturesDxeExtra.uni File Reference

Detailed Description

CpuFeaturesDxe Localized Strings and Content

Copyright (c) 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures/CpuFeaturesPei.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuFeatures
Functions | Variables
CpuFeaturesPei.c File Reference

Functions

EFI_STATUS EFIAPI CpuFeaturesPeimInitialize (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

Variables

EFI_PEI_PPI_DESCRIPTOR mPeiCpuFeaturesInitDonePpiDesc

Detailed Description

CPU Features PEIM driver to initialize CPU features.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI CpuFeaturesPeimInitialize | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

CPU Features driver entry point function.

It will perform CPU features initialization, except for PcdCpuFeaturesInitOnS3Resume is FALSE on S3 resume.

Parameters
FileHandle | Handle of the file being invoked.
PeiServices | Describes the list of possible PEI Services.
Return values
EFI_SUCCESS CPU Features is initialized successfully.

Variable Documentation

EFI_PEI_PPI_DESCRIPTOR mPeiCpuFeaturesInitDonePpiDesc
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiCpuFeaturesInitDoneGuid,
NULL
}
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures/CpuFeaturesPei.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuFeatures
CpuFeaturesPei.uni File Reference

Detailed Description

CPU Features PEIM driver.

CPU Features PEIM driver.

Copyright (c) 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuFeatures/CpuFeaturesPeiExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuFeatures
CpuFeaturesPeiExtra.uni File Reference

Detailed Description

CpuFeaturesPei Localized Strings and Content

Copyright (c) 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Dxe Directory Reference

  • UefiCpuPkg
  • CpuIo2Dxe
CpuIo2Dxe Directory Reference

Files

file | CpuIo2Dxe.c
file | CpuIo2Dxe.h
file | CpuIo2Dxe.inf
file | CpuIo2Dxe.uni
file | CpuIo2DxeExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Dxe
Functions | Variables
CpuIo2Dxe.c File Reference

Functions

EFI_STATUS | CpuIoCheckParameter (IN BOOLEAN MmioOperation, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceRead (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceWrite (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceRead (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceWrite (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIo2Initialize (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)

Variables

EFI_HANDLE | mHandle = NULL
EFI_CPU_IO2_PROTOCOL | mCpuIo2
UINT8 | mInStride []
UINT8 | mOutStride []

Detailed Description

Produces the CPU I/O 2 Protocol.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Function Documentation

EFI_STATUS EFIAPI CpuIo2Initialize | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The user Entry Point for module CpuIo2Dxe. The user code starts with this function.

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS | The entry point is executed successfully.
other | Some error occurs when executing this entry point.
EFI_STATUS CpuIoCheckParameter | ( | IN BOOLEAN | MmioOperation,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Check parameters to a CPU I/O 2 Protocol service request.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

Parameters
[in] | MmioOperation | TRUE for an MMIO operation, FALSE for I/O Port operation.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The parameters for this request pass the checks.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuIoServiceRead | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuIoServiceWrite | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Write I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuMemoryServiceRead | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuMemoryServiceWrite | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Writes memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.

Variable Documentation

EFI_CPU_IO2_PROTOCOL mCpuIo2
Initial value:
= {
{
CpuMemoryServiceRead,
CpuMemoryServiceWrite
},
{
CpuIoServiceRead,
CpuIoServiceWrite
}
}
CpuMemoryServiceWrite
EFI_STATUS EFIAPI CpuMemoryServiceWrite(IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
Definition: CpuIo2Dxe.c:304
CpuIoServiceRead
EFI_STATUS EFIAPI CpuIoServiceRead(IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
Definition: CpuIo2Dxe.c:384
CpuMemoryServiceRead
EFI_STATUS EFIAPI CpuMemoryServiceRead(IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
Definition: CpuIo2Dxe.c:224
CpuIoServiceWrite
EFI_STATUS EFIAPI CpuIoServiceWrite(IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
Definition: CpuIo2Dxe.c:488
UINT8 mInStride[]
Initial value:
= {
1,
2,
4,
8,
0,
0,
0,
0,
1,
2,
4,
8
}
UINT8 mOutStride[]
Initial value:
= {
1,
2,
4,
8,
1,
2,
4,
8,
0,
0,
0,
0
}
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Dxe
Functions
CpuIo2Dxe.h File Reference

Functions

EFI_STATUS EFIAPI | CpuMemoryServiceRead (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceWrite (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceRead (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceWrite (IN EFI_CPU_IO2_PROTOCOL *This, IN EFI_CPU_IO_PROTOCOL_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)

Detailed Description

Internal include file for the CPU I/O 2 Protocol.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Function Documentation

EFI_STATUS EFIAPI CpuIoServiceRead | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuIoServiceWrite | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Write I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuMemoryServiceRead | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
EFI_STATUS EFIAPI CpuMemoryServiceWrite | ( | IN EFI_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_CPU_IO_PROTOCOL_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Writes memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for satisfying any alignment and I/O width restrictions that a PI System on a platform might require. For example on some platforms, width requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will be handled by the driver.

If Width is EfiCpuIoWidthUint8, EfiCpuIoWidthUint16, EfiCpuIoWidthUint32, or EfiCpuIoWidthUint64, then both Address and Buffer are incremented for each of the Count operations that is performed.

If Width is EfiCpuIoWidthFifoUint8, EfiCpuIoWidthFifoUint16, EfiCpuIoWidthFifoUint32, or EfiCpuIoWidthFifoUint64, then only Buffer is incremented for each of the Count operations that is performed. The read or write operation is performed Count times on the same Address.

If Width is EfiCpuIoWidthFillUint8, EfiCpuIoWidthFillUint16, EfiCpuIoWidthFillUint32, or EfiCpuIoWidthFillUint64, then only Address is incremented for each of the Count operations that is performed. The read or write operation is performed Count times from the first element of Buffer.

Parameters
[in] | This | A pointer to the EFI_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O or Memory operation.
[in] | Address | The base address of the I/O operation.
[in] | Count | The number of I/O operations to perform. The number of bytes moved is Width size * Count, starting at Address.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the PI system.
EFI_INVALID_PARAMETER | Width is invalid for this PI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The Buffer is not aligned for the given Width.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this PI system.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Dxe
CpuIo2Dxe.uni File Reference

Detailed Description

Produces the CPU I/O 2 Protocol by using the services of the I/O Library.

Produces the CPU I/O 2 Protocol by using the services of the I/O Library.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Dxe/CpuIo2DxeExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Dxe
CpuIo2DxeExtra.uni File Reference

Detailed Description

CpuIo2Dxe Localized Strings and Content

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Smm Directory Reference

  • UefiCpuPkg
  • CpuIo2Smm
CpuIo2Smm Directory Reference

Files

file | CpuIo2Smm.c
file | CpuIo2Smm.h
file | CpuIo2Smm.inf
file | CpuIo2Smm.uni
file | CpuIo2SmmExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Smm
Functions | Variables
CpuIo2Smm.c File Reference

Functions

EFI_STATUS | CpuIoCheckParameter (IN BOOLEAN MmioOperation, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceRead (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceWrite (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceRead (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceWrite (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | SmmCpuIo2Initialize (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)

Variables

EFI_HANDLE | mHandle = NULL
EFI_SMM_CPU_IO2_PROTOCOL | mSmmCpuIo2
UINT8 | mStride []

Detailed Description

Produces the SMM CPU I/O Protocol.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Function Documentation

EFI_STATUS CpuIoCheckParameter | ( | IN BOOLEAN | MmioOperation,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Check parameters to a SMM CPU I/O Protocol service request.

Parameters
[in] | MmioOperation | TRUE for an MMIO operation, FALSE for I/O Port operation.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_STATUS EFIAPI CpuIoServiceRead | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI CpuIoServiceWrite | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Write I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI CpuMemoryServiceRead | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI CpuMemoryServiceWrite | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Writes memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI SmmCpuIo2Initialize | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The module Entry Point SmmCpuIoProtocol driver

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS | The entry point is executed successfully.
Other | Some error occurs when executing this entry point.

Variable Documentation

EFI_SMM_CPU_IO2_PROTOCOL mSmmCpuIo2
Initial value:
= {
{
CpuMemoryServiceRead,
CpuMemoryServiceWrite
},
{
CpuIoServiceRead,
CpuIoServiceWrite
}
}
CpuIoServiceWrite
EFI_STATUS EFIAPI CpuIoServiceWrite(IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
Definition: CpuIo2Smm.c:334
CpuMemoryServiceRead
EFI_STATUS EFIAPI CpuMemoryServiceRead(IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
Definition: CpuIo2Smm.c:155
CpuMemoryServiceWrite
EFI_STATUS EFIAPI CpuMemoryServiceWrite(IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
Definition: CpuIo2Smm.c:215
CpuIoServiceRead
EFI_STATUS EFIAPI CpuIoServiceRead(IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
Definition: CpuIo2Smm.c:275
UINT8 mStride[]
Initial value:
= {
1,
2,
4,
8
}
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Smm
Functions
CpuIo2Smm.h File Reference

Functions

EFI_STATUS EFIAPI | CpuMemoryServiceRead (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceWrite (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceRead (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceWrite (IN CONST EFI_SMM_CPU_IO2_PROTOCOL *This, IN EFI_SMM_IO_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)

Detailed Description

Internal include file for the SMM CPU I/O Protocol.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Function Documentation

EFI_STATUS EFIAPI CpuIoServiceRead | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI CpuIoServiceWrite | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Write I/O registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI CpuMemoryServiceRead | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[out] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
EFI_STATUS EFIAPI CpuMemoryServiceWrite | ( | IN CONST EFI_SMM_CPU_IO2_PROTOCOL * | This,
 |  | IN EFI_SMM_IO_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Writes memory-mapped registers.

The I/O operations are carried out exactly as requested. The caller is responsible for any alignment and I/O width issues that the bus, device, platform, or type of I/O might require.

Parameters
[in] | This | The EFI_SMM_CPU_IO2_PROTOCOL instance.
[in] | Width | Signifies the width of the I/O operations.
[in] | Address | The base address of the I/O operations. The caller is responsible for aligning the Address if required.
[in] | Count | The number of I/O operations to perform.
[in] | Buffer | For read operations, the destination buffer to store the results. For write operations, the source buffer from which to write data.
Return values
EFI_SUCCESS | The data was read from or written to the device.
EFI_UNSUPPORTED | The Address is not valid for this system.
EFI_INVALID_PARAMETER | Width or Count, or both, were invalid.
EFI_OUT_OF_RESOURCES | The request could not be completed due to a lack of resources
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Smm
CpuIo2Smm.uni File Reference

Detailed Description

Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library.

Produces the SMM CPU I/O 2 Protocol by using the services of the I/O Library.

Copyright (c) 2009 - 2014, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIo2Smm/CpuIo2SmmExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIo2Smm
CpuIo2SmmExtra.uni File Reference

Detailed Description

CpuIo2Smm Localized Strings and Content

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIoPei Directory Reference

  • UefiCpuPkg
  • CpuIoPei
CpuIoPei Directory Reference

Files

file | CpuIoPei.c
file | CpuIoPei.h
file | CpuIoPei.inf
file | CpuIoPei.uni
file | CpuIoPeiExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIoPei/CpuIoPei.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIoPei
Functions | Variables
CpuIoPei.c File Reference

Functions

EFI_STATUS | CpuIoCheckParameter (IN BOOLEAN MmioOperation, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceRead (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceWrite (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceRead (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceWrite (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
UINT8 EFIAPI | CpuIoRead8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT16 EFIAPI | CpuIoRead16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT32 EFIAPI | CpuIoRead32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT64 EFIAPI | CpuIoRead64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
VOID EFIAPI | CpuIoWrite8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT8 Data)
VOID EFIAPI | CpuIoWrite16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT16 Data)
VOID EFIAPI | CpuIoWrite32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT32 Data)
VOID EFIAPI | CpuIoWrite64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT64 Data)
UINT8 EFIAPI | CpuMemRead8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT16 EFIAPI | CpuMemRead16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT32 EFIAPI | CpuMemRead32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT64 EFIAPI | CpuMemRead64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
VOID EFIAPI | CpuMemWrite8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT8 Data)
VOID EFIAPI | CpuMemWrite16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT16 Data)
VOID EFIAPI | CpuMemWrite32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT32 Data)
VOID EFIAPI | CpuMemWrite64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT64 Data)
EFI_STATUS EFIAPI | CpuIoInitialize (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

Variables

EFI_PEI_CPU_IO_PPI | gCpuIoPpi
EFI_PEI_PPI_DESCRIPTOR | gPpiList
UINT8 | mInStride []
UINT8 | mOutStride []

Detailed Description

Produces the CPU I/O PPI.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Function Documentation

EFI_STATUS CpuIoCheckParameter | ( | IN BOOLEAN | MmioOperation,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Check parameters to a CPU I/O PPI service request.

Parameters
[in] | MmioOperation | TRUE for an MMIO operation, FALSE for I/O Port operation.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[in] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The parameters for this request pass the checks.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
EFI_STATUS EFIAPI CpuIoInitialize | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

The Entry point of the CPU I/O PEIM

This function is the Entry point of the CPU I/O PEIM which installs CpuIoPpi.

Parameters
[in] | FileHandle | Pointer to image file handle.
[in] | PeiServices | Pointer to PEI Services Table
Return values
EFI_SUCCESS CPU I/O PPI successfully installed
UINT16 EFIAPI CpuIoRead16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

16-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 16-bit value returned from the I/O space.
UINT32 EFIAPI CpuIoRead32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

32-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 32-bit value returned from the I/O space.
UINT64 EFIAPI CpuIoRead64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

64-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 64-bit value returned from the I/O space.
UINT8 EFIAPI CpuIoRead8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

8-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
An 8-bit value returned from the I/O space.
EFI_STATUS EFIAPI CpuIoServiceRead | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads I/O registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[out] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
EFI_STATUS EFIAPI CpuIoServiceWrite | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Write I/O registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[in] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
VOID EFIAPI CpuIoWrite16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT16 | Data
 | ) |  |

16-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuIoWrite32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT32 | Data
 | ) |  |

32-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuIoWrite64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT64 | Data
 | ) |  |

64-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuIoWrite8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT8 | Data
 | ) |  |

8-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
EFI_STATUS EFIAPI CpuMemoryServiceRead | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads memory-mapped registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[out] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
EFI_STATUS EFIAPI CpuMemoryServiceWrite | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Writes memory-mapped registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[in] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
UINT16 EFIAPI CpuMemRead16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

16-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 16-bit value returned from the memory space.
UINT32 EFIAPI CpuMemRead32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

32-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 32-bit value returned from the memory space.
UINT64 EFIAPI CpuMemRead64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

64-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 64-bit value returned from the memory space.
UINT8 EFIAPI CpuMemRead8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

8-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
An 8-bit value returned from the memory space.
VOID EFIAPI CpuMemWrite16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT16 | Data
 | ) |  |

16-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuMemWrite32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT32 | Data
 | ) |  |

32-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuMemWrite64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT64 | Data
 | ) |  |

64-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuMemWrite8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT8 | Data
 | ) |  |

8-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.

Variable Documentation

EFI_PEI_CPU_IO_PPI gCpuIoPpi
Initial value:
= {
{
CpuMemoryServiceRead,
CpuMemoryServiceWrite
},
{
CpuIoServiceRead,
CpuIoServiceWrite
},
CpuIoRead8,
CpuIoRead16,
CpuIoRead32,
CpuIoRead64,
CpuIoWrite8,
CpuIoWrite16,
CpuIoWrite32,
CpuIoWrite64,
CpuMemRead8,
CpuMemRead16,
CpuMemRead32,
CpuMemRead64,
CpuMemWrite8,
CpuMemWrite16,
CpuMemWrite32,
CpuMemWrite64
}
CpuIoRead64
UINT64 EFIAPI CpuIoRead64(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:596
CpuMemRead16
UINT16 EFIAPI CpuMemRead16(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:728
CpuIoWrite64
VOID EFIAPI CpuIoWrite64(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT64 Data)
Definition: CpuIoPei.c:683
CpuIoRead16
UINT16 EFIAPI CpuIoRead16(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:552
CpuIoRead32
UINT32 EFIAPI CpuIoRead32(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:574
CpuIoRead8
UINT8 EFIAPI CpuIoRead8(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:530
CpuMemoryServiceRead
EFI_STATUS EFIAPI CpuMemoryServiceRead(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
Definition: CpuIoPei.c:199
CpuMemWrite64
VOID EFIAPI CpuMemWrite64(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT64 Data)
Definition: CpuIoPei.c:859
CpuMemWrite32
VOID EFIAPI CpuMemWrite32(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT32 Data)
Definition: CpuIoPei.c:837
CpuIoServiceWrite
EFI_STATUS EFIAPI CpuIoServiceWrite(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
Definition: CpuIoPei.c:441
CpuMemWrite8
VOID EFIAPI CpuMemWrite8(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT8 Data)
Definition: CpuIoPei.c:793
CpuIoServiceRead
EFI_STATUS EFIAPI CpuIoServiceRead(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
Definition: CpuIoPei.c:347
CpuMemWrite16
VOID EFIAPI CpuMemWrite16(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT16 Data)
Definition: CpuIoPei.c:815
CpuMemoryServiceWrite
EFI_STATUS EFIAPI CpuMemoryServiceWrite(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
Definition: CpuIoPei.c:273
CpuMemRead64
UINT64 EFIAPI CpuMemRead64(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:772
CpuIoWrite8
VOID EFIAPI CpuIoWrite8(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT8 Data)
Definition: CpuIoPei.c:617
CpuIoWrite16
VOID EFIAPI CpuIoWrite16(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT16 Data)
Definition: CpuIoPei.c:639
CpuMemRead8
UINT8 EFIAPI CpuMemRead8(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:706
CpuMemRead32
UINT32 EFIAPI CpuMemRead32(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
Definition: CpuIoPei.c:750
CpuIoWrite32
VOID EFIAPI CpuIoWrite32(IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT32 Data)
Definition: CpuIoPei.c:661
EFI_PEI_PPI_DESCRIPTOR gPpiList
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiCpuIoPpiInstalledGuid,
NULL
}
UINT8 mInStride[]
Initial value:
= {
1,
2,
4,
8,
0,
0,
0,
0,
1,
2,
4,
8
}
UINT8 mOutStride[]
Initial value:
= {
1,
2,
4,
8,
1,
2,
4,
8,
0,
0,
0,
0
}
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIoPei/CpuIoPei.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIoPei
Functions
CpuIoPei.h File Reference

Functions

EFI_STATUS EFIAPI | CpuMemoryServiceRead (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuMemoryServiceWrite (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceRead (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, OUT VOID *Buffer)
EFI_STATUS EFIAPI | CpuIoServiceWrite (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN EFI_PEI_CPU_IO_PPI_WIDTH Width, IN UINT64 Address, IN UINTN Count, IN VOID *Buffer)
UINT8 EFIAPI | CpuIoRead8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT16 EFIAPI | CpuIoRead16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT32 EFIAPI | CpuIoRead32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT64 EFIAPI | CpuIoRead64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
VOID EFIAPI | CpuIoWrite8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT8 Data)
VOID EFIAPI | CpuIoWrite16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT16 Data)
VOID EFIAPI | CpuIoWrite32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT32 Data)
VOID EFIAPI | CpuIoWrite64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT64 Data)
UINT8 EFIAPI | CpuMemRead8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT16 EFIAPI | CpuMemRead16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT32 EFIAPI | CpuMemRead32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
UINT64 EFIAPI | CpuMemRead64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address)
VOID EFIAPI | CpuMemWrite8 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT8 Data)
VOID EFIAPI | CpuMemWrite16 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT16 Data)
VOID EFIAPI | CpuMemWrite32 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT32 Data)
VOID EFIAPI | CpuMemWrite64 (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_PEI_CPU_IO_PPI *This, IN UINT64 Address, IN UINT64 Data)

Detailed Description

Internal include file for the CPU I/O PPI.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

Function Documentation

UINT16 EFIAPI CpuIoRead16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

16-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 16-bit value returned from the I/O space.
UINT32 EFIAPI CpuIoRead32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

32-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 32-bit value returned from the I/O space.
UINT64 EFIAPI CpuIoRead64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

64-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 64-bit value returned from the I/O space.
UINT8 EFIAPI CpuIoRead8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

8-bit I/O read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
An 8-bit value returned from the I/O space.
EFI_STATUS EFIAPI CpuIoServiceRead | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads I/O registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[out] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
EFI_STATUS EFIAPI CpuIoServiceWrite | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Write I/O registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[in] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
VOID EFIAPI CpuIoWrite16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT16 | Data
 | ) |  |

16-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuIoWrite32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT32 | Data
 | ) |  |

32-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuIoWrite64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT64 | Data
 | ) |  |

64-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuIoWrite8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT8 | Data
 | ) |  |

8-bit I/O write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
EFI_STATUS EFIAPI CpuMemoryServiceRead | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | OUT VOID * | Buffer
 | ) |  |

Reads memory-mapped registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[out] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
EFI_STATUS EFIAPI CpuMemoryServiceWrite | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN EFI_PEI_CPU_IO_PPI_WIDTH | Width,
 |  | IN UINT64 | Address,
 |  | IN UINTN | Count,
 |  | IN VOID * | Buffer
 | ) |  |

Writes memory-mapped registers.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Width | The width of the access. Enumerated in bytes.
[in] | Address | The physical address of the access.
[in] | Count | The number of accesses to perform.
[in] | Buffer | A pointer to the buffer of data.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_INVALID_PARAMETER | Width is invalid for this EFI system.
EFI_INVALID_PARAMETER | Buffer is NULL.
EFI_UNSUPPORTED | The address range specified by Address, Width, and Count is not valid for this EFI system.
UINT16 EFIAPI CpuMemRead16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

16-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 16-bit value returned from the memory space.
UINT32 EFIAPI CpuMemRead32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

32-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 32-bit value returned from the memory space.
UINT64 EFIAPI CpuMemRead64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

64-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
A 64-bit value returned from the memory space.
UINT8 EFIAPI CpuMemRead8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address
 | ) |  |

8-bit memory read operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
Returns
An 8-bit value returned from the memory space.
VOID EFIAPI CpuMemWrite16 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT16 | Data
 | ) |  |

16-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuMemWrite32 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT32 | Data
 | ) |  |

32-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuMemWrite64 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT64 | Data
 | ) |  |

64-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
VOID EFIAPI CpuMemWrite8 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_PEI_CPU_IO_PPI * | This,
 |  | IN UINT64 | Address,
 |  | IN UINT8 | Data
 | ) |  |

8-bit memory write operations.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to local data for the interface.
[in] | Address | The physical address of the access.
[in] | Data | The data to write.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIoPei/CpuIoPei.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIoPei
CpuIoPei.uni File Reference

Detailed Description

Produces the CPU I/O PPI by using the services of the I/O Library.

Produces the CPU I/O PPI by using the services of the I/O Library.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuIoPei/CpuIoPeiExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuIoPei
CpuIoPeiExtra.uni File Reference

Detailed Description

CpuIoPei Localized Strings and Content

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.

SPDX-License-Identifier: BSD-2-Clause-Patent

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei Directory Reference

  • UefiCpuPkg
  • CpuMpPei
CpuMpPei Directory Reference

Files

file | CpuBist.c
file | CpuMpPei.c
file | CpuMpPei.h
file | CpuMpPei.inf
file | CpuMpPei.uni
file | CpuMpPeiExtra.uni
file | CpuPaging.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei/CpuBist.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuMpPei
Functions | Variables
CpuBist.c File Reference

Functions

EFI_STATUS EFIAPI | SecPlatformInformation2 (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2)
EFI_STATUS | GetBistInfoFromPpi (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_GUID *Guid, OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, OUT VOID **BistInformationData, OUT UINT64 *BistInformationSize OPTIONAL)
VOID | CollectBistDataFromPpi (IN CONST EFI_PEI_SERVICES **PeiServices)

Variables

EFI_SEC_PLATFORM_INFORMATION2_PPI | mSecPlatformInformation2Ppi
EFI_PEI_PPI_DESCRIPTOR | mPeiSecPlatformInformation2Ppi

Detailed Description

Update and publish processors' BIST information.

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID CollectBistDataFromPpi ( IN CONST EFI_PEI_SERVICES ** PeiServices )

Collects BIST data from PPI.

This function collects BIST data from Sec Platform Information2 PPI or SEC Platform Information PPI.

Parameters
PeiServices Pointer to PEI Services Table
EFI_STATUS GetBistInfoFromPpi | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_GUID * | Guid,
 |  | OUT EFI_PEI_PPI_DESCRIPTOR ** | PpiDescriptor,
 |  | OUT VOID ** | BistInformationData,
 |  | OUT UINT64 *BistInformationSize | OPTIONAL
 | ) |  |

Worker function to get CPUs' BIST by calling SecPlatformInformationPpi or SecPlatformInformation2Ppi.

Parameters
PeiServices | Pointer to PEI Services Table
Guid | PPI Guid
PpiDescriptor | Return a pointer to instance of the EFI_PEI_PPI_DESCRIPTOR
BistInformationData | Pointer to BIST information data
BistInformationSize | Return the size in bytes of BIST information
Return values
EFI_SUCCESS | Retrieve of the BIST data successfully
EFI_NOT_FOUND | No sec platform information(2) ppi export
EFI_DEVICE_ERROR | Failed to get CPU Information
EFI_STATUS EFIAPI SecPlatformInformation2 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 * | PlatformInformationRecord2
 | ) |  |

Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.

Parameters
PeiServices | The pointer to the PEI Services Table.
StructureSize | The pointer to the variable describing size of the input buffer.
PlatformInformationRecord2 | The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small. The current buffer size needed to hold the record is returned in StructureSize.

Variable Documentation

EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2Ppi
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiSecPlatformInformation2PpiGuid,
&mSecPlatformInformation2Ppi
}
EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2Ppi
Initial value:
= {
SecPlatformInformation2
}
SecPlatformInformation2
EFI_STATUS EFIAPI SecPlatformInformation2(IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2)
Definition: CpuBist.c:41
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei/CpuMpPei.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuMpPei
Functions | Variables
CpuMpPei.c File Reference

Functions

EFI_STATUS EFIAPI | PeiGetNumberOfProcessors (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
EFI_STATUS EFIAPI | PeiGetProcessorInfo (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
EFI_STATUS EFIAPI | PeiStartupAllAPs (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
EFI_STATUS EFIAPI | PeiStartupThisAP (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
EFI_STATUS EFIAPI | PeiSwitchBSP (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | PeiEnableDisableAP (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
EFI_STATUS EFIAPI | PeiWhoAmI (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
VOID EFIAPI | GetGdtr (IN OUT VOID *Buffer)
VOID EFIAPI | InitializeExceptionStackSwitchHandlers (IN OUT VOID *Buffer)
VOID InitializeMpExceptionStackSwitchHandlers (VOID)
EFI_STATUS | InitializeCpuMpWorker (IN CONST EFI_PEI_SERVICES **PeiServices)
EFI_STATUS EFIAPI | CpuMpPeimInit (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

Variables

EFI_PEI_MP_SERVICES_PPI | mMpServicesPpi
EFI_PEI_PPI_DESCRIPTOR | mPeiCpuMpPpiDesc

Detailed Description

CPU PEI Module installs CPU Multiple Processor PPI.

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI CpuMpPeimInit | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

The Entry point of the MP CPU PEIM.

This function will wakeup APs and collect CPU AP count and install the Mp Service Ppi.

Parameters
FileHandle | Handle of the file being invoked.
PeiServices | Describes the list of possible PEI Services.
Return values
EFI_SUCCESS MpServicePpi is installed successfully.
VOID EFIAPI GetGdtr ( IN OUT VOID * Buffer )

Get GDT register value.

This function is mainly for AP purpose because AP may have different GDT table than BSP.

Parameters
[in,out] Buffer The pointer to private data buffer.
EFI_STATUS InitializeCpuMpWorker ( IN CONST EFI_PEI_SERVICES ** PeiServices )

Initializes MP and exceptions handlers.

Parameters
PeiServices The pointer to the PEI Services Table.
Return values
EFI_SUCCESS | MP was successfully initialized.
others | Error occurred in MP initialization.
VOID EFIAPI InitializeExceptionStackSwitchHandlers ( IN OUT VOID * Buffer )

Initializes CPU exceptions handlers for the sake of stack switch requirement.

This function is a wrapper of InitializeCpuExceptionHandlersEx. It's mainly for the sake of AP's init because of EFI_AP_PROCEDURE API requirement.

Parameters
[in,out] Buffer The pointer to private data buffer.
VOID InitializeMpExceptionStackSwitchHandlers ( VOID )

Initializes MP exceptions handlers for the sake of stack switch requirement.

This function will allocate required resources required to setup stack switch and pass them through CPU_EXCEPTION_INIT_DATA to each logic processor.

EFI_STATUS EFIAPI PeiEnableDisableAP | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system.

If the enable or disable AP operation cannot be completed prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
EFI_STATUS EFIAPI PeiGetNumberOfProcessors | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | OUT UINTN * | NumberOfProcessors,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. This service may only be called from the BSP.

This function is used to retrieve the following information:

  • The number of logical processors that are present in the system.
  • The number of enabled logical processors in the system at the instant this call is made.

Because MP Service Ppi provides services to enable and disable processors dynamically, the number of enabled logical processors may vary during the course of a boot session.

If this service is called from an AP, then EFI_DEVICE_ERROR is returned. If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors is returned in NumberOfProcessors, the number of currently enabled processor is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL. NumberOfEnabledProcessors is NULL.
EFI_STATUS EFIAPI PeiGetProcessorInfo | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made. This service may only be called from the BSP.

This service retrieves detailed MP-related information about any processor on the platform. Note the following:

  • The processor information may change during the course of a boot session.
  • The information presented here is entirely MP related.

Information regarding the number of caches and their sizes, frequency of operation, slot numbers is all considered platform-related information and is not provided by this service.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[in] | ProcessorNumber | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | ProcessorInfoBuffer | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
EFI_STATUS EFIAPI PeiStartupAllAPs | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN UINTN | TimeoutInMicroSeconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs. APs can run either simultaneously or one at a time in sequence. This service supports both blocking requests only. This service may only be called from the BSP.

This function is used to dispatch all the enabled APs to the function specified by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.

If SingleThread is TRUE, all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. Otherwise, all the enabled APs execute the function specified by Procedure simultaneously.

If the timeout specified by TimeoutInMicroSeconds expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are always available for further calls to EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() and EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If FailedCpuList is not NULL, its content points to the list of processor handle numbers in which Procedure was terminated.

Note: It is the responsibility of the consumer of the EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() to make sure that the nature of the code that is executed on the BSP and the dispatched APs is well controlled. The MP Services Ppi does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are limited to certain independent tasks and well-controlled exclusive code. PEI services and Ppis may not be called by APs unless otherwise specified.

In blocking execution mode, BSP waits until all APs finish or TimeoutInMicroSeconds expires.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | TimeoutInMicroSeconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI PeiStartupThisAP | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function. The caller can request the BSP to wait for the completion of the AP. This service may only be called from the BSP.

This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument specified by ProcedureArgument. The execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires.

If the timeout specified by TimeoutInMicroseconds expires before the AP returns from Procedure, then execution of Procedure by the AP is terminated. The AP is available for subsequent calls to EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() and EFI_PEI_MP_SERVICES_PPI.StartupThisAP().

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI PeiSwitchBSP | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one left off.

If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_STATUS EFIAPI PeiWhoAmI | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

This return the handle number for the calling processor. This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[out] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

Variable Documentation

EFI_PEI_MP_SERVICES_PPI mMpServicesPpi
Initial value:
= {
PeiGetNumberOfProcessors,
PeiGetProcessorInfo,
PeiStartupAllAPs,
PeiStartupThisAP,
PeiSwitchBSP,
PeiEnableDisableAP,
PeiWhoAmI,
}
PeiStartupThisAP
EFI_STATUS EFIAPI PeiStartupThisAP(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
Definition: CpuMpPei.c:261
PeiSwitchBSP
EFI_STATUS EFIAPI PeiSwitchBSP(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
Definition: CpuMpPei.c:316
PeiEnableDisableAP
EFI_STATUS EFIAPI PeiEnableDisableAP(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
Definition: CpuMpPei.c:367
PeiStartupAllAPs
EFI_STATUS EFIAPI PeiStartupAllAPs(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
Definition: CpuMpPei.c:194
PeiGetNumberOfProcessors
EFI_STATUS EFIAPI PeiGetNumberOfProcessors(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
Definition: CpuMpPei.c:74
PeiWhoAmI
EFI_STATUS EFIAPI PeiWhoAmI(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
Definition: CpuMpPei.c:404
PeiGetProcessorInfo
EFI_STATUS EFIAPI PeiGetProcessorInfo(IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Definition: CpuMpPei.c:119
EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiMpServicesPpiGuid,
&mMpServicesPpi
}
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei/CpuMpPei.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuMpPei
Functions | Variables
CpuMpPei.h File Reference

Functions

EFI_STATUS EFIAPI | PeiGetNumberOfProcessors (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *NumberOfProcessors, OUT UINTN *NumberOfEnabledProcessors)
EFI_STATUS EFIAPI | PeiGetProcessorInfo (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
EFI_STATUS EFIAPI | PeiStartupAllAPs (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN UINTN TimeoutInMicroSeconds, IN VOID *ProcedureArgument OPTIONAL)
EFI_STATUS EFIAPI | PeiStartupThisAP (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL)
EFI_STATUS EFIAPI | PeiSwitchBSP (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | PeiEnableDisableAP (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
EFI_STATUS EFIAPI | PeiWhoAmI (IN CONST EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_MP_SERVICES_PPI *This, OUT UINTN *ProcessorNumber)
VOID | CollectBistDataFromPpi (IN CONST EFI_PEI_SERVICES **PeiServices)
EFI_STATUS EFIAPI | SecPlatformInformation2 (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2)
EFI_STATUS | InitializeCpuMpWorker (IN CONST EFI_PEI_SERVICES **PeiServices)
EFI_STATUS EFIAPI | MemoryDiscoveredPpiNotifyCallback (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)

Variables

EFI_PEI_PPI_DESCRIPTOR | mPeiCpuMpPpiDesc
EFI_PEI_NOTIFY_DESCRIPTOR | mPostMemNotifyList []

Detailed Description

Definitions to install Multiple Processor PPI.

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID CollectBistDataFromPpi ( IN CONST EFI_PEI_SERVICES ** PeiServices )

Collects BIST data from PPI.

This function collects BIST data from Sec Platform Information2 PPI or SEC Platform Information PPI.

Parameters
PeiServices Pointer to PEI Services Table
EFI_STATUS InitializeCpuMpWorker ( IN CONST EFI_PEI_SERVICES ** PeiServices )

Initializes MP and exceptions handlers.

Parameters
PeiServices The pointer to the PEI Services Table.
Return values
EFI_SUCCESS | MP was successfully initialized.
others | Error occurred in MP initialization.
EFI_STATUS EFIAPI MemoryDiscoveredPpiNotifyCallback | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Enabl/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.

Doing this in the memory-discovered callback is to make sure the Stack Guard feature to cover as most PEI code as possible.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | The notification structure this PEIM registered on install.
[in] | Ppi | The memory discovered PPI. Not used.
Return values
EFI_SUCCESS | The function completed successfully.
others | There's error in MP initialization.
EFI_STATUS EFIAPI PeiEnableDisableAP | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

This service allows the caller enable or disable an AP from this point onward. The caller can optionally specify the health status of the AP by Health. If an AP is being disabled, then the state of the disabled AP is implementation dependent. If an AP is enabled, then the implementation must guarantee that a complete initialization sequence is performed on the AP, so the AP is in a state that is compatible with an MP operating system.

If the enable or disable AP operation cannot be completed prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_PEI_MP_SERVICES_PPI.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
EFI_STATUS EFIAPI PeiGetNumberOfProcessors | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | OUT UINTN * | NumberOfProcessors,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

This service retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. This service may only be called from the BSP.

This function is used to retrieve the following information:

  • The number of logical processors that are present in the system.
  • The number of enabled logical processors in the system at the instant this call is made.

Because MP Service Ppi provides services to enable and disable processors dynamically, the number of enabled logical processors may vary during the course of a boot session.

If this service is called from an AP, then EFI_DEVICE_ERROR is returned. If NumberOfProcessors or NumberOfEnabledProcessors is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the total number of processors is returned in NumberOfProcessors, the number of currently enabled processor is returned in NumberOfEnabledProcessors, and EFI_SUCCESS is returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL. NumberOfEnabledProcessors is NULL.
EFI_STATUS EFIAPI PeiGetProcessorInfo | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made. This service may only be called from the BSP.

This service retrieves detailed MP-related information about any processor on the platform. Note the following:

  • The processor information may change during the course of a boot session.
  • The information presented here is entirely MP related.

Information regarding the number of caches and their sizes, frequency of operation, slot numbers is all considered platform-related information and is not provided by this service.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | Pointer to this instance of the PPI.
[in] | ProcessorNumber | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | ProcessorInfoBuffer | Number of processors in the system that are enabled.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
EFI_STATUS EFIAPI PeiStartupAllAPs | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN UINTN | TimeoutInMicroSeconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs. APs can run either simultaneously or one at a time in sequence. This service supports both blocking requests only. This service may only be called from the BSP.

This function is used to dispatch all the enabled APs to the function specified by Procedure. If any enabled AP is busy, then EFI_NOT_READY is returned immediately and Procedure is not started on any AP.

If SingleThread is TRUE, all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. Otherwise, all the enabled APs execute the function specified by Procedure simultaneously.

If the timeout specified by TimeoutInMicroSeconds expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are always available for further calls to EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() and EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If FailedCpuList is not NULL, its content points to the list of processor handle numbers in which Procedure was terminated.

Note: It is the responsibility of the consumer of the EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() to make sure that the nature of the code that is executed on the BSP and the dispatched APs is well controlled. The MP Services Ppi does not guarantee that the Procedure function is MP-safe. Hence, the tasks that can be run in parallel are limited to certain independent tasks and well-controlled exclusive code. PEI services and Ppis may not be called by APs unless otherwise specified.

In blocking execution mode, BSP waits until all APs finish or TimeoutInMicroSeconds expires.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | TimeoutInMicroSeconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI PeiStartupThisAP | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function. The caller can request the BSP to wait for the completion of the AP. This service may only be called from the BSP.

This function is used to dispatch one enabled AP to the function specified by Procedure passing in the argument specified by ProcedureArgument. The execution is in blocking mode. The BSP waits until the AP finishes or TimeoutInMicroSecondss expires.

If the timeout specified by TimeoutInMicroseconds expires before the AP returns from Procedure, then execution of Procedure by the AP is terminated. The AP is available for subsequent calls to EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() and EFI_PEI_MP_SERVICES_PPI.StartupThisAP().

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, for blocking mode only. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by EFI_PEI_MP_SERVICES_PPI.StartupAllAPs() or EFI_PEI_MP_SERVICES_PPI.StartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI PeiSwitchBSP | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one left off.

If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_STATUS EFIAPI PeiWhoAmI | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_MP_SERVICES_PPI * | This,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

This return the handle number for the calling processor. This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved with EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors(). This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters
[in] | PeiServices | An indirect pointer to the PEI Services Table published by the PEI Foundation.
[in] | This | A pointer to the EFI_PEI_MP_SERVICES_PPI instance.
[out] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by EFI_PEI_MP_SERVICES_PPI.GetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.
EFI_STATUS EFIAPI SecPlatformInformation2 | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 * | PlatformInformationRecord2
 | ) |  |

Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.

Parameters
PeiServices | The pointer to the PEI Services Table.
StructureSize | The pointer to the variable describing size of the input buffer.
PlatformInformationRecord2 | The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small. The current buffer size needed to hold the record is returned in StructureSize.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei/CpuMpPei.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuMpPei
CpuMpPei.uni File Reference

Detailed Description

CPU driver installs CPU PI Multi-processor PPI.

CPU driver installs CPU PI Multi-processor PPI.

Copyright (c) 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei/CpuMpPeiExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuMpPei
CpuMpPeiExtra.uni File Reference

Detailed Description

CpuMpPei Localized Strings and Content

Copyright (c) 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuMpPei/CpuPaging.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuMpPei
Data Structures | Enumerations | Functions | Variables
CpuPaging.c File Reference

Data Structures

struct PAGE_ATTRIBUTE_TABLE

Enumerations

enum PAGE_ATTRIBUTE {
PageNone, Page4K, Page2M, Page1G,
PageNone = 0, PageMin = 1, Page4K = PageMin, Page2M = 2,
Page1G = 3, Page512G = 4, PageMax = Page512G, PageNone,
Page4K, Page2M, Page1G
}

Functions

BOOLEAN | IsIa32PaeSupported (VOID)
VOID * | AllocatePageTableMemory (IN UINTN Pages)
UINTN | GetPhysicalAddressWidth (VOID)
PAGE_ATTRIBUTE | GetPageTableTopLevelType (VOID)
VOID * | GetPageTableEntry (IN PHYSICAL_ADDRESS Address, OUT PAGE_ATTRIBUTE *PageAttribute)
RETURN_STATUS | SplitPage (IN UINT64 *PageEntry, IN PAGE_ATTRIBUTE PageAttribute, IN PAGE_ATTRIBUTE SplitAttribute, IN BOOLEAN Recursively)
RETURN_STATUS EFIAPI | ConvertMemoryPageAttributes (IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
PAGE_ATTRIBUTE | GetMaxMemoryPage (IN PAGE_ATTRIBUTE TopLevelType)
UINTN | CreatePageTable (VOID)
VOID EnablePaging (VOID)
VOID EFIAPI | GetStackBase (IN OUT VOID *Buffer)
VOID SetupStackGuardPage (VOID)
EFI_STATUS EFIAPI | MemoryDiscoveredPpiNotifyCallback (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)

Variables

PAGE_ATTRIBUTE_TABLE | mPageAttributeTable []
EFI_PEI_NOTIFY_DESCRIPTOR | mPostMemNotifyList []

Detailed Description

Basic paging support for the CPU to enable Stack Guard.

Copyright (c) 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* AllocatePageTableMemory ( IN UINTN Pages )

This API provides a way to allocate memory for page table.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.
RETURN_STATUS EFIAPI ConvertMemoryPageAttributes | ( | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function modifies the page attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Caller should make sure BaseAddress and Length is at page boundary.

Parameters
[in] | BaseAddress | Start address of a memory region.
[in] | Length | Size in bytes of the memory region.
[in] | Attributes | Bit mask of attributes to modify.
Return values
RETURN_SUCCESS | The attributes were modified for the memory region.
RETURN_INVALID_PARAMETER | Length is zero; or, Attributes specified an illegal combination of attributes that cannot be set together; or Addressis not 4KB aligned.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes.
RETURN_UNSUPPORTED | Cannot modify the attributes of given memory.
UINTN CreatePageTable ( VOID )

Create PML4 or PAE page table.

Returns
The address of page table.
VOID EnablePaging ( VOID )

Setup page tables and make them work.

PAGE_ATTRIBUTE GetMaxMemoryPage ( IN PAGE_ATTRIBUTE TopLevelType )

Get maximum size of page memory supported by current processor.

Parameters
[in] TopLevelType The type of top level page entry.
Return values
Page1G | If processor supports 1G page and PML4.
Page2M | For all other situations.
VOID* GetPageTableEntry | ( | IN PHYSICAL_ADDRESS | Address,
 |  | OUT PAGE_ATTRIBUTE * | PageAttribute
 | ) |  |

Return page table entry matching the address.

Parameters
[in] | Address | The address to be checked.
[out] | PageAttributes | The page attribute of the page entry.
Returns
The page entry.
PAGE_ATTRIBUTE GetPageTableTopLevelType ( VOID )

Get the type of top level page table.

Return values
Page512G | PML4 paging.
Page1G | PAE paing.
UINTN GetPhysicalAddressWidth ( VOID )

Get the address width supported by current processor.

Return values
32 | If processor is in 32-bit mode.
36-48 | If processor is in 64-bit mode.
VOID EFIAPI GetStackBase ( IN OUT VOID * Buffer )

Get the base address of current AP's stack.

This function is called in AP's context and assumes that whole calling stacks (till this function) consumed by AP's wakeup procedure will not exceed 4KB.

PcdCpuApStackSize must be configured with value taking the Guard page into account.

Parameters
[in,out] Buffer The pointer to private data buffer.
BOOLEAN IsIa32PaeSupported ( VOID )

The function will check if IA32 PAE is supported.

Return values
TRUE | IA32 PAE is supported.
FALSE | IA32 PAE is not supported.
EFI_STATUS EFIAPI MemoryDiscoveredPpiNotifyCallback | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Enabl/setup stack guard for each processor if PcdCpuStackGuard is set to TRUE.

Doing this in the memory-discovered callback is to make sure the Stack Guard feature to cover as most PEI code as possible.

Parameters
[in] | PeiServices | General purpose services available to every PEIM.
[in] | NotifyDescriptor | The notification structure this PEIM registered on install.
[in] | Ppi | The memory discovered PPI. Not used.
Return values
EFI_SUCCESS | The function completed successfully.
others | There's error in MP initialization.
VOID SetupStackGuardPage ( VOID )

Setup stack Guard page at the stack base of each processor. BSP and APs have different way to get stack base address.

RETURN_STATUS SplitPage | ( | IN UINT64 * | PageEntry,
 |  | IN PAGE_ATTRIBUTE | PageAttribute,
 |  | IN PAGE_ATTRIBUTE | SplitAttribute,
 |  | IN BOOLEAN | Recursively
 | ) |  |

This function splits one page entry to smaller page entries.

Parameters
[in] | PageEntry | The page entry to be splitted.
[in] | PageAttribute | The page attribute of the page entry.
[in] | SplitAttribute | How to split the page entry.
[in] | Recursively | Do the split recursively or not.
Return values
RETURN_SUCCESS | The page entry is splitted.
RETURN_INVALID_PARAMETER | If target page attribute is invalid
RETURN_OUT_OF_RESOURCES | No resource to split page entry.

Variable Documentation

PAGE_ATTRIBUTE_TABLE mPageAttributeTable[]
Initial value:
= {
{PageNone, 0, 0, 0, 0},
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64, 12, 9},
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64, 21, 9},
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64, 30, 9},
{Page512G, SIZE_512GB, PAGING_512G_ADDRESS_MASK_64, 39, 9},
}
EFI_PEI_NOTIFY_DESCRIPTOR mPostMemNotifyList[]
Initial value:
= {
{
(EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiMemoryDiscoveredPpiGuid,
MemoryDiscoveredPpiNotifyCallback
}
}
MemoryDiscoveredPpiNotifyCallback
EFI_STATUS EFIAPI MemoryDiscoveredPpiNotifyCallback(IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Definition: CpuPaging.c:605
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuS3DataDxe Directory Reference

  • UefiCpuPkg
  • CpuS3DataDxe
CpuS3DataDxe Directory Reference

Files

file | CpuS3Data.c
file | CpuS3DataDxe.inf
file | CpuS3DataDxe.uni
file | CpuS3DataDxeExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c File Reference

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  • CpuS3DataDxe
Data Structures | Functions
CpuS3Data.c File Reference

Data Structures

struct ACPI_CPU_DATA_EX

Functions

VOID * | AllocateAcpiNvsMemory (IN UINTN Size)
VOID * | AllocateZeroPages (IN UINTN Size)
VOID EFIAPI | CpuS3DataOnEndOfDxe (IN EFI_EVENT Event, OUT VOID *Context)
EFI_STATUS EFIAPI | CpuS3DataInitialize (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)

Detailed Description

ACPI CPU Data initialization module

This module initializes the ACPI_CPU_DATA structure and registers the address of this structure in the PcdCpuS3DataAddress PCD. This is a generic/simple version of this module. It does not provide a machine check handler or CPU register initialization tables for ACPI S3 resume. It also only supports the number of CPUs reported by the MP Services Protocol, so this module does not support hot plug CPUs. This module can be copied into a CPU specific package and customized if these additional features are required.

Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2015, Red Hat, Inc.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* AllocateAcpiNvsMemory ( IN UINTN Size )

Allocate EfiACPIMemoryNVS memory.

Parameters
[in] Size Size of memory to allocate.
Returns
Allocated address for output.
VOID* AllocateZeroPages ( IN UINTN Size )

Allocate memory and clean it with zero.

Parameters
[in] Size Size of memory to allocate.
Returns
Allocated address for output.
EFI_STATUS EFIAPI CpuS3DataInitialize | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The entry function of the CpuS3Data driver.

Allocate and initialize all fields of the ACPI_CPU_DATA structure except the MTRR settings. Register an event notification on gEfiEndOfDxeEventGroupGuid to capture the ACPI_CPU_DATA MTRR settings. The PcdCpuS3DataAddress is set to the address that ACPI_CPU_DATA is allocated at.

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS | The entry point is executed successfully.
EFI_UNSUPPORTED | Do not support ACPI S3.
other | Some error occurs when executing this entry point.
VOID EFIAPI CpuS3DataOnEndOfDxe | ( | IN EFI_EVENT | Event,
 |  | OUT VOID * | Context
 | ) |  |

Callback function executed when the EndOfDxe event group is signaled.

We delay allocating StartupVector and saving the MTRR settings until BDS signals EndOfDxe.

Parameters
[in] | Event | Event whose notification function is being invoked.
[out] | Context | Pointer to the MTRR_SETTINGS buffer to fill in.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.uni File Reference

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  • UefiCpuPkg
  • CpuS3DataDxe
Variables
CpuS3DataDxe.uni File Reference

Variables

ACPI CPU Data initialization
module This module initializes
the ACPI_CPU_DATA structure
and registers the address of
this structure in the
PcdCpuS3DataAddress PCD This
is a generic simple version of
this module It does not
provide a machine check
handler or CPU register
initialization tables for ACPI
S3 resume It also only
supports the number of CPUs
reported by the MP Services 		Protocol

Detailed Description

ACPI CPU Data initialization module

This module initializes the ACPI_CPU_DATA structure and registers the address of this structure in the PcdCpuS3DataAddress PCD. This is a generic/simple version of this module. It does not provide a machine check handler or CPU register initialization tables for ACPI S3 resume. It also only supports the number of CPUs reported by the MP Services Protocol, so this module does not support hot plug CPUs. This module can be copied into a CPU specific package and customized if these additional features are required.

Copyright (c) 2015, Intel Corporation. All rights reserved.

Copyright (c) 2015, Red Hat, Inc.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxeExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • CpuS3DataDxe
CpuS3DataDxeExtra.uni File Reference

Detailed Description

CpuS3DataDxe Localized Strings and Content

Copyright (c) 2015, Intel Corporation. All rights reserved.

Copyright (c) 2015, Red Hat, Inc.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include Directory Reference

  • UefiCpuPkg
  • Include
Include Directory Reference

Directories

directory | Guid
directory | Library
directory | Protocol
directory | Register

Files

file | AcpiCpuData.h
file | CpuHotPlugData.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Guid Directory Reference

  • UefiCpuPkg
  • Include
  • Guid
Guid Directory Reference

Files

file | CpuFeaturesInitDone.h
file | CpuFeaturesSetDone.h
file | MsegSmram.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Guid/CpuFeaturesInitDone.h File Reference

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Variables
CpuFeaturesInitDone.h File Reference

Variables

EFI_GUID gEdkiiCpuFeaturesInitDoneGuid

Detailed Description

CPU Features Init Done PPI/Protocol should be installed after CPU features are initialized.

Copyright (c) 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Guid/CpuFeaturesSetDone.h File Reference

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Variables
CpuFeaturesSetDone.h File Reference

Variables

EFI_GUID gEdkiiCpuFeaturesSetDoneGuid

Detailed Description

CPU Features Set Done PPI/Protocol should be installed after CPU features configuration are set.

Copyright (c) 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Guid/MsegSmram.h File Reference

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  • UefiCpuPkg
  • Include
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Variables
MsegSmram.h File Reference

Variables

EFI_GUID gMsegSmramGuid

Detailed Description

Defines the HOB GUID used to describe the MSEG memory region allocated in PEI.

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library Directory Reference

  • UefiCpuPkg
  • Include
  • Library
Library Directory Reference

Files

file | LocalApicLib.h
file | MpInitLib.h
file | MtrrLib.h
file | PlatformSecLib.h
file | RegisterCpuFeaturesLib.h
file | SmmCpuFeaturesLib.h
file | SmmCpuPlatformHookLib.h
file | UefiCpuLib.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/LocalApicLib.h File Reference

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  • Include
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Functions
LocalApicLib.h File Reference

Functions

UINTN EFIAPI | GetLocalApicBaseAddress (VOID)
VOID EFIAPI | SetLocalApicBaseAddress (IN UINTN BaseAddress)
UINTN EFIAPI | GetApicMode (VOID)
VOID EFIAPI | SetApicMode (IN UINTN ApicMode)
UINT32 EFIAPI | GetInitialApicId (VOID)
UINT32 EFIAPI | GetApicId (VOID)
UINT32 EFIAPI | GetApicVersion (VOID)
VOID EFIAPI | SendFixedIpi (IN UINT32 ApicId, IN UINT8 Vector)
VOID EFIAPI | SendFixedIpiAllExcludingSelf (IN UINT8 Vector)
VOID EFIAPI | SendSmiIpi (IN UINT32 ApicId)
VOID EFIAPI | SendSmiIpiAllExcludingSelf (VOID)
VOID EFIAPI | SendInitIpi (IN UINT32 ApicId)
VOID EFIAPI | SendInitIpiAllExcludingSelf (VOID)
VOID EFIAPI | SendInitSipiSipi (IN UINT32 ApicId, IN UINT32 StartupRoutine)
VOID EFIAPI | SendInitSipiSipiAllExcludingSelf (IN UINT32 StartupRoutine)
VOID EFIAPI | InitializeLocalApicSoftwareEnable (IN BOOLEAN Enable)
VOID EFIAPI | ProgramVirtualWireMode (VOID)
VOID EFIAPI | DisableLvtInterrupts (VOID)
UINT32 EFIAPI | GetApicTimerInitCount (VOID)
UINT32 EFIAPI | GetApicTimerCurrentCount (VOID)
VOID EFIAPI | InitializeApicTimer (IN UINTN DivideValue, IN UINT32 InitCount, IN BOOLEAN PeriodicMode, IN UINT8 Vector)
VOID EFIAPI | GetApicTimerState (OUT UINTN *DivideValue OPTIONAL, OUT BOOLEAN *PeriodicMode OPTIONAL, OUT UINT8 *Vector OPTIONAL)
VOID EFIAPI | EnableApicTimerInterrupt (VOID)
VOID EFIAPI | DisableApicTimerInterrupt (VOID)
BOOLEAN EFIAPI | GetApicTimerInterruptState (VOID)
VOID EFIAPI | SendApicEoi (VOID)
UINT32 EFIAPI | GetApicMsiAddress (VOID)
UINT64 EFIAPI | GetApicMsiValue (IN UINT8 Vector, IN UINTN DeliveryMode, IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel)
VOID EFIAPI | GetProcessorLocationByApicId (IN UINT32 InitialApicId, OUT UINT32 *Package OPTIONAL, OUT UINT32 *Core OPTIONAL, OUT UINT32 *Thread OPTIONAL)

Detailed Description

Public include file for Local APIC library.

Local APIC library assumes local APIC is enabled. It does not handles cases where local APIC is disabled.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI DisableApicTimerInterrupt ( VOID )

Disable the local APIC timer interrupt.

VOID EFIAPI DisableLvtInterrupts ( VOID )

Disable LINT0 & LINT1 interrupts.

This function sets the mask flag in the LVT LINT0 & LINT1 registers.

VOID EFIAPI EnableApicTimerInterrupt ( VOID )

Enable the local APIC timer interrupt.

UINT32 EFIAPI GetApicId ( VOID )

Get the local APIC ID of the executing processor.

Returns
32-bit local APIC ID of the executing processor.
UINTN EFIAPI GetApicMode ( VOID )

Get the current local APIC mode.

If local APIC is disabled, then ASSERT.

Return values
LOCAL_APIC_MODE_XAPIC | current APIC mode is xAPIC.
LOCAL_APIC_MODE_X2APIC | current APIC mode is x2APIC.
UINT32 EFIAPI GetApicMsiAddress ( VOID )

Get the 32-bit address that a device should use to send a Message Signaled Interrupt (MSI) to the Local APIC of the currently executing processor.

Returns
32-bit address used to send an MSI to the Local APIC.
UINT64 EFIAPI GetApicMsiValue | ( | IN UINT8 | Vector,
 |  | IN UINTN | DeliveryMode,
 |  | IN BOOLEAN | LevelTriggered,
 |  | IN BOOLEAN | AssertionLevel
 | ) |  |

Get the 64-bit data value that a device should use to send a Message Signaled Interrupt (MSI) to the Local APIC of the currently executing processor.

If Vector is not in range 0x10..0xFE, then ASSERT(). If DeliveryMode is not supported, then ASSERT().

Parameters
Vector | The 8-bit interrupt vector associated with the MSI. Must be in the range 0x10..0xFE
DeliveryMode | A 3-bit value that specifies how the recept of the MSI is handled. The only supported values are: 0: LOCAL_APIC_DELIVERY_MODE_FIXED 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 2: LOCAL_APIC_DELIVERY_MODE_SMI 4: LOCAL_APIC_DELIVERY_MODE_NMI 5: LOCAL_APIC_DELIVERY_MODE_INIT 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
LevelTriggered | TRUE specifies a level triggered interrupt. FALSE specifies an edge triggered interrupt.
AssertionLevel | Ignored if LevelTriggered is FALSE. TRUE specifies a level triggered interrupt that active when the interrupt line is asserted. FALSE specifies a level triggered interrupt that active when the interrupt line is deasserted.
Returns
64-bit data value used to send an MSI to the Local APIC.
UINT32 EFIAPI GetApicTimerCurrentCount ( VOID )

Read the current count value from the current-count register.

Returns
The current count value read from the current-count register.
UINT32 EFIAPI GetApicTimerInitCount ( VOID )

Read the initial count value from the init-count register.

Returns
The initial count value read from the init-count register.
BOOLEAN EFIAPI GetApicTimerInterruptState ( VOID )

Get the local APIC timer interrupt state.

Return values
TRUE | The local APIC timer interrupt is enabled.
FALSE | The local APIC timer interrupt is disabled.
VOID EFIAPI GetApicTimerState | ( | OUT UINTN *DivideValue | OPTIONAL,
 |  | OUT BOOLEAN *PeriodicMode | OPTIONAL,
 |  | OUT UINT8 *Vector | OPTIONAL
 | ) |  |

Get the state of the local APIC timer.

Parameters
DivideValue | Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
PeriodicMode | Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | Return the timer interrupt vector number.

Get the state of the local APIC timer.

This function will ASSERT if the local APIC is not software enabled.

Parameters
DivideValue | Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
PeriodicMode | Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | Return the timer interrupt vector number.
UINT32 EFIAPI GetApicVersion ( VOID )

Get the value of the local APIC version register.

Returns
the value of the local APIC version register.
UINT32 EFIAPI GetInitialApicId ( VOID )

Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.

In xAPIC mode, the initial local APIC ID may be different from current APIC ID. In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, the 32-bit local APIC ID is returned as initial APIC ID.

Returns
32-bit initial local APIC ID of the executing processor.
UINTN EFIAPI GetLocalApicBaseAddress ( VOID )

Retrieve the base address of local APIC.

Returns
The base address of local APIC.
VOID EFIAPI GetProcessorLocationByApicId | ( | IN UINT32 | InitialApicId,
 |  | OUT UINT32 *Package | OPTIONAL,
 |  | OUT UINT32 *Core | OPTIONAL,
 |  | OUT UINT32 *Thread | OPTIONAL
 | ) |  |

Get Package ID/Core ID/Thread ID of a processor.

The algorithm assumes the target system has symmetry across physical package boundaries with respect to the number of logical processors per package, number of cores per package.

Parameters
[in] | InitialApicId | Initial APIC ID of the target logical processor.
[out] | Package | Returns the processor package ID.
[out] | Core | Returns the processor core ID.
[out] | Thread | Returns the processor thread ID.
VOID EFIAPI InitializeApicTimer | ( | IN UINTN | DivideValue,
 |  | IN UINT32 | InitCount,
 |  | IN BOOLEAN | PeriodicMode,
 |  | IN UINT8 | Vector
 | ) |  |

Initialize the local APIC timer.

The local APIC timer is initialized and enabled.

Parameters
DivideValue | The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128. If it is 0, then use the current divide value in the DCR.
InitCount | The initial count value.
PeriodicMode | If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | The timer interrupt vector number.
VOID EFIAPI InitializeLocalApicSoftwareEnable ( IN BOOLEAN Enable )

Initialize the state of the SoftwareEnable bit in the Local APIC Spurious Interrupt Vector register.

Parameters
Enable If TRUE, then set SoftwareEnable to 1 If FALSE, then set SoftwareEnable to 0.
VOID EFIAPI ProgramVirtualWireMode ( VOID )

Programming Virtual Wire Mode.

This function programs the local APIC for virtual wire mode following the example described in chapter A.3 of the MP 1.4 spec.

IOxAPIC is not involved in this type of virtual wire mode.

VOID EFIAPI SendApicEoi ( VOID )

Send EOI to the local APIC.

VOID EFIAPI SendFixedIpi | ( | IN UINT32 | ApicId,
 |  | IN UINT8 | Vector
 | ) |  |

Send a Fixed IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId | The local APIC ID of the target processor.
Vector | The vector number of the interrupt being sent.
VOID EFIAPI SendFixedIpiAllExcludingSelf ( IN UINT8 Vector )

Send a Fixed IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

Parameters
Vector The vector number of the interrupt being sent.
VOID EFIAPI SendInitIpi ( IN UINT32 ApicId )

Send an INIT IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId Specify the local APIC ID of the target processor.
VOID EFIAPI SendInitIpiAllExcludingSelf ( VOID )

Send an INIT IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

VOID EFIAPI SendInitSipiSipi | ( | IN UINT32 | ApicId,
 |  | IN UINT32 | StartupRoutine
 | ) |  |

Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

if StartupRoutine >= 1M, then ASSERT. if StartupRoutine is not multiple of 4K, then ASSERT.

Parameters
ApicId | Specify the local APIC ID of the target processor.
StartupRoutine | Points to a start-up routine which is below 1M physical address and 4K aligned.
VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( IN UINT32 StartupRoutine )

Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

if StartupRoutine >= 1M, then ASSERT. if StartupRoutine is not multiple of 4K, then ASSERT.

Parameters
StartupRoutine Points to a start-up routine which is below 1M physical address and 4K aligned.
VOID EFIAPI SendSmiIpi ( IN UINT32 ApicId )

Send a SMI IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId Specify the local APIC ID of the target processor.
VOID EFIAPI SendSmiIpiAllExcludingSelf ( VOID )

Send a SMI IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

VOID EFIAPI SetApicMode ( IN UINTN ApicMode )

Set the current local APIC mode.

If the specified local APIC mode is not valid, then ASSERT. If the specified local APIC mode can't be set as current, then ASSERT.

Parameters
ApicMode APIC mode to be set.
Note
This API must not be called from an interrupt handler or SMI handler. It may result in unpredictable behavior.
VOID EFIAPI SetLocalApicBaseAddress ( IN UINTN BaseAddress )

Set the base address of local APIC.

If BaseAddress is not aligned on a 4KB boundary, then ASSERT().

Parameters
[in] BaseAddress Local APIC base address to be set.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/MpInitLib.h File Reference

  • File List
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  • UefiCpuPkg
  • Include
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Functions
MpInitLib.h File Reference

Functions

EFI_STATUS EFIAPI | MpInitLibInitialize (VOID)
EFI_STATUS EFIAPI | MpInitLibGetNumberOfProcessors (OUT UINTN *NumberOfProcessors, OPTIONAL OUT UINTN *NumberOfEnabledProcessors OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibGetProcessorInfo (IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibStartupAllAPs (IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibStartupThisAP (IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibSwitchBSP (IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | MpInitLibEnableDisableAP (IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibWhoAmI (OUT UINTN *ProcessorNumber)

Detailed Description

Multiple-Processor initialization Library.

Copyright (c) 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI MpInitLibEnableDisableAP | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibGetNumberOfProcessors | ( | OUT UINTN * | NumberOfProcessors,
 |  | OPTIONAL OUT UINTN *NumberOfEnabledProcessors | OPTIONAL
 | ) |  |

Retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. This service may only be called from the BSP.

Parameters
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL and NumberOfEnabledProcessors is NULL.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibGetProcessorInfo | ( | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer,
 |  | OUT EFI_HEALTH_FLAGS *HealthData | OPTIONAL
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
[out] | HealthData | Return processor health data.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibInitialize ( VOID )

MP Initialize Library initialization.

This service will allocate AP reset vector and wakeup all APs to do APs initialization.

This service must be invoked before all other MP Initialize Library service are invoked.

Return values
EFI_SUCCESS | MP initialization succeeds.
Others | MP initialization fails.
EFI_STATUS EFIAPI MpInitLibStartupAllAPs | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on all the enabled APs, and go on executing immediately. If all return from Procedure, or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by MpInitLibStartupAllAPs() or MPInitLibStartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If NULL, this parameter is ignored. Otherwise, if all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs. The buffer is allocated by MP Initialization library, and it's the caller's responsibility to free the buffer with FreePool() service. In blocking mode, it is ready for consumption when the call returns. In non-blocking mode, it is ready when WaitEvent is signaled. The list of failed CPU is terminated by END_OF_CPU_LIST.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_UNSUPPORTED | WaitEvent is not NULL if non-blocking mode is not supported.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI MpInitLibStartupThisAP | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function.

Parameters
[in] | Procedure | A pointer to the function to be run on the designated AP of the system. See type EFI_AP_PROCEDURE.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until this AP finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on this AP, and go on executing immediately. If this AP return from Procedure or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for this AP to finish this Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before this AP returns from Procedure, then Procedure on the AP is terminated. The AP is available for next function assigned by MpInitLibStartupAllAPs() or MpInitLibStartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure on the specified AP.
[out] | Finished | If NULL, this parameter is ignored. In blocking mode, this parameter is ignored. In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE. The caller can determine if the AP returned from Procedure by evaluating this value.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_SUCCESS | In non-blocking mode, the function has been dispatched to specified AP.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_UNSUPPORTED | WaitEvent is not NULL if non-blocking mode is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI MpInitLibSwitchBSP | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibWhoAmI ( OUT UINTN * ProcessorNumber )

This return the handle number for the calling processor. This service may be called from the BSP and APs.

Parameters
[out] ProcessorNumber Pointer to the handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.
EFI_NOT_READY | MP Initialize Library is not initialized.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/MtrrLib.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Include
  • Library
Data Structures | Typedefs | Enumerations | Functions
MtrrLib.h File Reference

Data Structures

struct | FIXED_MTRR
struct | VARIABLE_MTRR
struct | _MTRR_VARIABLE_SETTING_
struct | _MTRR_VARIABLE_SETTINGS_
struct | _MTRR_FIXED_SETTINGS_
struct | _MTRR_SETTINGS_
struct | MTRR_MEMORY_RANGE

Typedefs

typedef struct
_MTRR_VARIABLE_SETTING_ 		MTRR_VARIABLE_SETTING
typedef struct
_MTRR_VARIABLE_SETTINGS_ 		MTRR_VARIABLE_SETTINGS
typedef struct
_MTRR_FIXED_SETTINGS_ 		MTRR_FIXED_SETTINGS
typedef struct _MTRR_SETTINGS_ MTRR_SETTINGS

Enumerations

enum MTRR_MEMORY_CACHE_TYPE {
CacheUncacheable = 0, CacheWriteCombining = 1, CacheWriteThrough = 4, CacheWriteProtected = 5,
CacheWriteBack = 6, CacheInvalid = 7
}

Functions

UINT32 EFIAPI | GetVariableMtrrCount (VOID)
UINT32 EFIAPI | GetFirmwareVariableMtrrCount (VOID)
RETURN_STATUS EFIAPI | MtrrSetMemoryAttribute (IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Attribute)
MTRR_MEMORY_CACHE_TYPE EFIAPI | MtrrGetMemoryAttribute (IN PHYSICAL_ADDRESS Address)
MTRR_VARIABLE_SETTINGS *EFIAPI | MtrrGetVariableMtrr (OUT MTRR_VARIABLE_SETTINGS *VariableSettings)
MTRR_VARIABLE_SETTINGS *EFIAPI | MtrrSetVariableMtrr (IN MTRR_VARIABLE_SETTINGS *VariableSettings)
MTRR_FIXED_SETTINGS *EFIAPI | MtrrGetFixedMtrr (OUT MTRR_FIXED_SETTINGS *FixedSettings)
MTRR_FIXED_SETTINGS *EFIAPI | MtrrSetFixedMtrr (IN MTRR_FIXED_SETTINGS *FixedSettings)
MTRR_SETTINGS *EFIAPI | MtrrGetAllMtrrs (OUT MTRR_SETTINGS *MtrrSetting)
MTRR_SETTINGS *EFIAPI | MtrrSetAllMtrrs (IN MTRR_SETTINGS *MtrrSetting)
UINT32 EFIAPI | MtrrGetMemoryAttributeInVariableMtrr (IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT VARIABLE_MTRR *VariableMtrr)
VOID EFIAPI | MtrrDebugPrintAllMtrrs (VOID)
BOOLEAN EFIAPI | IsMtrrSupported (VOID)
MTRR_MEMORY_CACHE_TYPE EFIAPI | MtrrGetDefaultMemoryType (VOID)
RETURN_STATUS EFIAPI | MtrrSetMemoryAttributeInMtrrSettings (IN OUT MTRR_SETTINGS *MtrrSetting, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Attribute)
RETURN_STATUS EFIAPI | MtrrSetMemoryAttributesInMtrrSettings (IN OUT MTRR_SETTINGS *MtrrSetting, IN VOID *Scratch, IN OUT UINTN *ScratchSize, IN CONST MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount)

Detailed Description

MTRR setting library

Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT32 EFIAPI GetFirmwareVariableMtrrCount ( VOID )

Returns the firmware usable variable MTRR count for the CPU.

Returns
Firmware usable variable MTRR count
UINT32 EFIAPI GetVariableMtrrCount ( VOID )

Returns the variable MTRR count for the CPU.

Returns
Variable MTRR count
BOOLEAN EFIAPI IsMtrrSupported ( VOID )

Checks if MTRR is supported.

Return values
TRUE | MTRR is supported.
FALSE | MTRR is not supported.
VOID EFIAPI MtrrDebugPrintAllMtrrs ( VOID )

This function prints all MTRRs for debugging.

MTRR_SETTINGS* EFIAPI MtrrGetAllMtrrs ( OUT MTRR_SETTINGS * MtrrSetting )

This function gets the content in all MTRRs (variable and fixed)

Parameters
[out] MtrrSetting A buffer to hold all MTRRs content.
Returns
The pointer of MtrrSetting

This function gets the content in all MTRRs (variable and fixed)

Parameters
[out] MtrrSetting A buffer to hold all MTRRs content.
Return values
the pointer of MtrrSetting
MTRR_MEMORY_CACHE_TYPE EFIAPI MtrrGetDefaultMemoryType ( VOID )

Returns the default MTRR cache type for the system.

Returns
The default MTRR cache type.
MTRR_FIXED_SETTINGS* EFIAPI MtrrGetFixedMtrr ( OUT MTRR_FIXED_SETTINGS * FixedSettings )

This function gets the content in fixed MTRRs

Parameters
[out] FixedSettings A buffer to hold fixed MTRRs content.
Returns
The pointer of FixedSettings

This function gets the content in fixed MTRRs

Parameters
[out] FixedSettings A buffer to hold fixed MTRRs content.
Return values
The pointer of FixedSettings
MTRR_MEMORY_CACHE_TYPE EFIAPI MtrrGetMemoryAttribute ( IN PHYSICAL_ADDRESS Address )

This function will get the memory cache type of the specific address. This function is mainly for debugging purposes.

Parameters
[in] Address The specific address
Returns
The memory cache type of the specific address

This function will get the memory cache type of the specific address.

This function is mainly for debug purpose.

Parameters
[in] Address The specific address
Returns
Memory cache type of the specific address
UINT32 EFIAPI MtrrGetMemoryAttributeInVariableMtrr | ( | IN UINT64 | MtrrValidBitsMask,
 |  | IN UINT64 | MtrrValidAddressMask,
 |  | OUT VARIABLE_MTRR * | VariableMtrr
 | ) |  |

Get the attribute of variable MTRRs.

This function shadows the content of variable MTRRs into an internal array: VariableMtrr

Parameters
[in] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[in] | MtrrValidAddressMask | The valid address mask for MTRR since the base address in MTRR must align to 4K, so valid address mask equal to MtrrValidBitsMask & 0xfffffffffffff000ULL
[out] | VariableMtrr | The array to shadow variable MTRRs content
Returns
The return value of this parameter indicates the number of MTRRs which has been used.

Gets the attribute of variable MTRRs.

This function shadows the content of variable MTRRs into an internal array: VariableMtrr.

Parameters
[in] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[in] | MtrrValidAddressMask | The valid address mask for MTRR
[out] | VariableMtrr | The array to shadow variable MTRRs content
Returns
The return value of this parameter indicates the number of MTRRs which has been used.
MTRR_VARIABLE_SETTINGS* EFIAPI MtrrGetVariableMtrr ( OUT MTRR_VARIABLE_SETTINGS * VariableSettings )

This function will get the raw value in variable MTRRs

Parameters
[out] VariableSettings A buffer to hold variable MTRRs content.
Returns
The buffer point to MTRR_VARIABLE_SETTINGS in which holds the content of the variable MTRR

This function will get the raw value in variable MTRRs

Parameters
[out] VariableSettings A buffer to hold variable MTRRs content.
Returns
The VariableSettings input pointer
MTRR_SETTINGS* EFIAPI MtrrSetAllMtrrs ( IN MTRR_SETTINGS * MtrrSetting )

This function sets all MTRRs (variable and fixed)

Parameters
[in] MtrrSetting A buffer to hold all MTRRs content.
Returns
The pointer of MtrrSetting

This function sets all MTRRs (variable and fixed)

Parameters
[in] MtrrSetting A buffer holding all MTRRs content.
Return values
The pointer of MtrrSetting
MTRR_FIXED_SETTINGS* EFIAPI MtrrSetFixedMtrr ( IN MTRR_FIXED_SETTINGS * FixedSettings )

This function sets fixed MTRRs

Parameters
[in] FixedSettings A buffer holding fixed MTRRs content.
Returns
The pointer of FixedSettings

This function sets fixed MTRRs

Parameters
[in] FixedSettings A buffer to hold fixed MTRRs content.
Return values
The pointer of FixedSettings
RETURN_STATUS EFIAPI MtrrSetMemoryAttribute | ( | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Attribute
 | ) |  |

This function attempts to set the attributes for a memory range.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attribute | The bit mask of attributes to set for the memory region.
Return values
RETURN_SUCCESS | The attributes were set for the memory region.
RETURN_INVALID_PARAMETER | Length is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range. Multiple memory range attributes setting by calling this API multiple times may fail with status RETURN_OUT_OF_RESOURCES. It may not mean the number of CPU MTRRs are too small to set such memory attributes. Pass the multiple memory range attributes to one call of MtrrSetMemoryAttributesInMtrrSettings() may succeed.
RETURN_BUFFER_TOO_SMALL | The fixed internal scratch buffer is too small for MTRR calculation. Caller should use MtrrSetMemoryAttributesInMtrrSettings() to specify external scratch buffer.

This function attempts to set the attributes for a memory range.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory range.
[in] | Length | The size in bytes of the memory range.
[in] | Attributes | The bit mask of attributes to set for the memory range.
Return values
RETURN_SUCCESS | The attributes were set for the memory range.
RETURN_INVALID_PARAMETER | Length is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range. Multiple memory range attributes setting by calling this API multiple times may fail with status RETURN_OUT_OF_RESOURCES. It may not mean the number of CPU MTRRs are too small to set such memory attributes. Pass the multiple memory range attributes to one call of MtrrSetMemoryAttributesInMtrrSettings() may succeed.
RETURN_BUFFER_TOO_SMALL | The fixed internal scratch buffer is too small for MTRR calculation. Caller should use MtrrSetMemoryAttributesInMtrrSettings() to specify external scratch buffer.
RETURN_STATUS EFIAPI MtrrSetMemoryAttributeInMtrrSettings | ( | IN OUT MTRR_SETTINGS * | MtrrSetting,
 |  | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Attribute
 | ) |  |

This function attempts to set the attributes into MTRR setting buffer for a memory range.

Parameters
[in,out] | MtrrSetting | MTRR setting buffer to be set.
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attribute | The bit mask of attributes to set for the memory region.
Return values
RETURN_SUCCESS | The attributes were set for the memory region.
RETURN_INVALID_PARAMETER | Length is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range. Multiple memory range attributes setting by calling this API multiple times may fail with status RETURN_OUT_OF_RESOURCES. It may not mean the number of CPU MTRRs are too small to set such memory attributes. Pass the multiple memory range attributes to one call of MtrrSetMemoryAttributesInMtrrSettings() may succeed.
RETURN_BUFFER_TOO_SMALL | The fixed internal scratch buffer is too small for MTRR calculation. Caller should use MtrrSetMemoryAttributesInMtrrSettings() to specify external scratch buffer.

This function attempts to set the attributes into MTRR setting buffer for a memory range.

Parameters
[in,out] | MtrrSetting | MTRR setting buffer to be set.
[in] | BaseAddress | The physical address that is the start address of a memory range.
[in] | Length | The size in bytes of the memory range.
[in] | Attribute | The bit mask of attributes to set for the memory range.
Return values
RETURN_SUCCESS | The attributes were set for the memory range.
RETURN_INVALID_PARAMETER | Length is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range. Multiple memory range attributes setting by calling this API multiple times may fail with status RETURN_OUT_OF_RESOURCES. It may not mean the number of CPU MTRRs are too small to set such memory attributes. Pass the multiple memory range attributes to one call of MtrrSetMemoryAttributesInMtrrSettings() may succeed.
RETURN_BUFFER_TOO_SMALL | The fixed internal scratch buffer is too small for MTRR calculation. Caller should use MtrrSetMemoryAttributesInMtrrSettings() to specify external scratch buffer.
RETURN_STATUS EFIAPI MtrrSetMemoryAttributesInMtrrSettings | ( | IN OUT MTRR_SETTINGS * | MtrrSetting,
 |  | IN VOID * | Scratch,
 |  | IN OUT UINTN * | ScratchSize,
 |  | IN CONST MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount
 | ) |  |

This function attempts to set the attributes into MTRR setting buffer for multiple memory ranges.

Parameters
[in,out] | MtrrSetting | MTRR setting buffer to be set.
[in] | Scratch | A temporary scratch buffer that is used to perform the calculation.
[in,out] | ScratchSize | Pointer to the size in bytes of the scratch buffer. It may be updated to the actual required size when the calculation needs more scratch buffer.
[in] | Ranges | Pointer to an array of MTRR_MEMORY_RANGE. When range overlap happens, the last one takes higher priority. When the function returns, either all the attributes are set successfully, or none of them is set.
[in] | RangeCount | Count of MTRR_MEMORY_RANGE.
Return values
RETURN_SUCCESS | The attributes were set for all the memory ranges.
RETURN_INVALID_PARAMETER | Length in any range is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length in any range.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length in any range.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource ranges.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_BUFFER_TOO_SMALL | The scratch buffer is too small for MTRR calculation.
MTRR_VARIABLE_SETTINGS* EFIAPI MtrrSetVariableMtrr ( IN MTRR_VARIABLE_SETTINGS * VariableSettings )

This function sets variable MTRRs

Parameters
[in] VariableSettings A buffer to hold variable MTRRs content.
Returns
The pointer of VariableSettings
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/PlatformSecLib.h File Reference

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  • UefiCpuPkg
  • Include
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Functions
PlatformSecLib.h File Reference

Functions

EFI_PEI_PPI_DESCRIPTOR *EFIAPI | SecPlatformMain (IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData)
EFI_STATUS EFIAPI | SecPlatformInformation (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
VOID EFIAPI | SecPlatformDisableTemporaryMemory (VOID)

Detailed Description

This library class defines interface for platform to perform platform specific initialization in SEC phase.

Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI SecPlatformDisableTemporaryMemory ( VOID )

This interface disables temporary memory in SEC Phase.

EFI_STATUS EFIAPI SecPlatformInformation | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD * | PlatformInformationRecord
 | ) |  |

This interface conveys state information out of the Security (SEC) phase into PEI.

Parameters
PeiServices | Pointer to the PEI Services Table.
StructureSize | Pointer to the variable describing size of the input buffer.
PlatformInformationRecord | Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.
EFI_PEI_PPI_DESCRIPTOR* EFIAPI SecPlatformMain ( IN OUT EFI_SEC_PEI_HAND_OFF * SecCoreData )

A developer supplied function to perform platform specific operations.

It's a developer supplied function to perform any operations appropriate to a given platform. It's invoked just before passing control to PEI core by SEC core. Platform developer may modify the SecCoreData passed to PEI Core. It returns a platform specific PPI list that platform wishes to pass to PEI core. The Generic SEC core module will merge this list to join the final list passed to PEI core.

Parameters
SecCoreData The same parameter as passing to PEI core. It could be overridden by this function.
Returns
The platform specific PPI list to be passed to PEI core or NULL if there is no need of such platform specific PPI list.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h File Reference

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Data Structures | Typedefs | Functions
RegisterCpuFeaturesLib.h File Reference

Data Structures

struct REGISTER_CPU_FEATURE_INFORMATION

Typedefs

typedef VOID *(EFIAPI * | CPU_FEATURE_GET_CONFIG_DATA )(IN UINTN NumberOfProcessors)
typedef BOOLEAN(EFIAPI * | CPU_FEATURE_SUPPORT )(IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
typedef RETURN_STATUS(EFIAPI * | CPU_FEATURE_INITIALIZE )(IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Functions

BOOLEAN EFIAPI | IsCpuFeatureSupported (IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureInSetting (IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureCapability (IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureUserConfiguration (IN UINT32 Feature)
RETURN_STATUS EFIAPI | RegisterCpuFeature (IN CHAR8 *FeatureName, OPTIONAL IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc, OPTIONAL IN CPU_FEATURE_SUPPORT SupportFunc, OPTIONAL IN CPU_FEATURE_INITIALIZE InitializeFunc, OPTIONAL...)
VOID EFIAPI | CpuFeaturesDetect (VOID)
VOID EFIAPI | CpuFeaturesInitialize (VOID)
VOID EFIAPI | SwitchBspAfterFeaturesInitialize (IN UINTN ProcessorNumber)
VOID EFIAPI | CpuRegisterTableWrite (IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value)
VOID EFIAPI | PreSmmCpuRegisterTableWrite (IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value)

Detailed Description

Register CPU Features Library to register and manage CPU features.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Typedef Documentation

typedef VOID*(EFIAPI * CPU_FEATURE_GET_CONFIG_DATA)(IN UINTN NumberOfProcessors)

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
typedef RETURN_STATUS(EFIAPI * CPU_FEATURE_INITIALIZE)(IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Initializes CPU feature to specific state.

This service does not initialize hardware and only produces entries in the Register Table for specified processor. Hardware initialization on BSP/APs will be done in CpuFeaturesInitialize().

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the CPU feature must be enabled. If FALSE, then the CPU feature must be disabled.
Return values
RETURN_SUCCESS CPU feature is initialized.
Note
This service could be called by BSP only.
typedef BOOLEAN(EFIAPI * CPU_FEATURE_SUPPORT)(IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)

Detects if CPU feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | CPU feature is supported.
FALSE | CPU feature is not supported.
Note
This service could be called by BSP/APs.

Function Documentation

VOID EFIAPI CpuFeaturesDetect ( VOID )

Performs CPU features detection.

This service will invoke MP service to check CPU features' capabilities on BSP/APs.

Note
This service could be called by BSP only.
VOID EFIAPI CpuFeaturesInitialize ( VOID )

Performs CPU features Initialization.

This service will invoke MP service to perform CPU features initialization on BSP/APs per user configuration.

Note
This service could be called by BSP only.
VOID EFIAPI CpuRegisterTableWrite | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_TYPE | RegisterType,
 |  | IN UINT64 | Index,
 |  | IN UINT64 | ValueMask,
 |  | IN UINT64 | Value
 | ) |  |

Adds an entry in specified register table.

This function adds an entry in specified register table, with given register type, register index, bit section and value.

Parameters
[in] | ProcessorNumber | The index of the CPU to add a register table entry.
[in] | RegisterType | Type of the register to program
[in] | Index | Index of the register to program
[in] | ValueMask | Mask of bits in register to write
[in] | Value | Value to write
Note
This service could be called by BSP only.

Adds an entry in specified register table.

This function adds an entry in specified register table, with given register type, register index, bit section and value.

Parameters
[in] | ProcessorNumber | The index of the CPU to add a register table entry
[in] | RegisterType | Type of the register to program
[in] | Index | Index of the register to program
[in] | ValueMask | Mask of bits in register to write
[in] | Value | Value to write
Note
This service could be called by BSP only.
BOOLEAN EFIAPI IsCpuFeatureCapability ( IN UINT32 Feature )

Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesCapability.
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesCapability.
FALSE | The CPU feature is not set in PcdCpuFeaturesCapability.
Note
This service could be called by BSP only.

Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesCapability
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesCapability.
FALSE | The CPU feature is not set in PcdCpuFeaturesCapability.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI IsCpuFeatureInSetting ( IN UINT32 Feature )

Determines if a CPU feature is set in PcdCpuFeaturesSetting bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesSetting.
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSetting.
FALSE | The CPU feature is not set in PcdCpuFeaturesSetting.
Note
This service could be called by BSP only.

Determines if a CPU feature is set in PcdCpuFeaturesSetting bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesSetting
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSetting.
FALSE | The CPU feature is not set in PcdCpuFeaturesSetting.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI IsCpuFeatureSupported ( IN UINT32 Feature )

Determines if a CPU feature is enabled in PcdCpuFeaturesSupport bit mask. If a CPU feature is disabled in PcdCpuFeaturesSupport then all the code/data associated with that feature should be optimized away if compiler optimizations are enabled.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesSupport.
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSupport.
FALSE | The CPU feature is not set in PcdCpuFeaturesSupport.
Note
This service could be called by BSP only.

Determines if a CPU feature is enabled in PcdCpuFeaturesSupport bit mask. If a CPU feature is disabled in PcdCpuFeaturesSupport then all the code/data associated with that feature should be optimized away if compiler optimizations are enabled.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesSupport
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSupport.
FALSE | The CPU feature is not set in PcdCpuFeaturesSupport.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI IsCpuFeatureUserConfiguration ( IN UINT32 Feature )

Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesUserConfiguration.
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesUserConfiguration.
FALSE | The CPU feature is not set in PcdCpuFeaturesUserConfiguration.
Note
This service could be called by BSP only.

Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesUserConfiguration
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesUserConfiguration.
FALSE | The CPU feature is not set in PcdCpuFeaturesUserConfiguration.
Note
This service could be called by BSP only.
VOID EFIAPI PreSmmCpuRegisterTableWrite | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_TYPE | RegisterType,
 |  | IN UINT64 | Index,
 |  | IN UINT64 | ValueMask,
 |  | IN UINT64 | Value
 | ) |  |

Adds an entry in specified Pre-SMM register table.

This function adds an entry in specified register table, with given register type, register index, bit section and value.

Parameters
[in] | ProcessorNumber | The index of the CPU to add a register table entry.
[in] | RegisterType | Type of the register to program
[in] | Index | Index of the register to program
[in] | ValueMask | Mask of bits in register to write
[in] | Value | Value to write
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI RegisterCpuFeature | ( | IN CHAR8 * | FeatureName,
 |  | OPTIONAL IN CPU_FEATURE_GET_CONFIG_DATA | GetConfigDataFunc,
 |  | OPTIONAL IN CPU_FEATURE_SUPPORT | SupportFunc,
 |  | OPTIONAL IN CPU_FEATURE_INITIALIZE | InitializeFunc,
 |  | OPTIONAL... |
 | ) |  |

Registers a CPU Feature.

Parameters
[in] | FeatureName | A Null-terminated Ascii string indicates CPU feature name.
[in] | GetConfigDataFunc | CPU feature get configuration data function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU configuration data for the registered feature is NULL.
[in] | SupportFunc | CPU feature support function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU feature is assumed to be supported by all CPUs.
[in] | InitializeFunc | CPU feature initialize function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU feature initialization is skipped.
[in] ... Variable argument list of UINT32 CPU feature value. Values with no modifiers are the features provided by the registered functions. Values with CPU_FEATURE_BEFORE modifier are features that must be initialized after the features provided by the registered functions are used. Values with CPU_FEATURE_AFTER modifier are features that must be initialized before the features provided by the registered functions are used. The last argument in this variable argument list must always be CPU_FEATURE_END.
Return values
RETURN_SUCCESS | The CPU feature was successfully registered.
RETURN_OUT_OF_RESOURCES | There are not enough resources to register the CPU feature.
RETURN_UNSUPPORTED | Registration of the CPU feature is not supported due to a circular dependency between BEFORE and AFTER features.
Note
This service could be called by BSP only.

Registers a CPU Feature.

Parameters
[in] | FeatureName | A Null-terminated Ascii string indicates CPU feature name.
[in] | GetConfigDataFunc | CPU feature get configuration data function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU configuration data for the registered feature is NULL.
[in] | SupportFunc | CPU feature support function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU feature is assumed to be supported by all CPUs.
[in] | InitializeFunc | CPU feature initialize function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU feature initialization is skipped.
[in] ... Variable argument list of UINT32 CPU feature value. Values with no modifiers are the features provided by the registered functions. Values with CPU_FEATURE_BEFORE modifier are features that must be initialized after the features provided by the registered functions are used. Values with CPU_FEATURE_AFTER modifier are features that must be initialized before the features provided by the registered functions are used. The last argument in this variable argument list must always be CPU_FEATURE_END.
Return values
RETURN_SUCCESS | The CPU feature was successfully registered.
RETURN_OUT_OF_RESOURCES | There are not enough resources to register the CPU feature.
RETURN_UNSUPPORTED | Registration of the CPU feature is not supported due to a circular dependency between BEFORE and AFTER features.
RETURN_NOT_READY | CPU feature PCD PcdCpuFeaturesUserConfiguration not updated by Platform driver yet.
Note
This service could be called by BSP only.
VOID EFIAPI SwitchBspAfterFeaturesInitialize ( IN UINTN ProcessorNumber )

Switches to assigned BSP after CPU features initialization.

Parameters
[in] ProcessorNumber The index of the CPU executing this function.
Note
This service could be called by BSP only.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/SmmCpuFeaturesLib.h File Reference

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  • UefiCpuPkg
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Enumerations | Functions
SmmCpuFeaturesLib.h File Reference

Enumerations

enum SMM_REG_NAME { SmmRegFeatureControl, SmmRegSmmEnable, SmmRegSmmDelayed, SmmRegSmmBlocked }

Functions

VOID EFIAPI | SmmCpuFeaturesInitializeProcessor (IN UINTN CpuIndex, IN BOOLEAN IsMonarch, IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, IN CPU_HOT_PLUG_DATA *CpuHotPlugData)
UINT64 EFIAPI | SmmCpuFeaturesHookReturnFromSmm (IN UINTN CpuIndex, IN SMRAM_SAVE_STATE_MAP *CpuState, IN UINT64 NewInstructionPointer32, IN UINT64 NewInstructionPointer)
VOID EFIAPI | SmmCpuFeaturesSmmRelocationComplete (VOID)
UINTN EFIAPI | SmmCpuFeaturesGetSmiHandlerSize (VOID)
VOID EFIAPI | SmmCpuFeaturesInstallSmiHandler (IN UINTN CpuIndex, IN UINT32 SmBase, IN VOID *SmiStack, IN UINTN StackSize, IN UINTN GdtBase, IN UINTN GdtSize, IN UINTN IdtBase, IN UINTN IdtSize, IN UINT32 Cr3)
BOOLEAN EFIAPI | SmmCpuFeaturesNeedConfigureMtrrs (VOID)
VOID EFIAPI | SmmCpuFeaturesDisableSmrr (VOID)
VOID EFIAPI | SmmCpuFeaturesReenableSmrr (VOID)
VOID EFIAPI | SmmCpuFeaturesRendezvousEntry (IN UINTN CpuIndex)
VOID EFIAPI | SmmCpuFeaturesRendezvousExit (IN UINTN CpuIndex)
BOOLEAN EFIAPI | SmmCpuFeaturesIsSmmRegisterSupported (IN UINTN CpuIndex, IN SMM_REG_NAME RegName)
UINT64 EFIAPI | SmmCpuFeaturesGetSmmRegister (IN UINTN CpuIndex, IN SMM_REG_NAME RegName)
VOID EFIAPI | SmmCpuFeaturesSetSmmRegister (IN UINTN CpuIndex, IN SMM_REG_NAME RegName, IN UINT64 Value)
EFI_STATUS EFIAPI | SmmCpuFeaturesReadSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, OUT VOID *Buffer)
EFI_STATUS EFIAPI | SmmCpuFeaturesWriteSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer)
VOID EFIAPI | SmmCpuFeaturesCompleteSmmReadyToLock (VOID)
VOID *EFIAPI | SmmCpuFeaturesAllocatePageTableMemory (IN UINTN Pages)

Detailed Description

Library that provides CPU specific functions to support the PiSmmCpuDxeSmm module.

Copyright (c) 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Enumeration Type Documentation

enum SMM_REG_NAME

Enumeration of SMM registers that are accessed using the library functions SmmCpuFeaturesIsSmmRegisterSupported (), SmmCpuFeaturesGetSmmRegister (), and SmmCpuFeaturesSetSmmRegister ().

Enumerator
SmmRegFeatureControl | Read-write register to provides access to MSR_SMM_FEATURE_CONTROL if the CPU supports this MSR.
SmmRegSmmEnable | Read-only register that returns a non-zero value if the CPU is able to respond to SMIs.
SmmRegSmmDelayed | Read-only register that returns a non-zero value if the CPU is able to respond to SMIs, but is busy with other actions that are causing a delay in responding to an SMI. This register abstracts access to MSR_SMM_DELAYED if the CPU supports this MSR.
SmmRegSmmBlocked | Read-only register that returns a non-zero value if the CPU is able to respond to SMIs, but is busy with other actions that are blocking its ability to respond to an SMI. This register abstracts access to MSR_SMM_BLOCKED if the CPU supports this MSR.

Function Documentation

VOID* EFIAPI SmmCpuFeaturesAllocatePageTableMemory ( IN UINTN Pages )

This API provides a method for a CPU to allocate a specific region for storing page tables.

This API can be called more once to allocate memory for page tables.

Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer for page tables.
Return values
NULL Fail to allocate a specific region for storing page tables, Or there is no preference on where the page tables are allocated in SMRAM.
VOID EFIAPI SmmCpuFeaturesCompleteSmmReadyToLock ( VOID )

This function is hook point called after the gEfiSmmReadyToLockProtocolGuid notification is completely processed.

VOID EFIAPI SmmCpuFeaturesDisableSmrr ( VOID )

Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.

UINTN EFIAPI SmmCpuFeaturesGetSmiHandlerSize ( VOID )

Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is returned, then a custom SMI handler is not provided by this library, and the default SMI handler must be used.

Return values
0 Use the default SMI handler.
> 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler() The caller is required to allocate enough SMRAM for each CPU to support the size of the custom SMI handler.
UINT64 EFIAPI SmmCpuFeaturesGetSmmRegister | ( | IN UINTN | CpuIndex,
 |  | IN SMM_REG_NAME | RegName
 | ) |  |

Returns the current value of the SMM register for the specified CPU. If the SMM register is not supported, then 0 is returned.

Parameters
[in] | CpuIndex | The index of the CPU to read the SMM register. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | RegName | Identifies the SMM register to read.
Returns
The value of the SMM register specified by RegName from the CPU specified by CpuIndex.
UINT64 EFIAPI SmmCpuFeaturesHookReturnFromSmm | ( | IN UINTN | CpuIndex,
 |  | IN SMRAM_SAVE_STATE_MAP * | CpuState,
 |  | IN UINT64 | NewInstructionPointer32,
 |  | IN UINT64 | NewInstructionPointer
 | ) |  |

This function updates the SMRAM save state on the currently executing CPU to resume execution at a specific address after an RSM instruction. This function must evaluate the SMRAM save state to determine the execution mode the RSM instruction resumes and update the resume execution address with either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart flag in the SMRAM save state must always be cleared. This function returns the value of the instruction pointer from the SMRAM save state that was replaced. If this function returns 0, then the SMRAM save state was not modified.

This function is called during the very first SMI on each CPU after SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode to signal that the SMBASE of each CPU has been updated before the default SMBASE address is used for the first SMI to the next CPU.

Parameters
[in] | CpuIndex | The index of the CPU to hook. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | CpuState | Pointer to SMRAM Save State Map for the currently executing CPU.
[in] | NewInstructionPointer32 | Instruction pointer to use if resuming to 32-bit execution mode from 64-bit SMM.
[in] | NewInstructionPointer | Instruction pointer to use if resuming to same execution mode as SMM.
Return values
0 This function did modify the SMRAM save state.
> 0 The original instruction pointer value from the SMRAM save state before it was replaced.
VOID EFIAPI SmmCpuFeaturesInitializeProcessor | ( | IN UINTN | CpuIndex,
 |  | IN BOOLEAN | IsMonarch,
 |  | IN EFI_PROCESSOR_INFORMATION * | ProcessorInfo,
 |  | IN CPU_HOT_PLUG_DATA * | CpuHotPlugData
 | ) |  |

Called during the very first SMI into System Management Mode to initialize CPU features, including SMBASE, for the currently executing CPU. Since this is the first SMI, the SMRAM Save State Map is at the default address of SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing CPU is specified by CpuIndex and CpuIndex can be used to access information about the currently executing CPU in the ProcessorInfo array and the HotPlugCpuData data structure.

Parameters
[in] | CpuIndex | The index of the CPU to initialize. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | IsMonarch | TRUE if the CpuIndex is the index of the CPU that was elected as monarch during System Management Mode initialization. FALSE if the CpuIndex is not the index of the CPU that was elected as monarch during System Management Mode initialization.
[in] | ProcessorInfo | Pointer to an array of EFI_PROCESSOR_INFORMATION structures. ProcessorInfo[CpuIndex] contains the information for the currently executing CPU.
[in] | CpuHotPlugData | Pointer to the CPU_HOT_PLUG_DATA structure that contains the ApidId and SmBase arrays.
VOID EFIAPI SmmCpuFeaturesInstallSmiHandler | ( | IN UINTN | CpuIndex,
 |  | IN UINT32 | SmBase,
 |  | IN VOID * | SmiStack,
 |  | IN UINTN | StackSize,
 |  | IN UINTN | GdtBase,
 |  | IN UINTN | GdtSize,
 |  | IN UINTN | IdtBase,
 |  | IN UINTN | IdtSize,
 |  | IN UINT32 | Cr3
 | ) |  |

Install a custom SMI handler for the CPU specified by CpuIndex. This function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater than zero and is called by the CPU that was elected as monarch during System Management Mode initialization.

Parameters
[in] | CpuIndex | The index of the CPU to install the custom SMI handler. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | SmBase | The SMBASE address for the CPU specified by CpuIndex.
[in] | SmiStack | The stack to use when an SMI is processed by the the CPU specified by CpuIndex.
[in] | StackSize | The size, in bytes, if the stack used when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtBase | The base address of the GDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtSize | The size, in bytes, of the GDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtBase | The base address of the IDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtSize | The size, in bytes, of the IDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | Cr3 | The base address of the page tables to use when an SMI is processed by the CPU specified by CpuIndex.
BOOLEAN EFIAPI SmmCpuFeaturesIsSmmRegisterSupported | ( | IN UINTN | CpuIndex,
 |  | IN SMM_REG_NAME | RegName
 | ) |  |

Check to see if an SMM register is supported by a specified CPU.

Parameters
[in] | CpuIndex | The index of the CPU to check for SMM register support. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | RegName | Identifies the SMM register to check for support.
Return values
TRUE | The SMM register specified by RegName is supported by the CPU specified by CpuIndex.
FALSE | The SMM register specified by RegName is not supported by the CPU specified by CpuIndex.
BOOLEAN EFIAPI SmmCpuFeaturesNeedConfigureMtrrs ( VOID )

Determines if MTRR registers must be configured to set SMRAM cache-ability when executing in System Management Mode.

Return values
TRUE | MTRR registers must be configured to set SMRAM cache-ability.
FALSE | MTRR registers do not need to be configured to set SMRAM cache-ability.
EFI_STATUS EFIAPI SmmCpuFeaturesReadSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | OUT VOID * | Buffer
 | ) |  |

Read an SMM Save State register on the target processor. If this function returns EFI_UNSUPPORTED, then the caller is responsible for reading the SMM Save Sate register.

Parameters
[in] | CpuIndex | The index of the CPU to read the SMM Save State. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | Register | The SMM Save State register to read.
[in] | Width | The number of bytes to read from the CPU save state.
[out] | Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State.
EFI_INVALID_PARAMTER | Buffer is NULL.
EFI_UNSUPPORTED | This function does not support reading Register.
VOID EFIAPI SmmCpuFeaturesReenableSmrr ( VOID )

Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.

VOID EFIAPI SmmCpuFeaturesRendezvousEntry ( IN UINTN CpuIndex )

Processor specific hook point each time a CPU enters System Management Mode.

Parameters
[in] CpuIndex The index of the CPU that has entered SMM. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
VOID EFIAPI SmmCpuFeaturesRendezvousExit ( IN UINTN CpuIndex )

Processor specific hook point each time a CPU exits System Management Mode.

Parameters
[in] CpuIndex The index of the CPU that is exiting SMM. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
VOID EFIAPI SmmCpuFeaturesSetSmmRegister | ( | IN UINTN | CpuIndex,
 |  | IN SMM_REG_NAME | RegName,
 |  | IN UINT64 | Value
 | ) |  |

Sets the value of an SMM register on a specified CPU. If the SMM register is not supported, then no action is performed.

Parameters
[in] | CpuIndex | The index of the CPU to write the SMM register. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | RegName | Identifies the SMM register to write. registers are read-only.
[in] | Value | The value to write to the SMM register.
VOID EFIAPI SmmCpuFeaturesSmmRelocationComplete ( VOID )

Hook point in normal execution mode that allows the one CPU that was elected as monarch during System Management Mode initialization to perform additional initialization actions immediately after all of the CPUs have processed their first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().

EFI_STATUS EFIAPI SmmCpuFeaturesWriteSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | IN CONST VOID * | Buffer
 | ) |  |

Writes an SMM Save State register on the target processor. If this function returns EFI_UNSUPPORTED, then the caller is responsible for writing the SMM Save Sate register.

Parameters
[in] | CpuIndex | The index of the CPU to write the SMM Save State. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | Register | The SMM Save State register to write.
[in] | Width | The number of bytes to write to the CPU save state.
[in] | Buffer | Upon entry, this holds the new CPU register value.
Return values
EFI_SUCCESS | The register was written to Save State.
EFI_INVALID_PARAMTER | Buffer is NULL.
EFI_UNSUPPORTED | This function does not support writing Register.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/SmmCpuPlatformHookLib.h File Reference

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Enumerations | Functions
SmmCpuPlatformHookLib.h File Reference

Enumerations

enum SMM_PAGE_SIZE_TYPE { SmmPageSize4K, SmmPageSize2M, SmmPageSize1G, MaxSmmPageSizeType }

Functions

BOOLEAN EFIAPI | PlatformValidSmi (VOID)
BOOLEAN EFIAPI | ClearTopLevelSmiStatus (VOID)
EFI_STATUS EFIAPI | PlatformSmmBspElection (OUT BOOLEAN *IsBsp)
EFI_STATUS EFIAPI | GetPlatformPageTableAttribute (IN UINT64 Address, OUT SMM_PAGE_SIZE_TYPE *PageSize, OUT UINTN *NumOfPages, OUT UINTN *PageAttribute)

Detailed Description

Public include file for the SMM CPU Platform Hook Library.

Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Enumeration Type Documentation

enum SMM_PAGE_SIZE_TYPE

SMM Page Size Type

Function Documentation

BOOLEAN EFIAPI ClearTopLevelSmiStatus ( VOID )

Clears platform top level SMI status bit.

This function clears platform top level SMI status bit.

Return values
TRUE | The platform top level SMI status is cleared.
FALSE | The platform top level SMI status cannot be cleared.
EFI_STATUS EFIAPI GetPlatformPageTableAttribute | ( | IN UINT64 | Address,
 |  | OUT SMM_PAGE_SIZE_TYPE * | PageSize,
 |  | OUT UINTN * | NumOfPages,
 |  | OUT UINTN * | PageAttribute
 | ) |  |

Get platform page table attribute .

This function gets page table attribute of platform.

Parameters
Address | Input parameter. Obtain the page table entries attribute on this address.
PageSize | Output parameter. The size of the page.
NumOfPages | Output parameter. Number of page.
PageAttribute | Output parameter. Paging Attributes (WB, UC, etc).
Return values
EFI_SUCCESS | The platform page table attribute from the address is determined.
EFI_UNSUPPORTED | The platform does not support getting page table attribute for the address.
EFI_STATUS EFIAPI PlatformSmmBspElection ( OUT BOOLEAN * IsBsp )

Performs platform specific way of SMM BSP election.

This function performs platform specific way of SMM BSP election.

Parameters
IsBsp Output parameter. TRUE: the CPU this function executes on is elected to be the SMM BSP. FALSE: the CPU this function executes on is to be SMM AP.
Return values
EFI_SUCCESS | The function executes successfully.
EFI_NOT_READY | The function does not determine whether this CPU should be BSP or AP. This may occur if hardware init sequence to enable the determination is yet to be done, or the function chooses not to do BSP election and will let SMM CPU driver to use its default BSP election process.
EFI_DEVICE_ERROR | The function cannot determine whether this CPU should be BSP or AP due to hardware error.
BOOLEAN EFIAPI PlatformValidSmi ( VOID )

Checks if platform produces a valid SMI.

This function checks if platform produces a valid SMI. This function is called at SMM entry to detect if this is a spurious SMI. This function must be implemented in an MP safe way because it is called by multiple CPU threads.

Return values
TRUE | There is a valid SMI
FALSE | There is no valid SMI
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Library/UefiCpuLib.h File Reference

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Functions
UefiCpuLib.h File Reference

Functions

VOID EFIAPI InitializeFloatingPointUnits (VOID)

Detailed Description

Public header file for UEFI CPU library class.

This library class defines some routines that are generic for IA32 family CPU to be UEFI specification compliant.

Copyright (c) 2009, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI InitializeFloatingPointUnits ( VOID )

Initializes floating point units for requirement of UEFI specification.

This function initializes floating-point control word to 0x027F (all exceptions masked,double-precision, round-to-nearest) and multimedia-extensions control word (if supported) to 0x1F80 (all exceptions masked, round-to-nearest, flush to zero for masked underflow).

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Protocol Directory Reference

  • UefiCpuPkg
  • Include
  • Protocol
Protocol Directory Reference

Files

file | SmmCpuService.h
file | SmMonitorInit.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Protocol/SmmCpuService.h File Reference

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SmmCpuService.h File Reference

Data Structures

struct _EFI_SMM_CPU_SERVICE_PROTOCOL

Typedefs

typedef struct
_EFI_SMM_CPU_SERVICE_PROTOCOL 		EFI_SMM_CPU_SERVICE_PROTOCOL
typedef IN UINTN | ProcessorNumber
typedef IN UINTN OUT
EFI_PROCESSOR_INFORMATION * 		ProcessorInfoBuffer
typedef IN UINT64 | ProcessorId
typedef IN EFI_EXCEPTION_TYPE | ExceptionType
typedef IN EFI_EXCEPTION_TYPE
IN EFI_CPU_INTERRUPT_HANDLER 		InterruptHandler

Functions

typedef EFI_STATUS (EFIAPI *EFI_SMM_GET_PROCESSOR_INFO)(IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This

Variables

EFI_GUID gEfiSmmCpuServiceProtocolGuid

Detailed Description

SMM CPU Service protocol definition.

Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

typedef EFI_STATUS ( EFIAPI * EFI_SM_MONITOR_GET_PI_RESOURCE )

Gets processor information on the requested processor at the instant this call is made. This service may only be called from the BSP.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. The new BSP can take over the execution of the old BSP and continue seamlessly from where the old one left off.

If the BSP cannot be switched prior to the return from this service, then EFI_UNSUPPORTED must be returned.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_SUCCESS | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.

Notify that a new processor has been added to the system.

The SMM CPU driver should add the processor to the SMM CPU list.

If the processor is disabled it won't participate any SMI handler during subsequent SMIs.

Parameters
This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
ProcessorId | The hardware ID of the processor.
ProcessorNumber | The handle number of processor.
ProcessorResource | A pointer to EFI_SMM_PROCESSOR_RESOURCE which holds the assigned resources.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_ALREADY_STARTED | Processor already present.
EFI_NOT_READY | Space for a new handle could not be allocated.

Notify that a processor is hot-removed.

Remove a processor from the CPU list of the SMM CPU driver. After this API is called, the removed processor must not respond to SMIs in the coherence domain.

Parameters
This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
ProcessorId | The hardware ID of the processor.
Return values
EFI_SUCCESS | The function completed successfully.
EFI_NOT_FOUND | Processor with the hardware ID specified by ProcessorId does not exist.
EFI_NOT_READY | Specified AP is busy.

This return the handle number for the calling processor. This service may be called from the BSP and APs.

This service returns the processor handle number for the calling processor. The returned value is in the range from 0 to the total number of logical processors minus 1. This service may be called from the BSP and APs. If ProcessorNumber is NULL, then EFI_INVALID_PARAMETER is returned. Otherwise, the current processors handle number is returned in ProcessorNumber, and EFI_SUCCESS is returned.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1.
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

Register exception handler.

Parameters
This | A pointer to the SMM_CPU_SERVICE_PROTOCOL instance.
ExceptionType | Defines which interrupt or exception to hook. Type EFI_EXCEPTION_TYPE and the valid values for this parameter are defined in EFI_DEBUG_SUPPORT_PROTOCOL of the UEFI 2.0 specification.
InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported.

Add resources in list to database.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are added
EFI_INVALID_PARAMETER | If nested procedure detected resource failer
EFI_OUT_OF_RESOURCES | If nested procedure returned it and we cannot allocate more areas.

Delete resources in list to database.

Parameters
ResourceList | A pointer to resource list to be deleted NULL means delete all resources.
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are deleted
EFI_INVALID_PARAMETER | If nested procedure detected resource failer

Get BIOS resources.

Parameters
ResourceList | A pointer to resource list to be filled
ResourceSize | On input it means size of resource list input. On output it means size of resource list filled, or the size of resource list to be filled if size of too small.
Return values
EFI_SUCCESS | If resources are returned.
EFI_BUFFER_TOO_SMALL | If resource list buffer is too small to hold the whole resources.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Protocol/SmMonitorInit.h File Reference

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SmMonitorInit.h File Reference

Data Structures

struct _EFI_SM_MONITOR_INIT_PROTOCOL

Typedefs

typedef IN UINTN | StmImageSize
typedef IN UINT32 NumEntries | OPTIONAL
typedef IN OUT UINT32 * | ResourceSize
typedef UINT32 | EFI_SM_MONITOR_STATE
typedef struct
_EFI_SM_MONITOR_INIT_PROTOCOL 		EFI_SM_MONITOR_INIT_PROTOCOL

Functions

typedef | EFI_STATUS (EFIAPI *EFI_SM_MONITOR_LOAD_MONITOR)(IN EFI_PHYSICAL_ADDRESS StmImage
typedef | EFI_SM_MONITOR_STATE (EFIAPI *EFI_SM_MONITOR_GET_MONITOR_STATE)(VOID)

Variables

EFI_GUID gEfiSmMonitorInitProtocolGuid

Detailed Description

STM service protocol definition

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

typedef EFI_SM_MONITOR_STATE ( EFIAPI * EFI_SM_MONITOR_GET_MONITOR_STATE )

Get STM state

Returns
STM state
typedef EFI_STATUS ( EFIAPI * EFI_SM_MONITOR_GET_PI_RESOURCE )

Load STM image to MSEG.

Parameters
StmImage | STM image
StmImageSize | STM image size
Return values
EFI_SUCCESS | Load STM to MSEG successfully
EFI_ALREADY_STARTED | STM image is already loaded to MSEG
EFI_BUFFER_TOO_SMALL | MSEG is smaller than minimal requirement of STM image
EFI_UNSUPPORTED | MSEG is not enabled

Add resources in list to database.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are added
EFI_INVALID_PARAMETER | If nested procedure detected resource failer
EFI_OUT_OF_RESOURCES | If nested procedure returned it and we cannot allocate more areas.

Delete resources in list to database.

Parameters
ResourceList | A pointer to resource list to be deleted NULL means delete all resources.
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are deleted
EFI_INVALID_PARAMETER | If nested procedure detected resource failer

Get BIOS resources.

Parameters
ResourceList | A pointer to resource list to be filled
ResourceSize | On input it means size of resource list input. On output it means size of resource list filled, or the size of resource list to be filled if size of too small.
Return values
EFI_SUCCESS | If resources are returned.
EFI_BUFFER_TOO_SMALL | If resource list buffer is too small to hold the whole resources.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register Directory Reference

  • UefiCpuPkg
  • Include
  • Register
Register Directory Reference

Directories

directory | Amd
directory | Msr

Files

file | ArchitecturalMsr.h
file | Cpuid.h
file | LocalApic.h
file | Microcode.h
file | Msr.h
file | SmramSaveStateMap.h
file | StmApi.h
file | StmResourceDescriptor.h
file | StmStatusCode.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Amd Directory Reference

  • UefiCpuPkg
  • Include
  • Register
  • Amd
Amd Directory Reference

Files

file | Cpuid.h
file | Fam17Msr.h
file | Msr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Amd/Cpuid.h File Reference

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Data Structures
Cpuid.h File Reference

Data Structures

union | CPUID_AMD_EXTENDED_CPU_SIG_EAX
union | CPUID_AMD_EXTENDED_CPU_SIG_EBX
union | CPUID_AMD_EXTENDED_CPU_SIG_ECX
union | CPUID_AMD_EXTENDED_CPU_SIG_EDX
union | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX
union | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX
union | CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX
union | CPUID_AMD_PROCESSOR_TOPOLOGY_EAX
union | CPUID_AMD_PROCESSOR_TOPOLOGY_EBX
union | CPUID_AMD_PROCESSOR_TOPOLOGY_ECX
union | CPUID_MEMORY_ENCRYPTION_INFO_EAX
union | CPUID_MEMORY_ENCRYPTION_INFO_EBX
union | CPUID_MEMORY_ENCRYPTION_INFO_ECX
union | CPUID_MEMORY_ENCRYPTION_INFO_EDX

Detailed Description

CPUID leaf definitions.

Provides defines for CPUID leaf indexes. Data structures are provided for registers returned by a CPUID leaf that contain one or more bit fields. If a register returned is a single 32-bit value, then a data structure is not provided for that register.

Copyright (c) 2017, Advanced Micro Devices. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Amd/Fam17Msr.h File Reference

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Data Structures
Fam17Msr.h File Reference

Data Structures

union MSR_SEV_STATUS_REGISTER

Detailed Description

MSR Definitions.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Amd/Msr.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
  • Amd
Msr.h File Reference

Detailed Description

MSR Definitions.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2017, Advanced Micro Devices. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
AMD64 Architecture Programming Manaul volume 2, March 2017, Sections 15.34
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr Directory Reference

  • UefiCpuPkg
  • Include
  • Register
  • Msr
Msr Directory Reference

Files

file | AtomMsr.h
file | BroadwellMsr.h
file | Core2Msr.h
file | CoreMsr.h
file | GoldmontMsr.h
file | GoldmontPlusMsr.h
file | HaswellEMsr.h
file | HaswellMsr.h
file | IvyBridgeMsr.h
file | NehalemMsr.h
file | P6Msr.h
file | Pentium4Msr.h
file | PentiumMMsr.h
file | PentiumMsr.h
file | SandyBridgeMsr.h
file | SilvermontMsr.h
file | SkylakeMsr.h
file | Xeon5600Msr.h
file | XeonDMsr.h
file | XeonE7Msr.h
file | XeonPhiMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/AtomMsr.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
  • Msr
Data Structures
AtomMsr.h File Reference

Data Structures

union | MSR_ATOM_PLATFORM_ID_REGISTER
union | MSR_ATOM_EBL_CR_POWERON_REGISTER
union | MSR_ATOM_FSB_FREQ_REGISTER
union | MSR_ATOM_BBL_CR_CTL3_REGISTER
union | MSR_ATOM_PERF_STATUS_REGISTER
union | MSR_ATOM_THERM2_CTL_REGISTER
union | MSR_ATOM_IA32_MISC_ENABLE_REGISTER
union | MSR_ATOM_PEBS_ENABLE_REGISTER

Detailed Description

MSR Definitions for the Intel(R) Atom(TM) Processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h File Reference

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  • UefiCpuPkg
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  • Register
  • Msr
Data Structures
BroadwellMsr.h File Reference

Data Structures

union | MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER
union | MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER
union | MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Broadwell microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/Core2Msr.h File Reference

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  • Include
  • Register
  • Msr
Data Structures
Core2Msr.h File Reference

Data Structures

union | MSR_CORE2_PLATFORM_ID_REGISTER
union | MSR_CORE2_EBL_CR_POWERON_REGISTER
union | MSR_CORE2_FEATURE_CONTROL_REGISTER
union | MSR_CORE2_SMRR_PHYSBASE_REGISTER
union | MSR_CORE2_SMRR_PHYSMASK_REGISTER
union | MSR_CORE2_FSB_FREQ_REGISTER
union | MSR_CORE2_PERF_STATUS_REGISTER
union | MSR_CORE2_THERM2_CTL_REGISTER
union | MSR_CORE2_IA32_MISC_ENABLE_REGISTER
union | MSR_CORE2_PERF_CAPABILITIES_REGISTER
union | MSR_CORE2_PEBS_ENABLE_REGISTER

Detailed Description

MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/CoreMsr.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
  • Msr
Data Structures
CoreMsr.h File Reference

Data Structures

union | MSR_CORE_EBL_CR_POWERON_REGISTER
union | MSR_CORE_FSB_FREQ_REGISTER
union | MSR_CORE_BBL_CR_CTL3_REGISTER
union | MSR_CORE_THERM2_CTL_REGISTER
union | MSR_CORE_IA32_MISC_ENABLE_REGISTER
union | MSR_CORE_IA32_EFER_REGISTER

Detailed Description

MSR Definitions for Intel Core Solo and Intel Core Duo Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
  • Msr
Data Structures
GoldmontMsr.h File Reference

Data Structures

union | MSR_GOLDMONT_FEATURE_CONTROL_REGISTER
union | MSR_GOLDMONT_PLATFORM_INFO_REGISTER
union | MSR_GOLDMONT_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_GOLDMONT_SMM_MCA_CAP_REGISTER
union | MSR_GOLDMONT_IA32_MISC_ENABLE_REGISTER
union | MSR_GOLDMONT_MISC_FEATURE_CONTROL_REGISTER
union | MSR_GOLDMONT_MISC_PWR_MGMT_REGISTER
union | MSR_GOLDMONT_TURBO_RATIO_LIMIT_REGISTER
union | MSR_GOLDMONT_TURBO_GROUP_CORECNT_REGISTER
union | MSR_GOLDMONT_LBR_SELECT_REGISTER
union | MSR_GOLDMONT_POWER_CTL_REGISTER
union | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
union | MSR_GOLDMONT_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
union | MSR_GOLDMONT_PEBS_ENABLE_REGISTER
union | MSR_GOLDMONT_SMM_FEATURE_CONTROL_REGISTER
union | MSR_GOLDMONT_IA32_RTIT_CTL_REGISTER
union | MSR_GOLDMONT_RAPL_POWER_UNIT_REGISTER
union | MSR_GOLDMONT_PKGC3_IRTL_REGISTER
union | MSR_GOLDMONT_PKGC_IRTL1_REGISTER
union | MSR_GOLDMONT_PKGC_IRTL2_REGISTER
union | MSR_GOLDMONT_PKG_POWER_INFO_REGISTER
union | MSR_GOLDMONT_TURBO_ACTIVATION_RATIO_REGISTER
union | MSR_GOLDMONT_CORE_PERF_LIMIT_REASONS_REGISTER
union | MSR_GOLDMONT_LASTBRANCH_FROM_IP_REGISTER
union | MSR_GOLDMONT_LASTBRANCH_TO_IP_REGISTER
union | MSR_GOLDMONT_IA32_PQR_ASSOC_REGISTER
union | MSR_GOLDMONT_IA32_L2_QOS_MASK_REGISTER
union | MSR_GOLDMONT_IA32_L2_QOS_MASK_3_REGISTER

Detailed Description

MSR Definitions for Intel Atom processors based on the Goldmont microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/GoldmontPlusMsr.h File Reference

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  • Msr
Data Structures
GoldmontPlusMsr.h File Reference

Data Structures

union MSR_GOLDMONT_PLUS_PEBS_ENABLE_REGISTER

Detailed Description

MSR Defintions for Intel Atom processors based on the Goldmont Plus microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h File Reference

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  • Register
  • Msr
Data Structures
HaswellEMsr.h File Reference

Data Structures

union | MSR_HASWELL_E_CORE_THREAD_COUNT_REGISTER
union | MSR_HASWELL_E_THREAD_ID_INFO_REGISTER
union | MSR_HASWELL_E_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_HASWELL_E_IA32_MCG_CAP_REGISTER
union | MSR_HASWELL_E_SMM_MCA_CAP_REGISTER
union | MSR_HASWELL_E_ERROR_CONTROL_REGISTER
union | MSR_HASWELL_E_TURBO_RATIO_LIMIT_REGISTER
union | MSR_HASWELL_E_TURBO_RATIO_LIMIT1_REGISTER
union | MSR_HASWELL_E_TURBO_RATIO_LIMIT2_REGISTER
union | MSR_HASWELL_E_RAPL_POWER_UNIT_REGISTER
union | MSR_HASWELL_E_DRAM_ENERGY_STATUS_REGISTER
union | MSR_HASWELL_E_PCIE_PLL_RATIO_REGISTER
union | MSR_HASWELL_E_MSRUNCORE_RATIO_LIMIT_REGISTER
union | MSR_HASWELL_E_CORE_PERF_LIMIT_REASONS_REGISTER
union | MSR_HASWELL_E_IA32_QM_EVTSEL_REGISTER
union | MSR_HASWELL_E_IA32_PQR_ASSOC_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Haswell-E microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/HaswellMsr.h File Reference

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  • Msr
Data Structures
HaswellMsr.h File Reference

Data Structures

union | MSR_HASWELL_PLATFORM_INFO_REGISTER
union | MSR_HASWELL_IA32_PERFEVTSEL_REGISTER
union | MSR_HASWELL_IA32_PERFEVTSEL2_REGISTER
union | MSR_HASWELL_LBR_SELECT_REGISTER
union | MSR_HASWELL_PKGC_IRTL1_REGISTER
union | MSR_HASWELL_PKGC_IRTL2_REGISTER
union | MSR_HASWELL_CONFIG_TDP_NOMINAL_REGISTER
union | MSR_HASWELL_CONFIG_TDP_LEVEL1_REGISTER
union | MSR_HASWELL_CONFIG_TDP_LEVEL2_REGISTER
union | MSR_HASWELL_CONFIG_TDP_CONTROL_REGISTER
union | MSR_HASWELL_TURBO_ACTIVATION_RATIO_REGISTER
union | MSR_HASWELL_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_HASWELL_SMM_MCA_CAP_REGISTER
union | MSR_HASWELL_TURBO_RATIO_LIMIT_REGISTER
union | MSR_HASWELL_UNC_PERF_GLOBAL_CTRL_REGISTER
union | MSR_HASWELL_UNC_PERF_GLOBAL_STATUS_REGISTER
union | MSR_HASWELL_UNC_PERF_FIXED_CTRL_REGISTER
union | MSR_HASWELL_UNC_PERF_FIXED_CTR_REGISTER
union | MSR_HASWELL_UNC_CBO_CONFIG_REGISTER
union | MSR_HASWELL_SMM_FEATURE_CONTROL_REGISTER
union | MSR_HASWELL_RAPL_POWER_UNIT_REGISTER
union | MSR_HASWELL_CORE_PERF_LIMIT_REASONS_REGISTER
union | MSR_HASWELL_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
union | MSR_HASWELL_RING_PERF_LIMIT_REASONS_REGISTER
union | MSR_HASWELL_PKG_C8_RESIDENCY_REGISTER
union | MSR_HASWELL_PKG_C9_RESIDENCY_REGISTER
union | MSR_HASWELL_PKG_C10_RESIDENCY_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Haswell microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h File Reference

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  • Msr
Data Structures
IvyBridgeMsr.h File Reference

Data Structures

union | MSR_IVY_BRIDGE_PLATFORM_INFO_REGISTER
union | MSR_IVY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_IVY_BRIDGE_CONFIG_TDP_NOMINAL_REGISTER
union | MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL1_REGISTER
union | MSR_IVY_BRIDGE_CONFIG_TDP_LEVEL2_REGISTER
union | MSR_IVY_BRIDGE_CONFIG_TDP_CONTROL_REGISTER
union | MSR_IVY_BRIDGE_TURBO_ACTIVATION_RATIO_REGISTER
union | MSR_IVY_BRIDGE_PPIN_CTL_REGISTER
union | MSR_IVY_BRIDGE_PLATFORM_INFO_1_REGISTER
union | MSR_IVY_BRIDGE_ERROR_CONTROL_REGISTER
union | MSR_IVY_BRIDGE_TEMPERATURE_TARGET_REGISTER
union | MSR_IVY_BRIDGE_TURBO_RATIO_LIMIT1_REGISTER
union | MSR_IVY_BRIDGE_IA32_MC6_MISC_REGISTER
union | MSR_IVY_BRIDGE_PEBS_ENABLE_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Ivy Bridge microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/NehalemMsr.h File Reference

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  • Msr
Data Structures
NehalemMsr.h File Reference

Data Structures

union | MSR_NEHALEM_PLATFORM_ID_REGISTER
union | MSR_NEHALEM_SMI_COUNT_REGISTER
union | MSR_NEHALEM_PLATFORM_INFO_REGISTER
union | MSR_NEHALEM_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_NEHALEM_PMG_IO_CAPTURE_BASE_REGISTER
union | MSR_NEHALEM_IA32_MISC_ENABLE_REGISTER
union | MSR_NEHALEM_TEMPERATURE_TARGET_REGISTER
union | MSR_NEHALEM_MISC_FEATURE_CONTROL_REGISTER
union | MSR_NEHALEM_MISC_PWR_MGMT_REGISTER
union | MSR_NEHALEM_TURBO_POWER_CURRENT_LIMIT_REGISTER
union | MSR_NEHALEM_TURBO_RATIO_LIMIT_REGISTER
union | MSR_NEHALEM_LBR_SELECT_REGISTER
union | MSR_NEHALEM_POWER_CTL_REGISTER
union | MSR_NEHALEM_PERF_GLOBAL_STATUS_REGISTER
union | MSR_NEHALEM_PERF_GLOBAL_OVF_CTRL_REGISTER
union | MSR_NEHALEM_PEBS_ENABLE_REGISTER
union | MSR_NEHALEM_PEBS_LD_LAT_REGISTER
union | MSR_NEHALEM_GQ_SNOOP_MESF_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Nehalem microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/P6Msr.h File Reference

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  • Include
  • Register
  • Msr
Data Structures
P6Msr.h File Reference

Data Structures

union | MSR_P6_IA32_PLATFORM_ID_REGISTER
union | MSR_P6_APIC_BASE_REGISTER
union | MSR_P6_EBL_CR_POWERON_REGISTER
union | MSR_P6_TEST_CTL_REGISTER
union | MSR_P6_BBL_CR_ADDR_REGISTER
union | MSR_P6_BBL_CR_CTL_REGISTER
union | MSR_P6_BBL_CR_CTL3_REGISTER
union | MSR_P6_PERFEVTSEL_REGISTER
union | MSR_P6_DEBUGCTLMSR_REGISTER
union | MSR_P6_MTRRDEFTYPE_REGISTER
union | MSR_P6_MC_STATUS_REGISTER

Detailed Description

MSR Definitions for P6 Family Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h File Reference

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Data Structures
Pentium4Msr.h File Reference

Data Structures

union | MSR_PENTIUM_4_EBC_HARD_POWERON_REGISTER
union | MSR_PENTIUM_4_EBC_SOFT_POWERON_REGISTER
union | MSR_PENTIUM_4_EBC_FREQUENCY_ID_REGISTER
union | MSR_PENTIUM_4_EBC_FREQUENCY_ID_1_REGISTER
union | MSR_PENTIUM_4_MCG_MISC_REGISTER
union | MSR_PENTIUM_4_IA32_MISC_ENABLE_REGISTER
union | MSR_PENTIUM_4_PLATFORM_BRV_REGISTER
union | MSR_PENTIUM_4_PEBS_ENABLE_REGISTER

Detailed Description

MSR Definitions for Pentium(R) 4 Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
  • Msr
Data Structures
PentiumMMsr.h File Reference

Data Structures

union | MSR_PENTIUM_M_EBL_CR_POWERON_REGISTER
union | MSR_PENTIUM_M_BBL_CR_CTL3_REGISTER
union | MSR_PENTIUM_M_THERM2_CTL_REGISTER
union | MSR_PENTIUM_M_IA32_MISC_ENABLE_REGISTER

Detailed Description

MSR Definitions for Pentium M Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/PentiumMsr.h File Reference

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  • Globals
  • UefiCpuPkg
  • Include
  • Register
  • Msr
PentiumMsr.h File Reference

Detailed Description

MSR Definitions for Pentium Processors.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h File Reference

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  • UefiCpuPkg
  • Include
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  • Msr
Data Structures
SandyBridgeMsr.h File Reference

Data Structures

union | MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER
union | MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER
union | MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER
union | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER
union | MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER
union | MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER
union | MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER
union | MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER
union | MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER
union | MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER
union | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER
union | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER
union | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
union | MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER
union | MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER
union | MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER
union | MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER
union | MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER
union | MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER
union | MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER
union | MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER
union | MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER
union | MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER
union | MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER
union | MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER
union | MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER
union | MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h File Reference

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  • UefiCpuPkg
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  • Msr
Data Structures
SilvermontMsr.h File Reference

Data Structures

union | MSR_SILVERMONT_PLATFORM_ID_REGISTER
union | MSR_SILVERMONT_EBL_CR_POWERON_REGISTER
union | MSR_SILVERMONT_SMI_COUNT_REGISTER
union | MSR_SILVERMONT_IA32_FEATURE_CONTROL_REGISTER
union | MSR_SILVERMONT_FSB_FREQ_REGISTER
union | MSR_SILVERMONT_PLATFORM_INFO_REGISTER
union | MSR_SILVERMONT_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_SILVERMONT_PMG_IO_CAPTURE_BASE_REGISTER
union | MSR_SILVERMONT_BBL_CR_CTL3_REGISTER
union | MSR_SILVERMONT_FEATURE_CONFIG_REGISTER
union | MSR_SILVERMONT_IA32_MISC_ENABLE_REGISTER
union | MSR_SILVERMONT_TEMPERATURE_TARGET_REGISTER
union | MSR_SILVERMONT_MISC_FEATURE_CONTROL_REGISTER
union | MSR_SILVERMONT_TURBO_RATIO_LIMIT_REGISTER
union | MSR_SILVERMONT_LBR_SELECT_REGISTER
union | MSR_SILVERMONT_PEBS_ENABLE_REGISTER
union | MSR_SILVERMONT_RAPL_POWER_UNIT_REGISTER
union | MSR_SILVERMONT_PKG_POWER_LIMIT_REGISTER
union | MSR_SILVERMONT_PKG_POWER_INFO_REGISTER
union | MSR_SILVERMONT_PP0_POWER_LIMIT_REGISTER

Detailed Description

MSR Definitions for Intel processors based on the Silvermont microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h File Reference

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  • UefiCpuPkg
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  • Msr
Data Structures
SkylakeMsr.h File Reference

Data Structures

union | MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER
union | MSR_SKYLAKE_POWER_CTL_REGISTER
union | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER
union | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
union | MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
union | MSR_SKYLAKE_PEBS_FRONTEND_REGISTER
union | MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER
union | MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER
union | MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER
union | MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER
union | MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER
union | MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER
union | MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER
union | MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER
union | MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER
union | MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER
union | MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER
union | MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER
union | MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER
union | MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER
union | MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER
union | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER
union | MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER
union | MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER
union | MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER
union | MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER
union | MSR_SKYLAKE_PPIN_CTL_REGISTER
union | MSR_SKYLAKE_PLATFORM_INFO_REGISTER
union | MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_SKYLAKE_IA32_MCG_CAP_REGISTER
union | MSR_SKYLAKE_SMM_MCA_CAP_REGISTER
union | MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER
union | MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER
union | MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER
union | MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER
union | MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER
union | MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER
union | MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER
union | MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER

Detailed Description

MSR Defintions for Intel processors based on the Skylake/Kabylake/Coffeelake/Cannonlake microarchitecture.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h File Reference

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Data Structures
Xeon5600Msr.h File Reference

Data Structures

union | MSR_XEON_5600_FEATURE_CONFIG_REGISTER
union | MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/XeonDMsr.h File Reference

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  • Msr
Data Structures
XeonDMsr.h File Reference

Data Structures

union | MSR_XEON_D_PPIN_CTL_REGISTER
union | MSR_XEON_D_PLATFORM_INFO_REGISTER
union | MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_XEON_D_IA32_MCG_CAP_REGISTER
union | MSR_XEON_D_SMM_MCA_CAP_REGISTER
union | MSR_XEON_D_TEMPERATURE_TARGET_REGISTER
union | MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER
union | MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER
union | MSR_XEON_D_RAPL_POWER_UNIT_REGISTER
union | MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER
union | MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER
union | MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER
union | MSR_XEON_D_IA32_QM_EVTSEL_REGISTER
union | MSR_XEON_D_IA32_PQR_ASSOC_REGISTER
union | MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER
union | MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER
union | MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor D product Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h File Reference

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  • Msr
Data Structures
XeonE7Msr.h File Reference

Data Structures

union MSR_XEON_E7_FEATURE_CONFIG_REGISTER

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Processor E7 Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h File Reference

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  • Msr
Data Structures
XeonPhiMsr.h File Reference

Data Structures

union | MSR_XEON_PHI_SMI_COUNT_REGISTER
union | MSR_XEON_PHI_PPIN_CTL_REGISTER
union | MSR_XEON_PHI_PLATFORM_INFO_REGISTER
union | MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER
union | MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER
union | MSR_XEON_PHI_FEATURE_CONFIG_REGISTER
union | MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER
union | MSR_XEON_PHI_SMM_MCA_CAP_REGISTER
union | MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER
union | MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER
union | MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER
union | MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER
union | MSR_XEON_PHI_LBR_SELECT_REGISTER
union | MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER
union | MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER
union | MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER

Detailed Description

MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/ArchitecturalMsr.h File Reference

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Data Structures | Enumerations
ArchitecturalMsr.h File Reference

Data Structures

union | MSR_IA32_PLATFORM_ID_REGISTER
union | MSR_IA32_APIC_BASE_REGISTER
union | MSR_IA32_FEATURE_CONTROL_REGISTER
union | MSR_IA32_BIOS_SIGN_ID_REGISTER
union | MSR_IA32_SMM_MONITOR_CTL_REGISTER
struct | MSEG_HEADER
union | MSR_IA32_MTRRCAP_REGISTER
union | MSR_IA32_SYSENTER_CS_REGISTER
union | MSR_IA32_MCG_CAP_REGISTER
union | MSR_IA32_MCG_STATUS_REGISTER
union | MSR_IA32_PERFEVTSEL_REGISTER
union | MSR_IA32_PERF_STATUS_REGISTER
union | MSR_IA32_PERF_CTL_REGISTER
union | MSR_IA32_CLOCK_MODULATION_REGISTER
union | MSR_IA32_THERM_INTERRUPT_REGISTER
union | MSR_IA32_THERM_STATUS_REGISTER
union | MSR_IA32_MISC_ENABLE_REGISTER
union | MSR_IA32_ENERGY_PERF_BIAS_REGISTER
union | MSR_IA32_PACKAGE_THERM_STATUS_REGISTER
union | MSR_IA32_PACKAGE_THERM_INTERRUPT_REGISTER
union | MSR_IA32_DEBUGCTL_REGISTER
union | MSR_IA32_SMRR_PHYSBASE_REGISTER
union | MSR_IA32_SMRR_PHYSMASK_REGISTER
union | MSR_IA32_DCA_0_CAP_REGISTER
union | MSR_IA32_MTRR_PHYSBASE_REGISTER
union | MSR_IA32_MTRR_PHYSMASK_REGISTER
union | MSR_IA32_PAT_REGISTER
union | MSR_IA32_MC_CTL2_REGISTER
union | MSR_IA32_MTRR_DEF_TYPE_REGISTER
union | MSR_IA32_PERF_CAPABILITIES_REGISTER
union | MSR_IA32_FIXED_CTR_CTRL_REGISTER
union | MSR_IA32_PERF_GLOBAL_STATUS_REGISTER
union | MSR_IA32_PERF_GLOBAL_CTRL_REGISTER
union | MSR_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER
union | MSR_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER
union | MSR_IA32_PERF_GLOBAL_STATUS_SET_REGISTER
union | MSR_IA32_PERF_GLOBAL_INUSE_REGISTER
union | MSR_IA32_PEBS_ENABLE_REGISTER
union | MSR_IA32_VMX_BASIC_REGISTER
union | IA32_VMX_MISC_REGISTER
union | MSR_IA32_MCG_EXT_CTL_REGISTER
union | MSR_IA32_SGX_SVN_STATUS_REGISTER
union | MSR_IA32_RTIT_OUTPUT_BASE_REGISTER
union | MSR_IA32_RTIT_OUTPUT_MASK_PTRS_REGISTER
union | RTIT_TOPA_TABLE_ENTRY
union | MSR_IA32_RTIT_CTL_REGISTER
union | MSR_IA32_RTIT_STATUS_REGISTER
union | MSR_IA32_RTIT_CR3_MATCH_REGISTER
union | MSR_IA32_RTIT_ADDR_REGISTER
union | MSR_IA32_PM_ENABLE_REGISTER
union | MSR_IA32_HWP_CAPABILITIES_REGISTER
union | MSR_IA32_HWP_REQUEST_PKG_REGISTER
union | MSR_IA32_HWP_INTERRUPT_REGISTER
union | MSR_IA32_HWP_REQUEST_REGISTER
union | MSR_IA32_HWP_STATUS_REGISTER
union | MSR_IA32_DEBUG_INTERFACE_REGISTER
union | MSR_IA32_L3_QOS_CFG_REGISTER
union | MSR_IA32_L2_QOS_CFG_REGISTER
union | MSR_IA32_QM_EVTSEL_REGISTER
union | MSR_IA32_QM_CTR_REGISTER
union | MSR_IA32_PQR_ASSOC_REGISTER
union | MSR_IA32_BNDCFGS_REGISTER
union | MSR_IA32_XSS_REGISTER
union | MSR_IA32_PKG_HDC_CTL_REGISTER
union | MSR_IA32_PM_CTL1_REGISTER
union | MSR_IA32_EFER_REGISTER
union | MSR_IA32_TSC_AUX_REGISTER

Enumerations

enum RTIT_TOPA_MEMORY_SIZE {
RtitTopaMemorySize4K = 0, RtitTopaMemorySize8K, RtitTopaMemorySize16K, RtitTopaMemorySize32K,
RtitTopaMemorySize64K, RtitTopaMemorySize128K, RtitTopaMemorySize256K, RtitTopaMemorySize512K,
RtitTopaMemorySize1M, RtitTopaMemorySize2M, RtitTopaMemorySize4M, RtitTopaMemorySize8M,
RtitTopaMemorySize16M, RtitTopaMemorySize32M, RtitTopaMemorySize64M, RtitTopaMemorySize128M
}

Detailed Description

Architectural MSR Definitions.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)

Enumeration Type Documentation

enum RTIT_TOPA_MEMORY_SIZE

The size of the associated output region usd by Topa.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Cpuid.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Include
  • Register
Data Structures
Cpuid.h File Reference

Data Structures

union | CPUID_VERSION_INFO_EAX
union | CPUID_VERSION_INFO_EBX
union | CPUID_VERSION_INFO_ECX
union | CPUID_VERSION_INFO_EDX
union | CPUID_CACHE_INFO_CACHE_TLB
union | CPUID_CACHE_PARAMS_EAX
union | CPUID_CACHE_PARAMS_EBX
union | CPUID_CACHE_PARAMS_EDX
union | CPUID_MONITOR_MWAIT_EAX
union | CPUID_MONITOR_MWAIT_EBX
union | CPUID_MONITOR_MWAIT_ECX
union | CPUID_MONITOR_MWAIT_EDX
union | CPUID_THERMAL_POWER_MANAGEMENT_EAX
union | CPUID_THERMAL_POWER_MANAGEMENT_EBX
union | CPUID_THERMAL_POWER_MANAGEMENT_ECX
union | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX
union | CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX
union | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX
union | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX
union | CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX
union | CPUID_EXTENDED_TOPOLOGY_EAX
union | CPUID_EXTENDED_TOPOLOGY_EBX
union | CPUID_EXTENDED_TOPOLOGY_ECX
union | CPUID_EXTENDED_STATE_MAIN_LEAF_EAX
union | CPUID_EXTENDED_STATE_SUB_LEAF_EAX
union | CPUID_EXTENDED_STATE_SUB_LEAF_ECX
union | CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX
union | CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF_EDX
union | CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF_EDX
union | CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF_EBX
union | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EAX
union | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_ECX
union | CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF_EDX
union | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EAX
union | CPUID_INTEL_RDT_ALLOCATION_L2_CACHE_SUB_LEAF_EDX
union | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EAX
union | CPUID_INTEL_SGX_CAPABILITIES_0_SUB_LEAF_EDX
union | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EAX
union | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EBX
union | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_ECX
union | CPUID_INTEL_SGX_CAPABILITIES_RESOURCES_SUB_LEAF_EDX
union | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX
union | CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX
union | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX
union | CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX
union | CPUID_PROCESSOR_FREQUENCY_EAX
union | CPUID_PROCESSOR_FREQUENCY_EBX
union | CPUID_PROCESSOR_FREQUENCY_ECX
union | CPUID_SOC_VENDOR_MAIN_LEAF_EBX
union | CPUID_SOC_VENDOR_BRAND_STRING_DATA
union | CPUID_EXTENDED_CPU_SIG_ECX
union | CPUID_EXTENDED_CPU_SIG_EDX
union | CPUID_BRAND_STRING_DATA
union | CPUID_EXTENDED_CACHE_INFO_ECX
union | CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX
union | CPUID_VIR_PHY_ADDRESS_SIZE_EAX

Detailed Description

CPUID leaf definitions.

Provides defines for CPUID leaf indexes. Data structures are provided for registers returned by a CPUID leaf that contain one or more bit fields. If a register returned is a single 32-bit value, then a data structure is not provided for that register.

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, September 2016, CPUID instruction.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/LocalApic.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Include
  • Register
Data Structures
LocalApic.h File Reference

Data Structures

union | LOCAL_APIC_VERSION
union | LOCAL_APIC_ICR_LOW
union | LOCAL_APIC_ICR_HIGH
union | LOCAL_APIC_SVR
union | LOCAL_APIC_DCR
union | LOCAL_APIC_LVT_TIMER
union | LOCAL_APIC_LVT_LINT
union | LOCAL_APIC_MSI_ADDRESS
union | LOCAL_APIC_MSI_DATA

Detailed Description

IA32 Local APIC Definitions.

Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Microcode.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Include
  • Register
Data Structures
Microcode.h File Reference

Data Structures

union | CPU_MICROCODE_DATE
union | CPU_MICROCODE_PROCESSOR_SIGNATURE
struct | CPU_MICROCODE_HEADER
struct | CPU_MICROCODE_EXTENDED_TABLE_HEADER
struct | CPU_MICROCODE_EXTENDED_TABLE

Detailed Description

Microcode Definitions.

Microcode Definitions based on contents of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3A, Section 9.11 Microcode Definitions

Copyright (c) 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, June 2016, Chapter 9 Processor Management and Initialization, Section 9-11.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/Msr.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Include
  • Register
Msr.h File Reference

Detailed Description

MSR Definitions.

Provides defines for Machine Specific Registers(MSR) indexes. Data structures are provided for MSRs that contain one or more bit fields. If the MSR value returned is a single 32-bit or 64-bit value, then a data structure is not provided for that MSR.

Copyright (c) 2016 ~ 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4, May 2018, Volume 4: Model-Specific-Registers (MSR)
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/SmramSaveStateMap.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Include
  • Register
Data Structures
SmramSaveStateMap.h File Reference

Data Structures

struct | SMRAM_SAVE_STATE_MAP32
struct | SMRAM_SAVE_STATE_MAP64
union | SMRAM_SAVE_STATE_MAP
union | SMRAM_SAVE_STATE_IOMISC

Detailed Description

SMRAM Save State Map Definitions.

SMRAM Save State Map definitions based on contents of the Intel(R) 64 and IA-32 Architectures Software Developer's Manual Volume 3C, Section 34.4 SMRAM Volume 3C, Section 34.5 SMI Handler Execution Environment Volume 3C, Section 34.7 Managing Synchronous and Asynchronous SMIs

Copyright (c) 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/StmApi.h File Reference

  • File List
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  • UefiCpuPkg
  • Include
  • Register
Data Structures | Enumerations
StmApi.h File Reference

Data Structures

struct | STM_FEAT
struct | SOFTWARE_STM_HEADER
struct | STM_HEADER
struct | STM_MAP_ADDRESS_RANGE_DESCRIPTOR
struct | STM_UNMAP_ADDRESS_RANGE_DESCRIPTOR
struct | STM_ADDRESS_LOOKUP_DESCRIPTOR
struct | STM_VMCS_DATABASE_REQUEST
struct | STM_EVENT_LOG_MANAGEMENT_REQUEST
struct | LOG_ENTRY_HEADER
struct | ENTRY_EVT_LOG_STARTED
struct | ENTRY_EVT_LOG_STOPPED
struct | ENTRY_EVT_LOG_INVALID_PARAM
struct | ENTRY_EVT_LOG_HANDLED_PROTECTION_EXCEPTION
struct | ENTRY_EVT_BIOS_ACCESS_UNCLAIMED_RSC
struct | ENTRY_EVT_MLE_RSC_PROT_GRANTED
struct | ENTRY_EVT_MLE_RSC_PROT_DENIED
struct | ENTRY_EVT_MLE_RSC_UNPROT
struct | ENTRY_EVT_MLE_RSC_UNPROT_ERROR
struct | ENTRY_EVT_MLE_DOMAIN_TYPE_DEGRADED
union | LOG_ENTRY_DATA
struct | STM_LOG_ENTRY
struct | STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32
struct | STM_PROTECTION_EXCEPTION_STACK_FRAME_X64
union | STM_PROTECTION_EXCEPTION_STACK_FRAME
struct | STM_PROTECTION_EXCEPTION_HANDLER
struct | STM_SMM_ENTRY_STATE
struct | STM_SMM_RESUME_STATE
struct | STM_SMM_STATE
struct | TXT_PROCESSOR_SMM_DESCRIPTOR

Enumerations

enum EVENT_TYPE {
EvtLogStarted, EvtLogStopped, EvtLogInvalidParameterDetected, EvtHandledProtectionException,
EvtBiosAccessToUnclaimedResource, EvtMleResourceProtectionGranted, EvtMleResourceProtectionDenied, EvtMleResourceUnprotect,
EvtMleResourceUnprotectError, EvtMleDomainTypeDegraded, EvtMleMax, EvtInvalid = 0xFFFFFFFF
}
enum TXT_SMM_PROTECTION_EXCEPTION_TYPE {
TxtSmmPageViolation = 1, TxtSmmMsrViolation, TxtSmmRegisterViolation, TxtSmmIoViolation,
TxtSmmPciViolation
}

Detailed Description

STM API definition

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00

Enumeration Type Documentation

enum EVENT_TYPE

Enum values for the Type field of LOG_ENTRY_HEADER

Enumerator
EvtBiosAccessToUnclaimedResource | unhandled protection exceptions result in reset & cannot be logged
EvtMleMax | add more here
EvtInvalid | Not used
enum TXT_SMM_PROTECTION_EXCEPTION_TYPE

Enum values for the ErrorCode field in STM_PROTECTION_EXCEPTION_STACK_FRAME_IA32 and STM_PROTECTION_EXCEPTION_STACK_FRAME_X64

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/StmResourceDescriptor.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
Data Structures | Enumerations
StmResourceDescriptor.h File Reference

Data Structures

struct | STM_RSC_DESC_HEADER
struct | STM_RSC_END
struct | STM_RSC_MEM_DESC
struct | STM_RSC_IO_DESC
struct | STM_RSC_MMIO_DESC
struct | STM_RSC_MSR_DESC
struct | STM_PCI_DEVICE_PATH_NODE
struct | STM_RSC_PCI_CFG_DESC
struct | STM_RSC_TRAPPED_IO_DESC
struct | STM_RSC_ALL_RESOURCES_DESC
struct | STM_REGISTER_VIOLATION_DESC
union | STM_RSC

Enumerations

enum STM_REGISTER_VIOLATION_TYPE {
StmRegisterCr0, StmRegisterCr2, StmRegisterCr3, StmRegisterCr4,
StmRegisterCr8, StmRegisterMax
}

Detailed Description

STM Resource Descriptor

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00

Enumeration Type Documentation

enum STM_REGISTER_VIOLATION_TYPE

Enum values for the RWAttributes field of STM_REGISTER_VIOLATION_DESC

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/Register/StmStatusCode.h File Reference

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  • UefiCpuPkg
  • Include
  • Register
Typedefs
StmStatusCode.h File Reference

Typedefs

typedef UINT32 STM_STATUS

Detailed Description

STM Status Codes

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Specification Reference:
SMI Transfer Monitor (STM) User Guide Revision 1.00

Typedef Documentation

typedef UINT32 STM_STATUS

STM Status Codes

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/AcpiCpuData.h File Reference

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  • Include
Data Structures | Enumerations
AcpiCpuData.h File Reference

Data Structures

struct | CPU_STATUS_INFORMATION
struct | CPU_REGISTER_TABLE_ENTRY
struct | CPU_REGISTER_TABLE
struct | ACPI_CPU_DATA

Enumerations

enum REGISTER_TYPE {
Msr, ControlRegister, MemoryMapped, CacheControl,
Semaphore, InvalidReg
}
enum CPU_FEATURE_DEPENDENCE_TYPE {
NoneDepType, ThreadDepType, CoreDepType, PackageDepType,
InvalidDepType
}

Detailed Description

Definitions for CPU S3 data.

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Include/CpuHotPlugData.h File Reference

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  • Include
Data Structures
CpuHotPlugData.h File Reference

Data Structures

struct CPU_HOT_PLUG_DATA

Detailed Description

Definition for a structure sharing information for CPU hot plug.

Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library Directory Reference

  • UefiCpuPkg
  • Library
Library Directory Reference

Directories

directory | BaseUefiCpuLib
directory | BaseXApicLib
directory | BaseXApicX2ApicLib
directory | CpuCommonFeaturesLib
directory | CpuExceptionHandlerLib
directory | MpInitLib
directory | MtrrLib
directory | PlatformSecLibNull
directory | RegisterCpuFeaturesLib
directory | SecPeiDxeTimerLibUefiCpu
directory | SmmCpuFeaturesLib
directory | SmmCpuPlatformHookLibNull
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/BaseUefiCpuLib Directory Reference

  • UefiCpuPkg
  • Library
  • BaseUefiCpuLib
BaseUefiCpuLib Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | BaseUefiCpuLib.inf
file | BaseUefiCpuLib.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.uni File Reference

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  • UefiCpuPkg
  • Library
  • BaseUefiCpuLib
BaseUefiCpuLib.uni File Reference

Detailed Description

This library defines some routines that are generic for IA32 family CPU.

The library routines are UEFI specification compliant.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/BaseXApicLib Directory Reference

  • UefiCpuPkg
  • Library
  • BaseXApicLib
BaseXApicLib Directory Reference

Files

file | BaseXApicLib.c
file | BaseXApicLib.inf
file | BaseXApicLib.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c File Reference

  • File List
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  • UefiCpuPkg
  • Library
  • BaseXApicLib
Functions
BaseXApicLib.c File Reference

Functions

BOOLEAN | StandardSignatureIsAuthenticAMD (VOID)
BOOLEAN | LocalApicBaseAddressMsrSupported (VOID)
UINTN EFIAPI | GetLocalApicBaseAddress (VOID)
VOID EFIAPI | SetLocalApicBaseAddress (IN UINTN BaseAddress)
UINT32 EFIAPI | ReadLocalApicReg (IN UINTN MmioOffset)
VOID EFIAPI | WriteLocalApicReg (IN UINTN MmioOffset, IN UINT32 Value)
VOID | SendIpi (IN UINT32 IcrLow, IN UINT32 ApicId)
UINTN EFIAPI | GetApicMode (VOID)
VOID EFIAPI | SetApicMode (IN UINTN ApicMode)
UINT32 EFIAPI | GetInitialApicId (VOID)
UINT32 EFIAPI | GetApicId (VOID)
UINT32 EFIAPI | GetApicVersion (VOID)
VOID EFIAPI | SendFixedIpi (IN UINT32 ApicId, IN UINT8 Vector)
VOID EFIAPI | SendFixedIpiAllExcludingSelf (IN UINT8 Vector)
VOID EFIAPI | SendSmiIpi (IN UINT32 ApicId)
VOID EFIAPI | SendSmiIpiAllExcludingSelf (VOID)
VOID EFIAPI | SendInitIpi (IN UINT32 ApicId)
VOID EFIAPI | SendInitIpiAllExcludingSelf (VOID)
VOID EFIAPI | SendInitSipiSipi (IN UINT32 ApicId, IN UINT32 StartupRoutine)
VOID EFIAPI | SendInitSipiSipiAllExcludingSelf (IN UINT32 StartupRoutine)
VOID EFIAPI | InitializeLocalApicSoftwareEnable (IN BOOLEAN Enable)
VOID EFIAPI | ProgramVirtualWireMode (VOID)
VOID EFIAPI | DisableLvtInterrupts (VOID)
UINT32 EFIAPI | GetApicTimerInitCount (VOID)
UINT32 EFIAPI | GetApicTimerCurrentCount (VOID)
VOID EFIAPI | InitializeApicTimer (IN UINTN DivideValue, IN UINT32 InitCount, IN BOOLEAN PeriodicMode, IN UINT8 Vector)
VOID EFIAPI | GetApicTimerState (OUT UINTN *DivideValue OPTIONAL, OUT BOOLEAN *PeriodicMode OPTIONAL, OUT UINT8 *Vector OPTIONAL)
VOID EFIAPI | EnableApicTimerInterrupt (VOID)
VOID EFIAPI | DisableApicTimerInterrupt (VOID)
BOOLEAN EFIAPI | GetApicTimerInterruptState (VOID)
VOID EFIAPI | SendApicEoi (VOID)
UINT32 EFIAPI | GetApicMsiAddress (VOID)
UINT64 EFIAPI | GetApicMsiValue (IN UINT8 Vector, IN UINTN DeliveryMode, IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel)
VOID EFIAPI | GetProcessorLocationByApicId (IN UINT32 InitialApicId, OUT UINT32 *Package OPTIONAL, OUT UINT32 *Core OPTIONAL, OUT UINT32 *Thread OPTIONAL)

Detailed Description

Local APIC Library.

This local APIC library instance supports xAPIC mode only.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI DisableApicTimerInterrupt ( VOID )

Disable the local APIC timer interrupt.

VOID EFIAPI DisableLvtInterrupts ( VOID )

Disable LINT0 & LINT1 interrupts.

This function sets the mask flag in the LVT LINT0 & LINT1 registers.

VOID EFIAPI EnableApicTimerInterrupt ( VOID )

Enable the local APIC timer interrupt.

UINT32 EFIAPI GetApicId ( VOID )

Get the local APIC ID of the executing processor.

Returns
32-bit local APIC ID of the executing processor.
UINTN EFIAPI GetApicMode ( VOID )

Get the current local APIC mode.

If local APIC is disabled, then ASSERT.

Return values
LOCAL_APIC_MODE_XAPIC | current APIC mode is xAPIC.
LOCAL_APIC_MODE_X2APIC | current APIC mode is x2APIC.
UINT32 EFIAPI GetApicMsiAddress ( VOID )

Get the 32-bit address that a device should use to send a Message Signaled Interrupt (MSI) to the Local APIC of the currently executing processor.

Returns
32-bit address used to send an MSI to the Local APIC.
UINT64 EFIAPI GetApicMsiValue | ( | IN UINT8 | Vector,
 |  | IN UINTN | DeliveryMode,
 |  | IN BOOLEAN | LevelTriggered,
 |  | IN BOOLEAN | AssertionLevel
 | ) |  |

Get the 64-bit data value that a device should use to send a Message Signaled Interrupt (MSI) to the Local APIC of the currently executing processor.

If Vector is not in range 0x10..0xFE, then ASSERT(). If DeliveryMode is not supported, then ASSERT().

Parameters
Vector | The 8-bit interrupt vector associated with the MSI. Must be in the range 0x10..0xFE
DeliveryMode | A 3-bit value that specifies how the recept of the MSI is handled. The only supported values are: 0: LOCAL_APIC_DELIVERY_MODE_FIXED 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 2: LOCAL_APIC_DELIVERY_MODE_SMI 4: LOCAL_APIC_DELIVERY_MODE_NMI 5: LOCAL_APIC_DELIVERY_MODE_INIT 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
LevelTriggered | TRUE specifies a level triggered interrupt. FALSE specifies an edge triggered interrupt.
AssertionLevel | Ignored if LevelTriggered is FALSE. TRUE specifies a level triggered interrupt that active when the interrupt line is asserted. FALSE specifies a level triggered interrupt that active when the interrupt line is deasserted.
Returns
64-bit data value used to send an MSI to the Local APIC.
UINT32 EFIAPI GetApicTimerCurrentCount ( VOID )

Read the current count value from the current-count register.

Returns
The current count value read from the current-count register.
UINT32 EFIAPI GetApicTimerInitCount ( VOID )

Read the initial count value from the init-count register.

Returns
The initial count value read from the init-count register.
BOOLEAN EFIAPI GetApicTimerInterruptState ( VOID )

Get the local APIC timer interrupt state.

Return values
TRUE | The local APIC timer interrupt is enabled.
FALSE | The local APIC timer interrupt is disabled.
VOID EFIAPI GetApicTimerState | ( | OUT UINTN *DivideValue | OPTIONAL,
 |  | OUT BOOLEAN *PeriodicMode | OPTIONAL,
 |  | OUT UINT8 *Vector | OPTIONAL
 | ) |  |

Get the state of the local APIC timer.

This function will ASSERT if the local APIC is not software enabled.

Parameters
DivideValue | Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
PeriodicMode | Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | Return the timer interrupt vector number.
UINT32 EFIAPI GetApicVersion ( VOID )

Get the value of the local APIC version register.

Returns
the value of the local APIC version register.
UINT32 EFIAPI GetInitialApicId ( VOID )

Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.

In xAPIC mode, the initial local APIC ID may be different from current APIC ID. In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, the 32-bit local APIC ID is returned as initial APIC ID.

Returns
32-bit initial local APIC ID of the executing processor.
UINTN EFIAPI GetLocalApicBaseAddress ( VOID )

Retrieve the base address of local APIC.

Returns
The base address of local APIC.
VOID EFIAPI GetProcessorLocationByApicId | ( | IN UINT32 | InitialApicId,
 |  | OUT UINT32 *Package | OPTIONAL,
 |  | OUT UINT32 *Core | OPTIONAL,
 |  | OUT UINT32 *Thread | OPTIONAL
 | ) |  |

Get Package ID/Core ID/Thread ID of a processor.

The algorithm assumes the target system has symmetry across physical package boundaries with respect to the number of logical processors per package, number of cores per package.

Parameters
[in] | InitialApicId | Initial APIC ID of the target logical processor.
[out] | Package | Returns the processor package ID.
[out] | Core | Returns the processor core ID.
[out] | Thread | Returns the processor thread ID.
VOID EFIAPI InitializeApicTimer | ( | IN UINTN | DivideValue,
 |  | IN UINT32 | InitCount,
 |  | IN BOOLEAN | PeriodicMode,
 |  | IN UINT8 | Vector
 | ) |  |

Initialize the local APIC timer.

The local APIC timer is initialized and enabled.

Parameters
DivideValue | The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128. If it is 0, then use the current divide value in the DCR.
InitCount | The initial count value.
PeriodicMode | If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | The timer interrupt vector number.
VOID EFIAPI InitializeLocalApicSoftwareEnable ( IN BOOLEAN Enable )

Initialize the state of the SoftwareEnable bit in the Local APIC Spurious Interrupt Vector register.

Parameters
Enable If TRUE, then set SoftwareEnable to 1 If FALSE, then set SoftwareEnable to 0.
BOOLEAN LocalApicBaseAddressMsrSupported ( VOID )

Determine if the CPU supports the Local APIC Base Address MSR.

Return values
TRUE | The CPU supports the Local APIC Base Address MSR.
FALSE | The CPU does not support the Local APIC Base Address MSR.
VOID EFIAPI ProgramVirtualWireMode ( VOID )

Programming Virtual Wire Mode.

This function programs the local APIC for virtual wire mode following the example described in chapter A.3 of the MP 1.4 spec.

IOxAPIC is not involved in this type of virtual wire mode.

UINT32 EFIAPI ReadLocalApicReg ( IN UINTN MmioOffset )

Read from a local APIC register.

This function reads from a local APIC register either in xAPIC or x2APIC mode. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, so this function only performs 32-bit read.

Parameters
MmioOffset The MMIO offset of the local APIC register in xAPIC mode. It must be 16-byte aligned.
Returns
32-bit Value read from the register.
VOID EFIAPI SendApicEoi ( VOID )

Send EOI to the local APIC.

VOID EFIAPI SendFixedIpi | ( | IN UINT32 | ApicId,
 |  | IN UINT8 | Vector
 | ) |  |

Send a Fixed IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId | The local APIC ID of the target processor.
Vector | The vector number of the interrupt being sent.
VOID EFIAPI SendFixedIpiAllExcludingSelf ( IN UINT8 Vector )

Send a Fixed IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

Parameters
Vector The vector number of the interrupt being sent.
VOID EFIAPI SendInitIpi ( IN UINT32 ApicId )

Send an INIT IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId Specify the local APIC ID of the target processor.
VOID EFIAPI SendInitIpiAllExcludingSelf ( VOID )

Send an INIT IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

VOID EFIAPI SendInitSipiSipi | ( | IN UINT32 | ApicId,
 |  | IN UINT32 | StartupRoutine
 | ) |  |

Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

if StartupRoutine >= 1M, then ASSERT. if StartupRoutine is not multiple of 4K, then ASSERT.

Parameters
ApicId | Specify the local APIC ID of the target processor.
StartupRoutine | Points to a start-up routine which is below 1M physical address and 4K aligned.
VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( IN UINT32 StartupRoutine )

Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

if StartupRoutine >= 1M, then ASSERT. if StartupRoutine is not multiple of 4K, then ASSERT.

Parameters
StartupRoutine Points to a start-up routine which is below 1M physical address and 4K aligned.
VOID SendIpi | ( | IN UINT32 | IcrLow,
 |  | IN UINT32 | ApicId
 | ) |  |

Send an IPI by writing to ICR.

This function returns after the IPI has been accepted by the target processor.

Parameters
IcrLow | 32-bit value to be written to the low half of ICR.
ApicId | APIC ID of the target processor if this IPI is targeted for a specific processor.
VOID EFIAPI SendSmiIpi ( IN UINT32 ApicId )

Send a SMI IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId Specify the local APIC ID of the target processor.
VOID EFIAPI SendSmiIpiAllExcludingSelf ( VOID )

Send a SMI IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

VOID EFIAPI SetApicMode ( IN UINTN ApicMode )

Set the current local APIC mode.

If the specified local APIC mode is not valid, then ASSERT. If the specified local APIC mode can't be set as current, then ASSERT.

Parameters
ApicMode APIC mode to be set.
Note
This API must not be called from an interrupt handler or SMI handler. It may result in unpredictable behavior.
VOID EFIAPI SetLocalApicBaseAddress ( IN UINTN BaseAddress )

Set the base address of local APIC.

If BaseAddress is not aligned on a 4KB boundary, then ASSERT().

Parameters
[in] BaseAddress Local APIC base address to be set.
BOOLEAN StandardSignatureIsAuthenticAMD ( VOID )

Determine if the standard CPU signature is "AuthenticAMD".

Return values
TRUE | The CPU signature matches.
FALSE | The CPU signature does not match.
VOID EFIAPI WriteLocalApicReg | ( | IN UINTN | MmioOffset,
 |  | IN UINT32 | Value
 | ) |  |

Write to a local APIC register.

This function writes to a local APIC register either in xAPIC or x2APIC mode. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, so this function only performs 32-bit write.

if the register index is invalid or unsupported in current APIC mode, then ASSERT.

Parameters
MmioOffset | The MMIO offset of the local APIC register in xAPIC mode. It must be 16-byte aligned.
Value | Value to be written to the register.
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AmdUefiCpuPkg: UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.uni File Reference

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Detailed Description

The Local Apic library supports xAPIC mode only.

Note: Local APIC library assumes local APIC is enabled. It does not handle cases where local APIC is disabled.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

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AmdUefiCpuPkg: UefiCpuPkg/Library/BaseXApicX2ApicLib Directory Reference

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file | BaseXApicX2ApicLib.c
file | BaseXApicX2ApicLib.inf
file | BaseXApicX2ApicLib.uni
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AmdUefiCpuPkg: UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c File Reference

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BaseXApicX2ApicLib.c File Reference

Functions

BOOLEAN | StandardSignatureIsAuthenticAMD (VOID)
BOOLEAN | LocalApicBaseAddressMsrSupported (VOID)
UINTN EFIAPI | GetLocalApicBaseAddress (VOID)
VOID EFIAPI | SetLocalApicBaseAddress (IN UINTN BaseAddress)
UINT32 EFIAPI | ReadLocalApicReg (IN UINTN MmioOffset)
VOID EFIAPI | WriteLocalApicReg (IN UINTN MmioOffset, IN UINT32 Value)
VOID | SendIpi (IN UINT32 IcrLow, IN UINT32 ApicId)
UINTN EFIAPI | GetApicMode (VOID)
VOID EFIAPI | SetApicMode (IN UINTN ApicMode)
UINT32 EFIAPI | GetInitialApicId (VOID)
UINT32 EFIAPI | GetApicId (VOID)
UINT32 EFIAPI | GetApicVersion (VOID)
VOID EFIAPI | SendFixedIpi (IN UINT32 ApicId, IN UINT8 Vector)
VOID EFIAPI | SendFixedIpiAllExcludingSelf (IN UINT8 Vector)
VOID EFIAPI | SendSmiIpi (IN UINT32 ApicId)
VOID EFIAPI | SendSmiIpiAllExcludingSelf (VOID)
VOID EFIAPI | SendInitIpi (IN UINT32 ApicId)
VOID EFIAPI | SendInitIpiAllExcludingSelf (VOID)
VOID EFIAPI | SendInitSipiSipi (IN UINT32 ApicId, IN UINT32 StartupRoutine)
VOID EFIAPI | SendInitSipiSipiAllExcludingSelf (IN UINT32 StartupRoutine)
VOID EFIAPI | InitializeLocalApicSoftwareEnable (IN BOOLEAN Enable)
VOID EFIAPI | ProgramVirtualWireMode (VOID)
VOID EFIAPI | DisableLvtInterrupts (VOID)
UINT32 EFIAPI | GetApicTimerInitCount (VOID)
UINT32 EFIAPI | GetApicTimerCurrentCount (VOID)
VOID EFIAPI | InitializeApicTimer (IN UINTN DivideValue, IN UINT32 InitCount, IN BOOLEAN PeriodicMode, IN UINT8 Vector)
VOID EFIAPI | GetApicTimerState (OUT UINTN *DivideValue OPTIONAL, OUT BOOLEAN *PeriodicMode OPTIONAL, OUT UINT8 *Vector OPTIONAL)
VOID EFIAPI | EnableApicTimerInterrupt (VOID)
VOID EFIAPI | DisableApicTimerInterrupt (VOID)
BOOLEAN EFIAPI | GetApicTimerInterruptState (VOID)
VOID EFIAPI | SendApicEoi (VOID)
UINT32 EFIAPI | GetApicMsiAddress (VOID)
UINT64 EFIAPI | GetApicMsiValue (IN UINT8 Vector, IN UINTN DeliveryMode, IN BOOLEAN LevelTriggered, IN BOOLEAN AssertionLevel)
VOID EFIAPI | GetProcessorLocationByApicId (IN UINT32 InitialApicId, OUT UINT32 *Package OPTIONAL, OUT UINT32 *Core OPTIONAL, OUT UINT32 *Thread OPTIONAL)

Detailed Description

Local APIC Library.

This local APIC library instance supports x2APIC capable processors which have xAPIC and x2APIC modes.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Inc. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI DisableApicTimerInterrupt ( VOID )

Disable the local APIC timer interrupt.

VOID EFIAPI DisableLvtInterrupts ( VOID )

Disable LINT0 & LINT1 interrupts.

This function sets the mask flag in the LVT LINT0 & LINT1 registers.

VOID EFIAPI EnableApicTimerInterrupt ( VOID )

Enable the local APIC timer interrupt.

UINT32 EFIAPI GetApicId ( VOID )

Get the local APIC ID of the executing processor.

Returns
32-bit local APIC ID of the executing processor.
UINTN EFIAPI GetApicMode ( VOID )

Get the current local APIC mode.

If local APIC is disabled, then ASSERT.

Return values
LOCAL_APIC_MODE_XAPIC | current APIC mode is xAPIC.
LOCAL_APIC_MODE_X2APIC | current APIC mode is x2APIC.
UINT32 EFIAPI GetApicMsiAddress ( VOID )

Get the 32-bit address that a device should use to send a Message Signaled Interrupt (MSI) to the Local APIC of the currently executing processor.

Returns
32-bit address used to send an MSI to the Local APIC.
UINT64 EFIAPI GetApicMsiValue | ( | IN UINT8 | Vector,
 |  | IN UINTN | DeliveryMode,
 |  | IN BOOLEAN | LevelTriggered,
 |  | IN BOOLEAN | AssertionLevel
 | ) |  |

Get the 64-bit data value that a device should use to send a Message Signaled Interrupt (MSI) to the Local APIC of the currently executing processor.

If Vector is not in range 0x10..0xFE, then ASSERT(). If DeliveryMode is not supported, then ASSERT().

Parameters
Vector | The 8-bit interrupt vector associated with the MSI. Must be in the range 0x10..0xFE
DeliveryMode | A 3-bit value that specifies how the recept of the MSI is handled. The only supported values are: 0: LOCAL_APIC_DELIVERY_MODE_FIXED 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 2: LOCAL_APIC_DELIVERY_MODE_SMI 4: LOCAL_APIC_DELIVERY_MODE_NMI 5: LOCAL_APIC_DELIVERY_MODE_INIT 7: LOCAL_APIC_DELIVERY_MODE_EXTINT
LevelTriggered | TRUE specifies a level triggered interrupt. FALSE specifies an edge triggered interrupt.
AssertionLevel | Ignored if LevelTriggered is FALSE. TRUE specifies a level triggered interrupt that active when the interrupt line is asserted. FALSE specifies a level triggered interrupt that active when the interrupt line is deasserted.
Returns
64-bit data value used to send an MSI to the Local APIC.
UINT32 EFIAPI GetApicTimerCurrentCount ( VOID )

Read the current count value from the current-count register.

Returns
The current count value read from the current-count register.
UINT32 EFIAPI GetApicTimerInitCount ( VOID )

Read the initial count value from the init-count register.

Returns
The initial count value read from the init-count register.
BOOLEAN EFIAPI GetApicTimerInterruptState ( VOID )

Get the local APIC timer interrupt state.

Return values
TRUE | The local APIC timer interrupt is enabled.
FALSE | The local APIC timer interrupt is disabled.
VOID EFIAPI GetApicTimerState | ( | OUT UINTN *DivideValue | OPTIONAL,
 |  | OUT BOOLEAN *PeriodicMode | OPTIONAL,
 |  | OUT UINT8 *Vector | OPTIONAL
 | ) |  |

Get the state of the local APIC timer.

This function will ASSERT if the local APIC is not software enabled.

Parameters
DivideValue | Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.
PeriodicMode | Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | Return the timer interrupt vector number.
UINT32 EFIAPI GetApicVersion ( VOID )

Get the value of the local APIC version register.

Returns
the value of the local APIC version register.
UINT32 EFIAPI GetInitialApicId ( VOID )

Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.

In xAPIC mode, the initial local APIC ID may be different from current APIC ID. In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, the 32-bit local APIC ID is returned as initial APIC ID.

Returns
32-bit initial local APIC ID of the executing processor.
UINTN EFIAPI GetLocalApicBaseAddress ( VOID )

Retrieve the base address of local APIC.

Returns
The base address of local APIC.
VOID EFIAPI GetProcessorLocationByApicId | ( | IN UINT32 | InitialApicId,
 |  | OUT UINT32 *Package | OPTIONAL,
 |  | OUT UINT32 *Core | OPTIONAL,
 |  | OUT UINT32 *Thread | OPTIONAL
 | ) |  |

Get Package ID/Core ID/Thread ID of a processor.

The algorithm assumes the target system has symmetry across physical package boundaries with respect to the number of logical processors per package, number of cores per package.

Parameters
[in] | InitialApicId | Initial APIC ID of the target logical processor.
[out] | Package | Returns the processor package ID.
[out] | Core | Returns the processor core ID.
[out] | Thread | Returns the processor thread ID.
VOID EFIAPI InitializeApicTimer | ( | IN UINTN | DivideValue,
 |  | IN UINT32 | InitCount,
 |  | IN BOOLEAN | PeriodicMode,
 |  | IN UINT8 | Vector
 | ) |  |

Initialize the local APIC timer.

The local APIC timer is initialized and enabled.

Parameters
DivideValue | The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128. If it is 0, then use the current divide value in the DCR.
InitCount | The initial count value.
PeriodicMode | If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.
Vector | The timer interrupt vector number.
VOID EFIAPI InitializeLocalApicSoftwareEnable ( IN BOOLEAN Enable )

Initialize the state of the SoftwareEnable bit in the Local APIC Spurious Interrupt Vector register.

Parameters
Enable If TRUE, then set SoftwareEnable to 1 If FALSE, then set SoftwareEnable to 0.
BOOLEAN LocalApicBaseAddressMsrSupported ( VOID )

Determine if the CPU supports the Local APIC Base Address MSR.

Return values
TRUE | The CPU supports the Local APIC Base Address MSR.
FALSE | The CPU does not support the Local APIC Base Address MSR.
VOID EFIAPI ProgramVirtualWireMode ( VOID )

Programming Virtual Wire Mode.

This function programs the local APIC for virtual wire mode following the example described in chapter A.3 of the MP 1.4 spec.

IOxAPIC is not involved in this type of virtual wire mode.

UINT32 EFIAPI ReadLocalApicReg ( IN UINTN MmioOffset )

Read from a local APIC register.

This function reads from a local APIC register either in xAPIC or x2APIC mode. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, so this function only performs 32-bit read.

Parameters
MmioOffset The MMIO offset of the local APIC register in xAPIC mode. It must be 16-byte aligned.
Returns
32-bit Value read from the register.
VOID EFIAPI SendApicEoi ( VOID )

Send EOI to the local APIC.

VOID EFIAPI SendFixedIpi | ( | IN UINT32 | ApicId,
 |  | IN UINT8 | Vector
 | ) |  |

Send a Fixed IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId | The local APIC ID of the target processor.
Vector | The vector number of the interrupt being sent.
VOID EFIAPI SendFixedIpiAllExcludingSelf ( IN UINT8 Vector )

Send a Fixed IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

Parameters
Vector The vector number of the interrupt being sent.
VOID EFIAPI SendInitIpi ( IN UINT32 ApicId )

Send an INIT IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId Specify the local APIC ID of the target processor.
VOID EFIAPI SendInitIpiAllExcludingSelf ( VOID )

Send an INIT IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

VOID EFIAPI SendInitSipiSipi | ( | IN UINT32 | ApicId,
 |  | IN UINT32 | StartupRoutine
 | ) |  |

Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

if StartupRoutine >= 1M, then ASSERT. if StartupRoutine is not multiple of 4K, then ASSERT.

Parameters
ApicId | Specify the local APIC ID of the target processor.
StartupRoutine | Points to a start-up routine which is below 1M physical address and 4K aligned.
VOID EFIAPI SendInitSipiSipiAllExcludingSelf ( IN UINT32 StartupRoutine )

Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

if StartupRoutine >= 1M, then ASSERT. if StartupRoutine is not multiple of 4K, then ASSERT.

Parameters
StartupRoutine Points to a start-up routine which is below 1M physical address and 4K aligned.
VOID SendIpi | ( | IN UINT32 | IcrLow,
 |  | IN UINT32 | ApicId
 | ) |  |

Send an IPI by writing to ICR.

This function returns after the IPI has been accepted by the target processor.

Parameters
IcrLow | 32-bit value to be written to the low half of ICR.
ApicId | APIC ID of the target processor if this IPI is targeted for a specific processor.
VOID EFIAPI SendSmiIpi ( IN UINT32 ApicId )

Send a SMI IPI to a specified target processor.

This function returns after the IPI has been accepted by the target processor.

Parameters
ApicId Specify the local APIC ID of the target processor.
VOID EFIAPI SendSmiIpiAllExcludingSelf ( VOID )

Send a SMI IPI to all processors excluding self.

This function returns after the IPI has been accepted by the target processors.

VOID EFIAPI SetApicMode ( IN UINTN ApicMode )

Set the current local APIC mode.

If the specified local APIC mode is not valid, then ASSERT. If the specified local APIC mode can't be set as current, then ASSERT.

Parameters
ApicMode APIC mode to be set.
Note
This API must not be called from an interrupt handler or SMI handler. It may result in unpredictable behavior.
VOID EFIAPI SetLocalApicBaseAddress ( IN UINTN BaseAddress )

Set the base address of local APIC.

If BaseAddress is not aligned on a 4KB boundary, then ASSERT().

Parameters
[in] BaseAddress Local APIC base address to be set.
BOOLEAN StandardSignatureIsAuthenticAMD ( VOID )

Determine if the standard CPU signature is "AuthenticAMD".

Return values
TRUE | The CPU signature matches.
FALSE | The CPU signature does not match.
VOID EFIAPI WriteLocalApicReg | ( | IN UINTN | MmioOffset,
 |  | IN UINT32 | Value
 | ) |  |

Write to a local APIC register.

This function writes to a local APIC register either in xAPIC or x2APIC mode. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, so this function only performs 32-bit write.

if the register index is invalid or unsupported in current APIC mode, then ASSERT.

Parameters
MmioOffset | The MMIO offset of the local APIC register in xAPIC mode. It must be 16-byte aligned.
Value | Value to be written to the register.
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AmdUefiCpuPkg: UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.uni File Reference

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BaseXApicX2ApicLib.uni File Reference

Detailed Description

The Local Apic library supports x2APIC capable processors which have xAPIC and x2APIC modes.

Note: Local APIC library assumes local APIC is enabled. It does not handle cases where local APIC is disabled.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib Directory Reference

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CpuCommonFeaturesLib Directory Reference

Files

file | Aesni.c
file | C1e.c
file | ClockModulation.c
file | CpuCommonFeatures.h
file | CpuCommonFeaturesLib.c
file | CpuCommonFeaturesLib.inf
file | CpuCommonFeaturesLib.uni
file | Eist.c
file | ExecuteDisable.c
file | FastStrings.c
file | FeatureControl.c
file | LimitCpuIdMaxval.c
file | MachineCheck.c
file | MonitorMwait.c
file | PendingBreak.c
file | Ppin.c
file | ProcTrace.c
file | X2Apic.c
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AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/Aesni.c File Reference

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Aesni.c File Reference

Functions

VOID *EFIAPI | AesniGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | AesniSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | AesniInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

AESNI feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* EFIAPI AesniGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI AesniInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes AESNI feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the AESNI feature must be enabled. If FALSE, then the AESNI feature must be disabled.
Return values
RETURN_SUCCESS AESNI feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI AesniSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if AESNI feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | AESNI feature is supported.
FALSE | AESNI feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c File Reference

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  • UefiCpuPkg
  • Library
  • CpuCommonFeaturesLib
Functions
C1e.c File Reference

Functions

BOOLEAN EFIAPI | C1eSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | C1eInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

C1E feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI C1eInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes C1E feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the C1E feature must be enabled. If FALSE, then the C1E feature must be disabled.
Return values
RETURN_SUCCESS C1E feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI C1eSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if C1E feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | C1E feature is supported.
FALSE | C1E feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/ClockModulation.c File Reference

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ClockModulation.c File Reference

Functions

BOOLEAN EFIAPI | ClockModulationSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | ClockModulationInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Clock Modulation feature.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI ClockModulationInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Clock Modulation feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Clock Modulation feature must be enabled. If FALSE, then the Clock Modulation feature must be disabled.
Return values
RETURN_SUCCESS Clock Modulation feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI ClockModulationSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Clock Modulation feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Clock Modulation feature is supported.
FALSE | Clock Modulation feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeatures.h File Reference

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  • UefiCpuPkg
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  • CpuCommonFeaturesLib
Functions
CpuCommonFeatures.h File Reference

Functions

VOID *EFIAPI | AesniGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | AesniSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | AesniInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | ClockModulationSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | ClockModulationInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | EistSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | EistInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | ExecuteDisableSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | ExecuteDisableInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
RETURN_STATUS EFIAPI | FastStringsInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | MonitorMwaitSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | MonitorMwaitInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | VmxSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | VmxInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | LockFeatureControlRegisterSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | LockFeatureControlRegisterInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | SmxSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | SmxInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | LimitCpuidMaxvalSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | LimitCpuidMaxvalInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | MceSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | MceInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | McaSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | McaInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | McgCtlSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | McgCtlInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | PendingBreakSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | PendingBreakInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | C1eSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | C1eInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
VOID *EFIAPI | X2ApicGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | X2ApicSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | X2ApicInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
VOID *EFIAPI | FeatureControlGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | PpinSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | PpinInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | LmceSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | LmceInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
VOID *EFIAPI | ProcTraceGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | ProcTraceSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | ProcTraceInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

CPU Common features library header file.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* EFIAPI AesniGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI AesniInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes AESNI feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the AESNI feature must be enabled. If FALSE, then the AESNI feature must be disabled.
Return values
RETURN_SUCCESS AESNI feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI AesniSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if AESNI feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | AESNI feature is supported.
FALSE | AESNI feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI C1eInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes C1E feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the C1E feature must be enabled. If FALSE, then the C1E feature must be disabled.
Return values
RETURN_SUCCESS C1E feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI C1eSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if C1E feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | C1E feature is supported.
FALSE | C1E feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI ClockModulationInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Clock Modulation feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Clock Modulation feature must be enabled. If FALSE, then the Clock Modulation feature must be disabled.
Return values
RETURN_SUCCESS Clock Modulation feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI ClockModulationSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Clock Modulation feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Clock Modulation feature is supported.
FALSE | Clock Modulation feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI EistInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Enhanced Intel SpeedStep feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Enhanced Intel SpeedStep feature must be enabled. If FALSE, then the Enhanced Intel SpeedStep feature must be disabled.
Return values
RETURN_SUCCESS Enhanced Intel SpeedStep feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI EistSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Enhanced Intel SpeedStep feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Enhanced Intel SpeedStep feature is supported.
FALSE | Enhanced Intel SpeedStep feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI ExecuteDisableInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Execute Disable feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Execute Disable feature must be enabled. If FALSE, then the Execute Disable feature must be disabled.
Return values
RETURN_SUCCESS Execute Disable feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI ExecuteDisableSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Execute Disable feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Execute Disable feature is supported.
FALSE | Execute Disable feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI FastStringsInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Fast-Strings feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Fast-Strings feature must be enabled. If FALSE, then the Fast-Strings feature must be disabled.
Return values
RETURN_SUCCESS Fast-Strings feature is initialized.
Note
This service could be called by BSP only.
VOID* EFIAPI FeatureControlGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI LimitCpuidMaxvalInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes LimitCpuidMaxval feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the LimitCpuidMaxval feature must be enabled. If FALSE, then the LimitCpuidMaxval feature must be disabled.
Return values
RETURN_SUCCESS LimitCpuidMaxval feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI LimitCpuidMaxvalSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if LimitCpuidMaxval feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | LimitCpuidMaxval feature is supported.
FALSE | LimitCpuidMaxval feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI LmceInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Local machine check exception feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Local machine check exception feature must be enabled. If FALSE, then the Local machine check exception feature must be disabled.
Return values
RETURN_SUCCESS Local machine check exception feature is initialized.
BOOLEAN EFIAPI LmceSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Local machine check exception feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Local machine check exception feature is supported.
FALSE | Local machine check exception feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI LockFeatureControlRegisterInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Lock Feature Control Register feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Lock Feature Control Register feature must be enabled. If FALSE, then the Lock Feature Control Register feature must be disabled.
Return values
RETURN_SUCCESS Lock Feature Control Register feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI LockFeatureControlRegisterSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Lock Feature Control Register feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Lock Feature Control Register feature is supported.
FALSE | Lock Feature Control Register feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI McaInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Machine Check Architecture feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Machine Check Architecture feature must be enabled. If FALSE, then the Machine Check Architecture feature must be disabled.
Return values
RETURN_SUCCESS Machine Check Architecture feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI McaSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Machine Check Architecture feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Machine Check Architecture feature is supported.
FALSE | Machine Check Architecture feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI MceInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Machine Check Exception feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Machine Check Exception feature must be enabled. If FALSE, then the Machine Check Exception feature must be disabled.
Return values
RETURN_SUCCESS Machine Check Exception feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI MceSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Machine Check Exception feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Machine Check Exception feature is supported.
FALSE | Machine Check Exception feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI McgCtlInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes IA32_MCG_CTL feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the IA32_MCG_CTL feature must be enabled. If FALSE, then the IA32_MCG_CTL feature must be disabled.
Return values
RETURN_SUCCESS IA32_MCG_CTL feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI McgCtlSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if IA32_MCG_CTL feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | IA32_MCG_CTL feature is supported.
FALSE | IA32_MCG_CTL feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI MonitorMwaitInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes MONITOR/MWAIT feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the MONITOR/MWAIT feature must be enabled. If FALSE, then the MONITOR/MWAIT feature must be disabled.
Return values
RETURN_SUCCESS MONITOR/MWAIT feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI MonitorMwaitSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if MONITOR/MWAIT feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | MONITOR/MWAIT feature is supported.
FALSE | MONITOR/MWAIT feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI PendingBreakInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Pending Break feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Pending Break feature must be enabled. If FALSE, then the Pending Break feature must be disabled.
Return values
RETURN_SUCCESS Pending Break feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI PendingBreakSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Pending Break feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Pending Break feature is supported.
FALSE | Pending Break feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI PpinInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Protected Processor Inventory Number feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Protected Processor Inventory Number feature must be enabled. If FALSE, then the Protected Processor Inventory Number feature must be disabled.
Return values
RETURN_SUCCESS | Protected Processor Inventory Number feature is initialized.
RETURN_DEVICE_ERROR | Device can't change state because it has been locked.
BOOLEAN EFIAPI PpinSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Protected Processor Inventory Number feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Protected Processor Inventory Number feature is supported.
FALSE | Protected Processor Inventory Number feature is not supported.
Note
This service could be called by BSP/APs.
VOID* EFIAPI ProcTraceGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI ProcTraceInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Intel Processor Trace feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Processor Trace feature must be enabled. If FALSE, then the Processor Trace feature must be disabled.
Return values
RETURN_SUCCESS Intel Processor Trace feature is initialized.

Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding

Clear bit 0 in MSR IA32_RTIT_CTL (570)

Clear MSR IA32_RTIT_STS (571h) to all zeros

Check Processor Trace output scheme: Single Range output or ToPA table

Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)

BOOLEAN EFIAPI ProcTraceSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Intel Processor Trace feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Processor Trace feature is supported.
FALSE | Processor Trace feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI SmxInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes SMX feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then SMX feature must be enabled. If FALSE, then SMX feature must be disabled.
Return values
RETURN_SUCCESS | SMX feature is initialized.
RETURN_UNSUPPORTED | VMX not initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI SmxSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if SMX feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | SMX feature is supported.
FALSE | SMX feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI VmxInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes VMX feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the VMX feature must be enabled. If FALSE, then the VMX feature must be disabled.
Return values
RETURN_SUCCESS VMX feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI VmxSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if VMX feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | VMX feature is supported.
FALSE | VMX feature is not supported.
Note
This service could be called by BSP/APs.
VOID* EFIAPI X2ApicGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI X2ApicInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes X2Apci feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the X2Apci feature must be enabled. If FALSE, then the X2Apci feature must be disabled.
Return values
RETURN_SUCCESS X2Apci feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI X2ApicSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if X2Apci feature supported on current processor.

Detect if X2Apci has been already enabled.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | X2Apci feature is supported.
FALSE | X2Apci feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.c File Reference

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  • UefiCpuPkg
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  • CpuCommonFeaturesLib
Functions
CpuCommonFeaturesLib.c File Reference

Functions

RETURN_STATUS EFIAPI CpuCommonFeaturesLibConstructor (VOID)

Detailed Description

This library registers CPU features defined in Intel(R) 64 and IA-32 Architectures Software Developer's Manual.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI CpuCommonFeaturesLibConstructor ( VOID )

Register CPU features.

Return values
RETURN_SUCCESS Register successfully
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/CpuCommonFeaturesLib.uni File Reference

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  • Globals
  • UefiCpuPkg
  • Library
  • CpuCommonFeaturesLib
CpuCommonFeaturesLib.uni File Reference

Detailed Description

Dxe Crc32 Guided Section Extract library.

This library doesn't produce any library class. The constructor function uses ExtractGuidedSectionLib service to register CRC32 guided section handler that parses CRC32 encapsulation section and extracts raw data.

It uses UEFI boot service CalculateCrc32 to authenticate 32 bit CRC value.

Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/Eist.c File Reference

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  • UefiCpuPkg
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  • CpuCommonFeaturesLib
Functions
Eist.c File Reference

Functions

BOOLEAN EFIAPI | EistSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | EistInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Enhanced Intel SpeedStep feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI EistInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Enhanced Intel SpeedStep feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Enhanced Intel SpeedStep feature must be enabled. If FALSE, then the Enhanced Intel SpeedStep feature must be disabled.
Return values
RETURN_SUCCESS Enhanced Intel SpeedStep feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI EistSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Enhanced Intel SpeedStep feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Enhanced Intel SpeedStep feature is supported.
FALSE | Enhanced Intel SpeedStep feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/ExecuteDisable.c File Reference

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Functions
ExecuteDisable.c File Reference

Functions

BOOLEAN EFIAPI | ExecuteDisableSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | ExecuteDisableInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Execute Disable feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI ExecuteDisableInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Execute Disable feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Execute Disable feature must be enabled. If FALSE, then the Execute Disable feature must be disabled.
Return values
RETURN_SUCCESS Execute Disable feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI ExecuteDisableSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Execute Disable feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Execute Disable feature is supported.
FALSE | Execute Disable feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/FastStrings.c File Reference

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FastStrings.c File Reference

Functions

RETURN_STATUS EFIAPI FastStringsInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Fast-Strings feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI FastStringsInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Fast-Strings feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Fast-Strings feature must be enabled. If FALSE, then the Fast-Strings feature must be disabled.
Return values
RETURN_SUCCESS Fast-Strings feature is initialized.
Note
This service could be called by BSP only.
Generated on Tue Sep 1 2020 14:37:08 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/FeatureControl.c File Reference

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FeatureControl.c File Reference

Functions

VOID *EFIAPI | FeatureControlGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | VmxSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | VmxInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | LockFeatureControlRegisterSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | LockFeatureControlRegisterInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | SmxSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | SmxInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Features in MSR_IA32_FEATURE_CONTROL register.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* EFIAPI FeatureControlGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI LockFeatureControlRegisterInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Lock Feature Control Register feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Lock Feature Control Register feature must be enabled. If FALSE, then the Lock Feature Control Register feature must be disabled.
Return values
RETURN_SUCCESS Lock Feature Control Register feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI LockFeatureControlRegisterSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Lock Feature Control Register feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Lock Feature Control Register feature is supported.
FALSE | Lock Feature Control Register feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI SmxInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes SMX feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then SMX feature must be enabled. If FALSE, then SMX feature must be disabled.
Return values
RETURN_SUCCESS | SMX feature is initialized.
RETURN_UNSUPPORTED | VMX not initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI SmxSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if SMX feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | SMX feature is supported.
FALSE | SMX feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI VmxInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes VMX feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the VMX feature must be enabled. If FALSE, then the VMX feature must be disabled.
Return values
RETURN_SUCCESS VMX feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI VmxSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if VMX feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | VMX feature is supported.
FALSE | VMX feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/LimitCpuIdMaxval.c File Reference

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LimitCpuIdMaxval.c File Reference

Functions

BOOLEAN EFIAPI | LimitCpuidMaxvalSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | LimitCpuidMaxvalInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

LimitCpuidMaxval Feature.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI LimitCpuidMaxvalInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes LimitCpuidMaxval feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the LimitCpuidMaxval feature must be enabled. If FALSE, then the LimitCpuidMaxval feature must be disabled.
Return values
RETURN_SUCCESS LimitCpuidMaxval feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI LimitCpuidMaxvalSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if LimitCpuidMaxval feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | LimitCpuidMaxval feature is supported.
FALSE | LimitCpuidMaxval feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c File Reference

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MachineCheck.c File Reference

Functions

BOOLEAN EFIAPI | MceSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | MceInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | McaSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | McaInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | McgCtlSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | McgCtlInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)
BOOLEAN EFIAPI | LmceSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | LmceInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Machine Check features.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI LmceInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Local machine check exception feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Local machine check exception feature must be enabled. If FALSE, then the Local machine check exception feature must be disabled.
Return values
RETURN_SUCCESS Local machine check exception feature is initialized.
BOOLEAN EFIAPI LmceSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Local machine check exception feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Local machine check exception feature is supported.
FALSE | Local machine check exception feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI McaInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Machine Check Architecture feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Machine Check Architecture feature must be enabled. If FALSE, then the Machine Check Architecture feature must be disabled.
Return values
RETURN_SUCCESS Machine Check Architecture feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI McaSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Machine Check Architecture feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Machine Check Architecture feature is supported.
FALSE | Machine Check Architecture feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI MceInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Machine Check Exception feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Machine Check Exception feature must be enabled. If FALSE, then the Machine Check Exception feature must be disabled.
Return values
RETURN_SUCCESS Machine Check Exception feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI MceSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Machine Check Exception feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Machine Check Exception feature is supported.
FALSE | Machine Check Exception feature is not supported.
Note
This service could be called by BSP/APs.
RETURN_STATUS EFIAPI McgCtlInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes IA32_MCG_CTL feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the IA32_MCG_CTL feature must be enabled. If FALSE, then the IA32_MCG_CTL feature must be disabled.
Return values
RETURN_SUCCESS IA32_MCG_CTL feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI McgCtlSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if IA32_MCG_CTL feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | IA32_MCG_CTL feature is supported.
FALSE | IA32_MCG_CTL feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/MonitorMwait.c File Reference

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MonitorMwait.c File Reference

Functions

BOOLEAN EFIAPI | MonitorMwaitSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | MonitorMwaitInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

MonitorMwait feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI MonitorMwaitInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes MONITOR/MWAIT feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the MONITOR/MWAIT feature must be enabled. If FALSE, then the MONITOR/MWAIT feature must be disabled.
Return values
RETURN_SUCCESS MONITOR/MWAIT feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI MonitorMwaitSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if MONITOR/MWAIT feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | MONITOR/MWAIT feature is supported.
FALSE | MONITOR/MWAIT feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/PendingBreak.c File Reference

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PendingBreak.c File Reference

Functions

BOOLEAN EFIAPI | PendingBreakSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | PendingBreakInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Pending Break feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI PendingBreakInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Pending Break feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Pending Break feature must be enabled. If FALSE, then the Pending Break feature must be disabled.
Return values
RETURN_SUCCESS Pending Break feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI PendingBreakSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Pending Break feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Pending Break feature is supported.
FALSE | Pending Break feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuCommonFeaturesLib
Functions
Ppin.c File Reference

Functions

BOOLEAN EFIAPI | PpinSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | PpinInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Protected Processor Inventory Number(PPIN) feature.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI PpinInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Protected Processor Inventory Number feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Protected Processor Inventory Number feature must be enabled. If FALSE, then the Protected Processor Inventory Number feature must be disabled.
Return values
RETURN_SUCCESS | Protected Processor Inventory Number feature is initialized.
RETURN_DEVICE_ERROR | Device can't change state because it has been locked.
BOOLEAN EFIAPI PpinSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Protected Processor Inventory Number feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Protected Processor Inventory Number feature is supported.
FALSE | Protected Processor Inventory Number feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/ProcTrace.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuCommonFeaturesLib
Data Structures | Enumerations | Functions
ProcTrace.c File Reference

Data Structures

struct | PROC_TRACE_PROCESSOR_DATA
struct | PROC_TRACE_DATA
struct | PROC_TRACE_TOPA_TABLE

Enumerations

enum RTIT_OUTPUT_SCHEME { RtitOutputSchemeSingleRange = 0, RtitOutputSchemeToPA }

Functions

VOID *EFIAPI | ProcTraceGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | ProcTraceSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | ProcTraceInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

Intel Processor Trace feature.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Enumeration Type Documentation

enum RTIT_OUTPUT_SCHEME

Processor trace output scheme selection.

Function Documentation

VOID* EFIAPI ProcTraceGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI ProcTraceInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes Intel Processor Trace feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the Processor Trace feature must be enabled. If FALSE, then the Processor Trace feature must be disabled.
Return values
RETURN_SUCCESS Intel Processor Trace feature is initialized.

Refer to PROC_TRACE_MEM_SIZE Table for Size Encoding

Clear bit 0 in MSR IA32_RTIT_CTL (570)

Clear MSR IA32_RTIT_STS (571h) to all zeros

Check Processor Trace output scheme: Single Range output or ToPA table

Enable the Processor Trace feature from MSR IA32_RTIT_CTL (570h)

BOOLEAN EFIAPI ProcTraceSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if Intel Processor Trace feature supported on current processor.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | Processor Trace feature is supported.
FALSE | Processor Trace feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuCommonFeaturesLib/X2Apic.c File Reference

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  • UefiCpuPkg
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  • CpuCommonFeaturesLib
Functions
X2Apic.c File Reference

Functions

VOID *EFIAPI | X2ApicGetConfigData (IN UINTN NumberOfProcessors)
BOOLEAN EFIAPI | X2ApicSupport (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData OPTIONAL)
RETURN_STATUS EFIAPI | X2ApicInitialize (IN UINTN ProcessorNumber, IN REGISTER_CPU_FEATURE_INFORMATION *CpuInfo, IN VOID *ConfigData, OPTIONAL IN BOOLEAN State)

Detailed Description

X2Apic feature.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* EFIAPI X2ApicGetConfigData ( IN UINTN NumberOfProcessors )

Prepares for the data used by CPU feature detection and initialization.

Parameters
[in] NumberOfProcessors The number of CPUs in the platform.
Returns
Pointer to a buffer of CPU related configuration data.
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI X2ApicInitialize | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID * | ConfigData,
 |  | OPTIONAL IN BOOLEAN | State
 | ) |  |

Initializes X2Apci feature to specific state.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
[in] | State | If TRUE, then the X2Apci feature must be enabled. If FALSE, then the X2Apci feature must be disabled.
Return values
RETURN_SUCCESS X2Apci feature is initialized.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI X2ApicSupport | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_CPU_FEATURE_INFORMATION * | CpuInfo,
 |  | IN VOID *ConfigData | OPTIONAL
 | ) |  |

Detects if X2Apci feature supported on current processor.

Detect if X2Apci has been already enabled.

Parameters
[in] | ProcessorNumber | The index of the CPU executing this function.
[in] | CpuInfo | A pointer to the REGISTER_CPU_FEATURE_INFORMATION structure for the CPU executing this function.
[in] | ConfigData | A pointer to the configuration buffer returned by CPU_FEATURE_GET_CONFIG_DATA. NULL if CPU_FEATURE_GET_CONFIG_DATA was not provided in RegisterCpuFeature().
Return values
TRUE | X2Apci feature is supported.
FALSE | X2Apci feature is not supported.
Note
This service could be called by BSP/APs.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib Directory Reference

  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
CpuExceptionHandlerLib Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | CpuExceptionCommon.c
file | CpuExceptionCommon.h
file | DxeCpuExceptionHandlerLib.inf
file | DxeCpuExceptionHandlerLib.uni
file | DxeException.c
file | PeiCpuException.c
file | PeiCpuExceptionHandlerLib.inf
file | PeiCpuExceptionHandlerLib.uni
file | PeiDxeSmmCpuException.c
file | SecPeiCpuException.c
file | SecPeiCpuExceptionHandlerLib.inf
file | SecPeiCpuExceptionHandlerLib.uni
file | SmmCpuExceptionHandlerLib.inf
file | SmmCpuExceptionHandlerLib.uni
file | SmmException.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32 Directory Reference

  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
  • Ia32
Ia32 Directory Reference

Files

file | ArchExceptionHandler.c
file | ArchInterruptDefs.h
file | ExceptionHandlerAsm.nasm
file | ExceptionHandlerAsm.S
file | ExceptionTssEntryAsm.nasm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
  • Ia32
Functions
ArchExceptionHandler.c File Reference

Functions

VOID | ArchUpdateIdtEntry (IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry, IN UINTN InterruptHandler)
UINTN | ArchGetIdtHandler (IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry)
VOID | ArchSaveExceptionContext (IN UINTN ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID | ArchRestoreExceptionContext (IN UINTN ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
EFI_STATUS | ArchSetupExcpetionStack (IN CPU_EXCEPTION_INIT_DATA *StackSwitchData)
VOID EFIAPI | DumpCpuContext (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID | DumpImageAndCpuContent (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)

Detailed Description

IA32 CPU Exception Handler functons.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINTN ArchGetIdtHandler ( IN IA32_IDT_GATE_DESCRIPTOR * IdtEntry )

Read IDT handler value from IDT entry.

Parameters
IdtEntry Pointer to IDT entry to be read.
VOID ArchRestoreExceptionContext | ( | IN UINTN | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
[in] | ExceptionHandlerData | Pointer to exception handler data.
VOID ArchSaveExceptionContext | ( | IN UINTN | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
[in] | ExceptionHandlerData | Pointer to exception handler data.
EFI_STATUS ArchSetupExcpetionStack ( IN CPU_EXCEPTION_INIT_DATA * StackSwitchData )

Setup separate stack for given exceptions.

Parameters
[in] StackSwitchData Pointer to data required for setuping up stack switch.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized with new stack.
EFI_INVALID_PARAMETER | StackSwitchData contains invalid content.
VOID ArchUpdateIdtEntry | ( | IN IA32_IDT_GATE_DESCRIPTOR * | IdtEntry,
 |  | IN UINTN | InterruptHandler
 | ) |  |

Return address map of exception handler template so that C code can generate exception tables.

Parameters
IdtEntry | Pointer to IDT entry to be updated.
InterruptHandler | IDT handler value.
VOID EFIAPI DumpCpuContext | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Display processor context.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Processor context to be display.
VOID DumpImageAndCpuContent | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Display CPU information.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchInterruptDefs.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
  • Ia32
Data Structures
ArchInterruptDefs.h File Reference

Data Structures

struct | EXCEPTION_HANDLER_CONTEXT
struct | CPU_STATUS_CODE_TEMPLATE
struct | RESERVED_VECTORS_DATA

Detailed Description

Ia32 arch definition for CPU Exception Handler Library.

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/X64 Directory Reference

  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
  • X64
X64 Directory Reference

Files

file | ArchExceptionHandler.c
file | ArchInterruptDefs.h
file | ExceptionHandlerAsm.nasm
file | ExceptionHandlerAsm.S
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
  • X64
Functions
ArchExceptionHandler.c File Reference

Functions

VOID | ArchUpdateIdtEntry (IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry, IN UINTN InterruptHandler)
UINTN | ArchGetIdtHandler (IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry)
VOID | ArchSaveExceptionContext (IN UINTN ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID | ArchRestoreExceptionContext (IN UINTN ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
EFI_STATUS | ArchSetupExcpetionStack (IN CPU_EXCEPTION_INIT_DATA *StackSwitchData)
VOID EFIAPI | DumpCpuContext (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID | DumpImageAndCpuContent (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)

Detailed Description

x64 CPU Exception Handler.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINTN ArchGetIdtHandler ( IN IA32_IDT_GATE_DESCRIPTOR * IdtEntry )

Read IDT handler value from IDT entry.

Parameters
IdtEntry Pointer to IDT entry to be read.
VOID ArchRestoreExceptionContext | ( | IN UINTN | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
[in] | ExceptionHandlerData | Pointer to exception handler data.
VOID ArchSaveExceptionContext | ( | IN UINTN | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
[in] | ExceptionHandlerData | Pointer to exception handler data.
EFI_STATUS ArchSetupExcpetionStack ( IN CPU_EXCEPTION_INIT_DATA * StackSwitchData )

Setup separate stack for given exceptions.

Parameters
[in] StackSwitchData Pointer to data required for setuping up stack switch.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized with new stack.
EFI_INVALID_PARAMETER | StackSwitchData contains invalid content.
VOID ArchUpdateIdtEntry | ( | IN IA32_IDT_GATE_DESCRIPTOR * | IdtEntry,
 |  | IN UINTN | InterruptHandler
 | ) |  |

Return address map of exception handler template so that C code can generate exception tables.

Parameters
IdtEntry | Pointer to IDT entry to be updated.
InterruptHandler | IDT handler value.
VOID EFIAPI DumpCpuContext | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Display CPU information.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
VOID DumpImageAndCpuContent | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Display CPU information.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchInterruptDefs.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
  • X64
Data Structures
ArchInterruptDefs.h File Reference

Data Structures

struct | EXCEPTION_HANDLER_CONTEXT
struct | CPU_STATUS_CODE_TEMPLATE
struct | RESERVED_VECTORS_DATA

Detailed Description

X64 arch definition for CPU Exception Handler Library.

Copyright (c) 2013, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
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  • CpuExceptionHandlerLib
Functions | Variables
CpuExceptionCommon.c File Reference

Functions

CONST CHAR8 * | GetExceptionNameStr (IN EFI_EXCEPTION_TYPE ExceptionType)
VOID EFIAPI | InternalPrintMessage (IN CONST CHAR8 *Format,...)
VOID | DumpModuleImageInfo (IN UINTN CurrentEip)
EFI_STATUS | ReadAndVerifyVectorInfo (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, OUT RESERVED_VECTORS_DATA *ReservedVector, IN UINTN VectorCount)

Variables

CONST UINT32 | mErrorCodeFlag = 0x00027d00
CONST CHAR8 | mExceptionReservedStr [] = "Reserved"
CONST CHAR8 * | mExceptionNameStr []

Detailed Description

CPU Exception Handler Library common functions.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID DumpModuleImageInfo ( IN UINTN CurrentEip )

Find and display image base address and return image base and its entry point.

Parameters
CurrentEip Current instruction pointer.
CONST CHAR8* GetExceptionNameStr ( IN EFI_EXCEPTION_TYPE ExceptionType )

Get ASCII format string exception name by exception type.

Parameters
ExceptionType Exception type.
Returns
ASCII format string exception name.
VOID EFIAPI InternalPrintMessage | ( | IN CONST CHAR8 * | Format,
 |  |  | ...
 | ) |  |

Prints a message to the serial port.

Parameters
Format Format string for the message to print.
... Variable argument list whose contents are accessed based on the format string specified by Format.
EFI_STATUS ReadAndVerifyVectorInfo | ( | IN EFI_VECTOR_HANDOFF_INFO * | VectorInfo,
 |  | OUT RESERVED_VECTORS_DATA * | ReservedVector,
 |  | IN UINTN | VectorCount
 | ) |  |

Read and save reserved vector information

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[out] | ReservedVector | Pointer to reserved vector data buffer.
[in] | VectorCount | Vector number to be updated.
Returns
EFI_SUCCESS Read and save vector info successfully.
Return values
EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.

Variable Documentation

CONST CHAR8* mExceptionNameStr[]
Initial value:
= {
"#DE - Divide Error",
"#DB - Debug",
"NMI Interrupt",
"#BP - Breakpoint",
"#OF - Overflow",
"#BR - BOUND Range Exceeded",
"#UD - Invalid Opcode",
"#NM - Device Not Available",
"#DF - Double Fault",
"Coprocessor Segment Overrun",
"#TS - Invalid TSS",
"#NP - Segment Not Present",
"#SS - Stack Fault Fault",
"#GP - General Protection",
"#PF - Page-Fault",
"Reserved",
"#MF - x87 FPU Floating-Point Error",
"#AC - Alignment Check",
"#MC - Machine-Check",
"#XM - SIMD floating-point",
"#VE - Virtualization"
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
Data Structures | Functions | Variables
CpuExceptionCommon.h File Reference

Data Structures

struct | EXCEPTION_HANDLER_TEMPLATE_MAP
struct | EXCEPTION_HANDLER_DATA

Functions

VOID EFIAPI | AsmGetTemplateAddressMap (OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap)
VOID | ArchUpdateIdtEntry (IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry, IN UINTN InterruptHandler)
UINTN | ArchGetIdtHandler (IN IA32_IDT_GATE_DESCRIPTOR *IdtEntry)
VOID EFIAPI | InternalPrintMessage (IN CONST CHAR8 *Format,...)
VOID | DumpModuleImageInfo (IN UINTN CurrentEip)
VOID | DumpImageAndCpuContent (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
EFI_STATUS | InitializeCpuExceptionHandlersWorker (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
EFI_STATUS | RegisterCpuInterruptHandlerWorker (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID | UpdateIdtTable (IN IA32_IDT_GATE_DESCRIPTOR *IdtTable, IN EXCEPTION_HANDLER_TEMPLATE_MAP *TemplateMap, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID | ArchSaveExceptionContext (IN UINTN ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID | ArchRestoreExceptionContext (IN UINTN ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID EFIAPI | AsmVectorNumFixup (IN VOID *NewVectorAddr, IN UINT8 VectorNum, IN VOID *OldVectorAddr)
EFI_STATUS | ReadAndVerifyVectorInfo (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo, OUT RESERVED_VECTORS_DATA *ReservedVector, IN UINTN VectorCount)
CONST CHAR8 * | GetExceptionNameStr (IN EFI_EXCEPTION_TYPE ExceptionType)
VOID | CommonExceptionHandlerWorker (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
EFI_STATUS | ArchSetupExcpetionStack (IN CPU_EXCEPTION_INIT_DATA *StackSwitchData)
VOID EFIAPI | AsmGetTssTemplateMap (OUT EXCEPTION_HANDLER_TEMPLATE_MAP *AddressMap)

Variables

CONST UINT32 | mErrorCodeFlag
CONST UINTN | mDoFarReturnFlag

Detailed Description

Common header file for CPU Exception Handler Library.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINTN ArchGetIdtHandler ( IN IA32_IDT_GATE_DESCRIPTOR * IdtEntry )

Read IDT handler value from IDT entry.

Parameters
IdtEntry Pointer to IDT entry to be read.
VOID ArchRestoreExceptionContext | ( | IN UINTN | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Restore CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
[in] | ExceptionHandlerData | Pointer to exception handler data.
VOID ArchSaveExceptionContext | ( | IN UINTN | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Save CPU exception context when handling EFI_VECTOR_HANDOFF_HOOK_AFTER case.

Parameters
[in] | ExceptionType | Exception type.
[in] | SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
[in] | ExceptionHandlerData | Pointer to exception handler data.
EFI_STATUS ArchSetupExcpetionStack ( IN CPU_EXCEPTION_INIT_DATA * StackSwitchData )

Setup separate stack for specific exceptions.

Parameters
[in] StackSwitchData Pointer to data required for setuping up stack switch.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized with new stack.
EFI_INVALID_PARAMETER | StackSwitchData contains invalid content.

Setup separate stack for given exceptions.

Parameters
[in] StackSwitchData Pointer to data required for setuping up stack switch.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized with new stack.
EFI_INVALID_PARAMETER | StackSwitchData contains invalid content.
VOID ArchUpdateIdtEntry | ( | IN IA32_IDT_GATE_DESCRIPTOR * | IdtEntry,
 |  | IN UINTN | InterruptHandler
 | ) |  |

Return address map of exception handler template so that C code can generate exception tables.

Parameters
IdtEntry | Pointer to IDT entry to be updated.
InterruptHandler | IDT handler value.
VOID EFIAPI AsmGetTemplateAddressMap ( OUT EXCEPTION_HANDLER_TEMPLATE_MAP * AddressMap )

Return address map of exception handler template so that C code can generate exception tables.

Parameters
AddressMap Pointer to a buffer where the address map is returned.
VOID EFIAPI AsmGetTssTemplateMap ( OUT EXCEPTION_HANDLER_TEMPLATE_MAP * AddressMap )

Return address map of exception handler template so that C code can generate exception tables. The template is only for exceptions using task gate instead of interrupt gate.

Parameters
AddressMap Pointer to a buffer where the address map is returned.
VOID EFIAPI AsmVectorNumFixup | ( | IN VOID * | NewVectorAddr,
 |  | IN UINT8 | VectorNum,
 |  | IN VOID * | OldVectorAddr
 | ) |  |

Fix up the vector number and function address in the vector code.

Parameters
[in] | NewVectorAddr | New vector handler address.
[in] | VectorNum | Index of vector.
[in] | OldVectorAddr | Old vector handler address.
VOID CommonExceptionHandlerWorker | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Internal worker function for common exception handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
ExceptionHandlerData | Pointer to exception handler data.
VOID DumpImageAndCpuContent | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Display CPU information.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
VOID DumpModuleImageInfo ( IN UINTN CurrentEip )

Find and display image base address and return image base and its entry point.

Parameters
CurrentEip Current instruction pointer.
CONST CHAR8* GetExceptionNameStr ( IN EFI_EXCEPTION_TYPE ExceptionType )

Get ASCII format string exception name by exception type.

Parameters
ExceptionType Exception type.
Returns
ASCII format string exception name.
EFI_STATUS InitializeCpuExceptionHandlersWorker | ( | IN EFI_VECTOR_HANDOFF_INFO *VectorInfo | OPTIONAL,
 |  | IN OUT EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Internal worker function to initialize exception handler.

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[in,out] | ExceptionHandlerData | Pointer to exception handler data.
Return values
EFI_SUCCESS | CPU Exception Entries have been successfully initialized with default exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
VOID EFIAPI InternalPrintMessage | ( | IN CONST CHAR8 * | Format,
 |  |  | ...
 | ) |  |

Prints a message to the serial port.

Parameters
Format Format string for the message to print.
... Variable argument list whose contents are accessed based on the format string specified by Format.
EFI_STATUS ReadAndVerifyVectorInfo | ( | IN EFI_VECTOR_HANDOFF_INFO * | VectorInfo,
 |  | OUT RESERVED_VECTORS_DATA * | ReservedVector,
 |  | IN UINTN | VectorCount
 | ) |  |

Read and save reserved vector information

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[out] | ReservedVector | Pointer to reserved vector data buffer.
[in] | VectorCount | Vector number to be updated.
Returns
EFI_SUCCESS Read and save vector info successfully.
Return values
EFI_INVALID_PARAMETER VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_STATUS RegisterCpuInterruptHandlerWorker | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Registers a function to be called from the processor interrupt handler.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled
[in] | ExceptionHandlerData | Pointer to exception handler data.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported, or this function is not supported.
VOID UpdateIdtTable | ( | IN IA32_IDT_GATE_DESCRIPTOR * | IdtTable,
 |  | IN EXCEPTION_HANDLER_TEMPLATE_MAP * | TemplateMap,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Internal worker function to update IDT entries accordling to vector attributes.

Parameters
[in] | IdtTable | Pointer to IDT table.
[in] | TemplateMap | Pointer to a buffer where the address map is returned.
[in] | ExceptionHandlerData | Pointer to exception handler data.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
DxeCpuExceptionHandlerLib.uni File Reference

Detailed Description

CPU Exception Handler library instance for DXE modules.

CPU Exception Handler library instance for DXE modules.

Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeException.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
Functions | Variables
DxeException.c File Reference

Functions

VOID EFIAPI | CommonExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | InitializeCpuInterruptHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | RegisterCpuInterruptHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlersEx (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL)

Variables

CONST UINTN | mDoFarReturnFlag = 0
RESERVED_VECTORS_DATA | mReservedVectorsData [CPU_EXCEPTION_NUM]
EFI_CPU_INTERRUPT_HANDLER | mExternalInterruptHandlerTable [CPU_EXCEPTION_NUM]
UINTN | mEnabledInterruptNum = 0
EXCEPTION_HANDLER_DATA | mExceptionHandlerData
UINT8 | mNewStack [CPU_STACK_SWITCH_EXCEPTION_NUMBER *CPU_KNOWN_GOOD_STACK_SIZE]
UINT8 | mNewGdt [CPU_TSS_GDT_SIZE]

Detailed Description

CPU exception handler library implemenation for DXE modules.

Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI CommonExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Common exception handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU exceptions entries and provides the default exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | CPU Exception Entries have been successfully initialized with default exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx | ( | IN EFI_VECTOR_HANDOFF_INFO *VectorInfo | OPTIONAL,
 |  | IN CPU_EXCEPTION_INIT_DATA *InitData | OPTIONAL
 | ) |  |

Initializes CPU exceptions entries and setup stack switch for given exceptions.

This method will call InitializeCpuExceptionHandlers() to setup default exception handlers unless indicated not to do it explicitly.

If InitData is passed with NULL, this method will use the resource reserved by global variables to initialize it; Otherwise it will use data in InitData to setup stack switch. This is for the different use cases in DxeCore and Cpu MP exception initialization.

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[in] | InitData | Pointer to data required to setup stack switch for given exceptions.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized.
EFI_INVALID_PARAMETER | VectorInfo or InitData contains invalid content.
EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | All CPU interrupt/exception entries have been successfully initialized with default interrupt/exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI RegisterCpuInterruptHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Registers a function to be called from the processor interrupt handler.

This function registers and enables the handler specified by InterruptHandler for a processor interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the handler for the processor interrupt or exception type specified by InterruptType is uninstalled. The installed handler is called once for each processor interrupt or exception. NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported, or this function is not supported.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuException.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
Data Structures | Functions | Variables
PeiCpuException.c File Reference

Data Structures

struct EXCEPTION0_STUB_HEADER

Functions

EXCEPTION_HANDLER_DATA * GetExceptionHandlerData (VOID)
VOID | SetExceptionHandlerData (IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID EFIAPI | CommonExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | InitializeCpuInterruptHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | RegisterCpuInterruptHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlersEx (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL)

Variables

CONST UINTN mDoFarReturnFlag = 0

Detailed Description

CPU exception handler library implementation for PEIM module.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI CommonExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Common exception handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
EXCEPTION_HANDLER_DATA* GetExceptionHandlerData ( VOID )

Get exception handler data pointer from IDT[0].

The exception #0 stub header is duplicated in an allocated pool with extra 4-byte/8-byte to store the exception handler data. The new allocated memory layout follows structure EXCEPTION0_STUB_HEADER. The code assumes that all processors uses the same exception handler for #0 exception.

Returns
pointer to exception handler data.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU exceptions entries and provides the default exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly. Note: Before invoking this API, caller must allocate memory for IDT table and load IDTR by AsmWriteIdtr().

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | CPU Exception Entries have been successfully initialized with default exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx | ( | IN EFI_VECTOR_HANDOFF_INFO *VectorInfo | OPTIONAL,
 |  | IN CPU_EXCEPTION_INIT_DATA *InitData | OPTIONAL
 | ) |  |

Initializes all CPU exceptions entries with optional extra initializations.

By default, this method should include all functionalities implemented by InitializeCpuExceptionHandlers(), plus extra initialization works, if any. This could be done by calling InitializeCpuExceptionHandlers() directly in this method besides the extra works.

InitData is optional and its use and content are processor arch dependent. The typical usage of it is to convey resources which have to be reserved elsewhere and are necessary for the extra initializations of exception.

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[in] | InitData | Pointer to data optional for extra initializations of exception.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized.
EFI_INVALID_PARAMETER | VectorInfo or InitData contains invalid content.
EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | All CPU interrupt/exception entries have been successfully initialized with default interrupt/exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI RegisterCpuInterruptHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Registers a function to be called from the processor interrupt handler.

This function registers and enables the handler specified by InterruptHandler for a processor interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the handler for the processor interrupt or exception type specified by InterruptType is uninstalled. The installed handler is called once for each processor interrupt or exception. NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported, or this function is not supported.
VOID SetExceptionHandlerData ( IN EXCEPTION_HANDLER_DATA * ExceptionHandlerData )

Set exception handler data pointer to IDT[0].

The exception #0 stub header is duplicated in an allocated pool with extra 4-byte/8-byte to store the exception handler data. The new allocated memory layout follows structure EXCEPTION0_STUB_HEADER. The code assumes that all processors uses the same exception handler for #0 exception.

Parameters
ExceptionHandlerData pointer to exception handler data.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
PeiCpuExceptionHandlerLib.uni File Reference

Detailed Description

CPU Exception Handler library instance for PEI module.

CPU Exception Handler library instance for PEI module.

Copyright (c) 2016, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
Functions
PeiDxeSmmCpuException.c File Reference

Functions

VOID | CommonExceptionHandlerWorker (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
VOID | UpdateIdtTable (IN IA32_IDT_GATE_DESCRIPTOR *IdtTable, IN EXCEPTION_HANDLER_TEMPLATE_MAP *TemplateMap, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
EFI_STATUS | InitializeCpuExceptionHandlersWorker (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN OUT EXCEPTION_HANDLER_DATA *ExceptionHandlerData)
EFI_STATUS | RegisterCpuInterruptHandlerWorker (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler, IN EXCEPTION_HANDLER_DATA *ExceptionHandlerData)

Detailed Description

CPU Exception Library provides PEI/DXE/SMM CPU common exception handler.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID CommonExceptionHandlerWorker | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Internal worker function for common exception handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
ExceptionHandlerData | Pointer to exception handler data.
EFI_STATUS InitializeCpuExceptionHandlersWorker | ( | IN EFI_VECTOR_HANDOFF_INFO *VectorInfo | OPTIONAL,
 |  | IN OUT EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Internal worker function to initialize exception handler.

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[in,out] | ExceptionHandlerData | Pointer to exception handler data.
Return values
EFI_SUCCESS | CPU Exception Entries have been successfully initialized with default exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS RegisterCpuInterruptHandlerWorker | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Registers a function to be called from the processor interrupt handler.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled
[in] | ExceptionHandlerData | Pointer to exception handler data.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported, or this function is not supported.
VOID UpdateIdtTable | ( | IN IA32_IDT_GATE_DESCRIPTOR * | IdtTable,
 |  | IN EXCEPTION_HANDLER_TEMPLATE_MAP * | TemplateMap,
 |  | IN EXCEPTION_HANDLER_DATA * | ExceptionHandlerData
 | ) |  |

Internal worker function to update IDT entries accordling to vector attributes.

Parameters
[in] | IdtTable | Pointer to IDT table.
[in] | TemplateMap | Pointer to a buffer where the address map is returned.
[in] | ExceptionHandlerData | Pointer to exception handler data.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
Functions | Variables
SecPeiCpuException.c File Reference

Functions

VOID EFIAPI | CommonExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | InitializeCpuInterruptHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | RegisterCpuInterruptHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlersEx (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL)

Variables

CONST UINTN mDoFarReturnFlag = 0

Detailed Description

CPU exception handler library implemenation for SEC/PEIM modules.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI CommonExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Common exception handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU exceptions entries and provides the default exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly. Note: Before invoking this API, caller must allocate memory for IDT table and load IDTR by AsmWriteIdtr().

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | CPU Exception Entries have been successfully initialized with default exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx | ( | IN EFI_VECTOR_HANDOFF_INFO *VectorInfo | OPTIONAL,
 |  | IN CPU_EXCEPTION_INIT_DATA *InitData | OPTIONAL
 | ) |  |

Initializes all CPU exceptions entries with optional extra initializations.

By default, this method should include all functionalities implemented by InitializeCpuExceptionHandlers(), plus extra initialization works, if any. This could be done by calling InitializeCpuExceptionHandlers() directly in this method besides the extra works.

InitData is optional and its use and content are processor arch dependent. The typical usage of it is to convey resources which have to be reserved elsewhere and are necessary for the extra initializations of exception.

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[in] | InitData | Pointer to data optional for extra initializations of exception.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized.
EFI_INVALID_PARAMETER | VectorInfo or InitData contains invalid content.
EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | All CPU interrupt/exception entries have been successfully initialized with default interrupt/exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI RegisterCpuInterruptHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Registers a function to be called from the processor interrupt handler.

This function registers and enables the handler specified by InterruptHandler for a processor interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the handler for the processor interrupt or exception type specified by InterruptType is uninstalled. The installed handler is called once for each processor interrupt or exception. NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported, or this function is not supported.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
SecPeiCpuExceptionHandlerLib.uni File Reference

Detailed Description

CPU Exception Handler library instance for SEC/PEI modules.

CPU Exception Handler library instance for SEC/PEI modules.

Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
SmmCpuExceptionHandlerLib.uni File Reference

Detailed Description

CPU Exception Handler library instance for SMM modules.

CPU Exception Handler library instance for SMM modules.

Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmException.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • CpuExceptionHandlerLib
Functions | Variables
SmmException.c File Reference

Functions

VOID EFIAPI | CommonExceptionHandler (IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_SYSTEM_CONTEXT SystemContext)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | InitializeCpuInterruptHandlers (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL)
EFI_STATUS EFIAPI | RegisterCpuInterruptHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS EFIAPI | InitializeCpuExceptionHandlersEx (IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL, IN CPU_EXCEPTION_INIT_DATA *InitData OPTIONAL)

Variables

CONST UINTN | mDoFarReturnFlag = 1
SPIN_LOCK | mDisplayMessageSpinLock
RESERVED_VECTORS_DATA | mReservedVectorsData [CPU_EXCEPTION_NUM]
EFI_CPU_INTERRUPT_HANDLER | mExternalInterruptHandlerTable [CPU_EXCEPTION_NUM]
EXCEPTION_HANDLER_DATA | mExceptionHandlerData

Detailed Description

CPU exception handler library implemenation for SMM modules.

Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI CommonExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Common exception handler.

Parameters
ExceptionType | Exception type.
SystemContext | Pointer to EFI_SYSTEM_CONTEXT.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU exceptions entries and provides the default exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | CPU Exception Entries have been successfully initialized with default exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI InitializeCpuExceptionHandlersEx | ( | IN EFI_VECTOR_HANDOFF_INFO *VectorInfo | OPTIONAL,
 |  | IN CPU_EXCEPTION_INIT_DATA *InitData | OPTIONAL
 | ) |  |

Initializes all CPU exceptions entries with optional extra initializations.

By default, this method should include all functionalities implemented by InitializeCpuExceptionHandlers(), plus extra initialization works, if any. This could be done by calling InitializeCpuExceptionHandlers() directly in this method besides the extra works.

InitData is optional and its use and content are processor arch dependent. The typical usage of it is to convey resources which have to be reserved elsewhere and are necessary for the extra initializations of exception.

Parameters
[in] | VectorInfo | Pointer to reserved vector list.
[in] | InitData | Pointer to data optional for extra initializations of exception.
Return values
EFI_SUCCESS | The exceptions have been successfully initialized.
EFI_INVALID_PARAMETER | VectorInfo or InitData contains invalid content.
EFI_STATUS EFIAPI InitializeCpuInterruptHandlers ( IN EFI_VECTOR_HANDOFF_INFO *VectorInfo OPTIONAL )

Initializes all CPU interrupt/exceptions entries and provides the default interrupt/exception handlers.

Caller should try to get an array of interrupt and/or exception vectors that are in use and need to persist by EFI_VECTOR_HANDOFF_INFO defined in PI 1.3 specification. If caller cannot get reserved vector list or it does not exists, set VectorInfo to NULL. If VectorInfo is not NULL, the exception vectors will be initialized per vector attribute accordingly.

Parameters
[in] VectorInfo Pointer to reserved vector list.
Return values
EFI_SUCCESS | All CPU interrupt/exception entries have been successfully initialized with default interrupt/exception handlers.
EFI_INVALID_PARAMETER | VectorInfo includes the invalid content if VectorInfo is not NULL.
EFI_UNSUPPORTED | This function is not supported.
EFI_STATUS EFIAPI RegisterCpuInterruptHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Registers a function to be called from the processor interrupt handler.

This function registers and enables the handler specified by InterruptHandler for a processor interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the handler for the processor interrupt or exception type specified by InterruptType is uninstalled. The installed handler is called once for each processor interrupt or exception. NOTE: This function should be invoked after InitializeCpuExceptionHandlers() or InitializeCpuInterruptHandlers() invoked, otherwise EFI_UNSUPPORTED returned.

Parameters
[in] | InterruptType | Defines which interrupt or exception to hook.
[in] | InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported, or this function is not supported.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib Directory Reference

  • UefiCpuPkg
  • Library
  • MpInitLib
MpInitLib Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | DxeMpInitLib.inf
file | DxeMpInitLib.uni
file | DxeMpLib.c
file | Microcode.c
file | MpLib.c
file | MpLib.h
file | PeiMpInitLib.inf
file | PeiMpInitLib.uni
file | PeiMpLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
DxeMpInitLib.uni File Reference

Detailed Description

MP Initialize Library instance for DXE driver.

MP Initialize Library instance for DXE driver.

Copyright (c) 2016, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/DxeMpLib.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
Functions | Variables
DxeMpLib.c File Reference

Functions

UINT32 | ReadLocalApicReg (IN UINTN MmioOffset)
VOID | WriteLocalApicReg (IN UINTN MmioOffset, IN UINT32 Value)
VOID EnableDebugAgent (VOID)
CPU_MP_DATA * GetCpuMpData (VOID)
VOID | SaveCpuMpData (IN CPU_MP_DATA *CpuMpData)
UINTN | GetWakeupBuffer (IN UINTN WakeupBufferSize)
UINTN | GetModeTransitionBuffer (IN UINTN BufferSize)
VOID CheckAndUpdateApsStatus (VOID)
VOID EFIAPI | CheckApsStatus (IN EFI_EVENT Event, IN VOID *Context)
UINT16 | GetProtectedModeCS (VOID)
VOID EFIAPI | RelocateApLoop (IN OUT VOID *Buffer)
VOID EFIAPI | MpInitChangeApLoopCallback (IN EFI_EVENT Event, IN VOID *Context)
VOID | InitMpGlobalData (IN CPU_MP_DATA *CpuMpData)
EFI_STATUS EFIAPI | MpInitLibStartupAllAPs (IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibStartupThisAP (IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibSwitchBSP (IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | MpInitLibEnableDisableAP (IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)

Variables

CPU_MP_DATA * | mCpuMpData = NULL
EFI_EVENT | mCheckAllApsEvent = NULL
EFI_EVENT | mMpInitExitBootServicesEvent = NULL
EFI_EVENT | mLegacyBootEvent = NULL
volatile BOOLEAN | mStopCheckAllApsStatus = TRUE
VOID * | mReservedApLoopFunc = NULL
UINTN | mReservedTopOfApStack
volatile UINT32 | mNumberToFinish = 0
EFI_PHYSICAL_ADDRESS | mStartAddress = 0

Detailed Description

MP initialize support functions for DXE phase.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID CheckAndUpdateApsStatus ( VOID )

Checks APs status and updates APs status if needed.

VOID EFIAPI CheckApsStatus | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Checks APs' status periodically.

This function is triggered by timer periodically to check the state of APs for StartupAllAPs() and StartupThisAP() executed in non-blocking mode.

Parameters
[in] | Event | Event triggered.
[in] | Context | Parameter passed with the event.
VOID EnableDebugAgent ( VOID )

Enable Debug Agent to support source debugging on AP function.

CPU_MP_DATA* GetCpuMpData ( VOID )

Get the pointer to CPU MP Data structure.

Returns
The pointer to CPU MP Data structure.
UINTN GetModeTransitionBuffer ( IN UINTN BufferSize )

Get available EfiBootServicesCode memory below 4GB by specified size.

This buffer is required to safely transfer AP from real address mode to protected mode or long mode, due to the fact that the buffer returned by GetWakeupBuffer() may be marked as non-executable.

Parameters
[in] BufferSize Wakeup transition buffer size.
Return values
other | Return wakeup transition buffer address below 4GB.
0 | Cannot find free memory below 4GB.
UINT16 GetProtectedModeCS ( VOID )

Get Protected mode code segment from current GDT table.

Returns
Protected mode code segment value.
UINTN GetWakeupBuffer ( IN UINTN WakeupBufferSize )

Get available system memory below 1MB by specified size.

Parameters
[in] WakeupBufferSize Wakeup buffer size required
Return values
other | Return wakeup buffer address below 1MB.
-1 | Cannot find free memory below 1MB.
VOID InitMpGlobalData ( IN CPU_MP_DATA * CpuMpData )

Initialize global data for MP support.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure.
VOID EFIAPI MpInitChangeApLoopCallback | ( | IN EFI_EVENT | Event,
 |  | IN VOID * | Context
 | ) |  |

Callback function for ExitBootServices.

Parameters
[in] | Event | Event whose notification function is being invoked.
[in] | Context | The pointer to the notification function's context, which is implementation-dependent.
EFI_STATUS EFIAPI MpInitLibEnableDisableAP | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibStartupAllAPs | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on all the enabled APs, and go on executing immediately. If all return from Procedure, or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by MpInitLibStartupAllAPs() or MPInitLibStartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If NULL, this parameter is ignored. Otherwise, if all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs. The buffer is allocated by MP Initialization library, and it's the caller's responsibility to free the buffer with FreePool() service. In blocking mode, it is ready for consumption when the call returns. In non-blocking mode, it is ready when WaitEvent is signaled. The list of failed CPU is terminated by END_OF_CPU_LIST.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_UNSUPPORTED | WaitEvent is not NULL if non-blocking mode is not supported.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI MpInitLibStartupThisAP | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function.

Parameters
[in] | Procedure | A pointer to the function to be run on the designated AP of the system. See type EFI_AP_PROCEDURE.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until this AP finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on this AP, and go on executing immediately. If this AP return from Procedure or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for this AP to finish this Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before this AP returns from Procedure, then Procedure on the AP is terminated. The AP is available for next function assigned by MpInitLibStartupAllAPs() or MpInitLibStartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure on the specified AP.
[out] | Finished | If NULL, this parameter is ignored. In blocking mode, this parameter is ignored. In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE. The caller can determine if the AP returned from Procedure by evaluating this value.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_SUCCESS | In non-blocking mode, the function has been dispatched to specified AP.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_UNSUPPORTED | WaitEvent is not NULL if non-blocking mode is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI MpInitLibSwitchBSP | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
UINT32 ReadLocalApicReg ( IN UINTN MmioOffset )

Read from a local APIC register.

This function reads from a local APIC register either in xAPIC or x2APIC mode. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, so this function only performs 32-bit read.

Parameters
MmioOffset The MMIO offset of the local APIC register in xAPIC mode. It must be 16-byte aligned.
Returns
32-bit Value read from the register.
VOID EFIAPI RelocateApLoop ( IN OUT VOID * Buffer )

Do sync on APs.

Parameters
[in,out] Buffer Pointer to private data buffer.
VOID SaveCpuMpData ( IN CPU_MP_DATA * CpuMpData )

Save the pointer to CPU MP Data structure.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure will be saved.
VOID WriteLocalApicReg | ( | IN UINTN | MmioOffset,
 |  | IN UINT32 | Value
 | ) |  |

Write to a local APIC register.

This function writes to a local APIC register either in xAPIC or x2APIC mode. It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be accessed using multiple 32-bit loads or stores, so this function only performs 32-bit write.

if the register index is invalid or unsupported in current APIC mode, then ASSERT.

Parameters
MmioOffset | The MMIO offset of the local APIC register in xAPIC mode. It must be 16-byte aligned.
Value | Value to be written to the register.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/Microcode.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
Functions
Microcode.c File Reference

Functions

UINT32 | GetCurrentMicrocodeSignature (VOID)
VOID | MicrocodeDetect (IN CPU_MP_DATA *CpuMpData, IN BOOLEAN IsBspCallIn)

Detailed Description

Implementation of loading microcode on processors.

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT32 GetCurrentMicrocodeSignature ( VOID )

Get microcode update signature of currently loaded microcode update.

Returns
Microcode signature.
VOID MicrocodeDetect | ( | IN CPU_MP_DATA * | CpuMpData,
 |  | IN BOOLEAN | IsBspCallIn
 | ) |  |

Detect whether specified processor can find matching microcode patch and load it.

Parameters
[in] | CpuMpData | The pointer to CPU MP Data structure.
[in] | IsBspCallIn | Indicate whether the caller is BSP or not.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/MpLib.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
Functions | Variables
MpLib.c File Reference

Functions

VOID | InitializeMtrr ()
BOOLEAN | IsBspExecuteDisableEnabled (VOID)
VOID EFIAPI | FutureBSPProc (IN VOID *Buffer)
CPU_STATE | GetApState (IN CPU_AP_DATA *CpuData)
VOID | SetApState (IN CPU_AP_DATA *CpuData, IN CPU_STATE State)
VOID | SaveLocalApicTimerSetting (IN CPU_MP_DATA *CpuMpData)
VOID | SyncLocalApicTimerSetting (IN CPU_MP_DATA *CpuMpData)
VOID | SaveVolatileRegisters (OUT CPU_VOLATILE_REGISTERS *VolatileRegisters)
VOID | RestoreVolatileRegisters (IN CPU_VOLATILE_REGISTERS *VolatileRegisters, IN BOOLEAN IsRestoreDr)
BOOLEAN | IsMwaitSupport (VOID)
UINT8 | GetApLoopMode (OUT UINT32 *MonitorFilterSize)
VOID | SortApicId (IN CPU_MP_DATA *CpuMpData)
VOID EFIAPI | ApFuncEnableX2Apic (IN OUT VOID *Buffer)
VOID EFIAPI | ApInitializeSync (IN OUT VOID *Buffer)
EFI_STATUS | GetProcessorNumber (IN CPU_MP_DATA *CpuMpData, OUT UINTN *ProcessorNumber)
UINTN | CollectProcessorCount (IN CPU_MP_DATA *CpuMpData)
VOID | InitializeApData (IN OUT CPU_MP_DATA *CpuMpData, IN UINTN ProcessorNumber, IN UINT32 BistData, IN UINT64 ApTopOfStack)
VOID EFIAPI | ApWakeupFunction (IN MP_CPU_EXCHANGE_INFO *ExchangeInfo, IN UINTN ApIndex)
VOID | WaitApWakeup (IN volatile UINT32 *ApStartupSignalBuffer)
VOID | FillExchangeInfoData (IN CPU_MP_DATA *CpuMpData)
VOID | TimedWaitForApFinish (IN CPU_MP_DATA *CpuMpData, IN UINT32 FinishedApLimit, IN UINT32 TimeLimit)
VOID | BackupAndPrepareWakeupBuffer (IN CPU_MP_DATA *CpuMpData)
VOID | RestoreWakeupBuffer (IN CPU_MP_DATA *CpuMpData)
VOID | AllocateResetVector (IN OUT CPU_MP_DATA *CpuMpData)
VOID | FreeResetVector (IN CPU_MP_DATA *CpuMpData)
VOID | WakeUpAP (IN CPU_MP_DATA *CpuMpData, IN BOOLEAN Broadcast, IN UINTN ProcessorNumber, IN EFI_AP_PROCEDURE Procedure, OPTIONAL IN VOID *ProcedureArgument, OPTIONAL IN BOOLEAN WakeUpDisabledAps)
UINT64 | CalculateTimeout (IN UINTN TimeoutInMicroseconds, OUT UINT64 *CurrentTime)
BOOLEAN | CheckTimeout (IN OUT UINT64 *PreviousTime, IN UINT64 *TotalTime, IN UINT64 Timeout)
VOID | ResetProcessorToIdleState (IN UINTN ProcessorNumber)
EFI_STATUS | GetNextWaitingProcessorNumber (OUT UINTN *NextProcessorNumber)
EFI_STATUS | CheckThisAP (IN UINTN ProcessorNumber)
EFI_STATUS CheckAllAPs (VOID)
EFI_STATUS EFIAPI | MpInitLibInitialize (VOID)
EFI_STATUS EFIAPI | MpInitLibGetProcessorInfo (IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL)
EFI_STATUS | SwitchBSPWorker (IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS | EnableDisableApWorker (IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibWhoAmI (OUT UINTN *ProcessorNumber)
EFI_STATUS EFIAPI | MpInitLibGetNumberOfProcessors (OUT UINTN *NumberOfProcessors, OPTIONAL OUT UINTN *NumberOfEnabledProcessors OPTIONAL)
EFI_STATUS | StartupAllAPsWorker (IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS | StartupThisAPWorker (IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
CPU_MP_DATA * GetCpuMpDataFromGuidedHob (VOID)

Variables

EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID

Detailed Description

CPU MP Initialize Library common functions.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID AllocateResetVector ( IN OUT CPU_MP_DATA * CpuMpData )

Allocate reset vector buffer.

Parameters
[in,out] CpuMpData The pointer to CPU MP Data structure.
VOID EFIAPI ApFuncEnableX2Apic ( IN OUT VOID * Buffer )

Enable x2APIC mode on APs.

Parameters
[in,out] Buffer Pointer to private data buffer.
VOID EFIAPI ApInitializeSync ( IN OUT VOID * Buffer )

Do sync on APs.

Parameters
[in,out] Buffer Pointer to private data buffer.
VOID EFIAPI ApWakeupFunction | ( | IN MP_CPU_EXCHANGE_INFO * | ExchangeInfo,
 |  | IN UINTN | ApIndex
 | ) |  |

This function will be called from AP reset code if BSP uses WakeUpAP.

Parameters
[in] | ExchangeInfo | Pointer to the MP exchange info buffer
[in] | ApIndex | Number of current executing AP
VOID BackupAndPrepareWakeupBuffer ( IN CPU_MP_DATA * CpuMpData )

Get available system memory below 1MB by specified size.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure.
UINT64 CalculateTimeout | ( | IN UINTN | TimeoutInMicroseconds,
 |  | OUT UINT64 * | CurrentTime
 | ) |  |

Calculate timeout value and return the current performance counter value.

Calculate the number of performance counter ticks required for a timeout. If TimeoutInMicroseconds is 0, return value is also 0, which is recognized as infinity.

Parameters
[in] | TimeoutInMicroseconds | Timeout value in microseconds.
[out] | CurrentTime | Returns the current value of the performance counter.
Returns
Expected time stamp counter for timeout. If TimeoutInMicroseconds is 0, return value is also 0, which is recognized as infinity.
EFI_STATUS CheckAllAPs ( VOID )

Checks status of all APs.

This function checks whether all APs have finished task assigned by StartupAllAPs(), and whether timeout expires.

Return values
EFI_SUCCESS | All APs have finished task assigned by StartupAllAPs().
EFI_TIMEOUT | The timeout expires.
EFI_NOT_READY | APs have not finished task and timeout has not expired.
EFI_STATUS CheckThisAP ( IN UINTN ProcessorNumber )

Checks status of specified AP.

This function checks whether the specified AP has finished the task assigned by StartupThisAP(), and whether timeout expires.

Parameters
[in] ProcessorNumber The handle number of processor.
Return values
EFI_SUCCESS | Specified AP has finished task assigned by StartupThisAPs().
EFI_TIMEOUT | The timeout expires.
EFI_NOT_READY | Specified AP has not finished task and timeout has not expired.
BOOLEAN CheckTimeout | ( | IN OUT UINT64 * | PreviousTime,
 |  | IN UINT64 * | TotalTime,
 |  | IN UINT64 | Timeout
 | ) |  |

Checks whether timeout expires.

Check whether the number of elapsed performance counter ticks required for a timeout condition has been reached. If Timeout is zero, which means infinity, return value is always FALSE.

Parameters
[in,out] | PreviousTime | On input, the value of the performance counter when it was last read. On output, the current value of the performance counter
[in] | TotalTime | The total amount of elapsed time in performance counter ticks.
[in] | Timeout | The number of performance counter ticks required to reach a timeout condition.
Return values
TRUE | A timeout condition has been reached.
FALSE | A timeout condition has not been reached.
UINTN CollectProcessorCount ( IN CPU_MP_DATA * CpuMpData )

This function will get CPU count in the system.

Parameters
[in] CpuMpData Pointer to PEI CPU MP Data
Returns
CPU count detected
EFI_STATUS EnableDisableApWorker | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

Worker function to let the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP.
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
others | Failed to Enable/Disable AP.
VOID FillExchangeInfoData ( IN CPU_MP_DATA * CpuMpData )

This function will fill the exchange info structure.

Parameters
[in] CpuMpData Pointer to CPU MP Data
VOID FreeResetVector ( IN CPU_MP_DATA * CpuMpData )

Free AP reset vector buffer.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure.
VOID EFIAPI FutureBSPProc ( IN VOID * Buffer )

Worker function for SwitchBSP().

Worker function for SwitchBSP(), assigned to the AP which is intended to become BSP.

Parameters
[in] Buffer Pointer to CPU MP Data
UINT8 GetApLoopMode ( OUT UINT32 * MonitorFilterSize )

Get AP loop mode.

Parameters
[out] MonitorFilterSize Returns the largest monitor-line size in bytes.
Returns
The AP loop mode.
CPU_STATE GetApState ( IN CPU_AP_DATA * CpuData )

Get the Application Processors state.

Parameters
[in] CpuData The pointer to CPU_AP_DATA of specified AP
Returns
The AP status
CPU_MP_DATA* GetCpuMpDataFromGuidedHob ( VOID )

Get pointer to CPU MP Data structure from GUIDed HOB.

Returns
The pointer to CPU MP Data structure.
EFI_STATUS GetNextWaitingProcessorNumber ( OUT UINTN * NextProcessorNumber )

Searches for the next waiting AP.

Search for the next AP that is put in waiting state by single-threaded StartupAllAPs().

Parameters
[out] NextProcessorNumber Pointer to the processor number of the next waiting AP.
Return values
EFI_SUCCESS | The next waiting AP has been found.
EFI_NOT_FOUND | No waiting AP exists.
EFI_STATUS GetProcessorNumber | ( | IN CPU_MP_DATA * | CpuMpData,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

Find the current Processor number by APIC ID.

Parameters
[in] | CpuMpData | Pointer to PEI CPU MP Data
[out] | ProcessorNumber | Return the pocessor number found
Return values
EFI_SUCCESS | ProcessorNumber is found and returned.
EFI_NOT_FOUND | ProcessorNumber is not found.
VOID InitializeApData | ( | IN OUT CPU_MP_DATA * | CpuMpData,
 |  | IN UINTN | ProcessorNumber,
 |  | IN UINT32 | BistData,
 |  | IN UINT64 | ApTopOfStack
 | ) |  |

Initialize CPU AP Data when AP is wakeup at the first time.

Parameters
[in,out] | CpuMpData | Pointer to PEI CPU MP Data
[in] | ProcessorNumber | The handle number of processor
[in] | BistData | Processor BIST data
[in] | ApTopOfStack | Top of AP stack
BOOLEAN IsBspExecuteDisableEnabled ( VOID )

The function will check if BSP Execute Disable is enabled.

DxeIpl may have enabled Execute Disable for BSP, APs need to get the status and sync up the settings. If BSP's CR0.Paging is not set, BSP execute Disble feature is not working actually.

Return values
TRUE | BSP Execute Disable is enabled.
FALSE | BSP Execute Disable is not enabled.
BOOLEAN IsMwaitSupport ( VOID )

Detect whether Mwait-monitor feature is supported.

Return values
TRUE | Mwait-monitor feature is supported.
FALSE | Mwait-monitor feature is not supported.
EFI_STATUS EFIAPI MpInitLibGetNumberOfProcessors | ( | OUT UINTN * | NumberOfProcessors,
 |  | OPTIONAL OUT UINTN *NumberOfEnabledProcessors | OPTIONAL
 | ) |  |

Retrieves the number of logical processor in the platform and the number of those logical processors that are enabled on this boot. This service may only be called from the BSP.

Parameters
[out] | NumberOfProcessors | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
Return values
EFI_SUCCESS | The number of logical processors and enabled logical processors was retrieved.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | NumberOfProcessors is NULL and NumberOfEnabledProcessors is NULL.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibGetProcessorInfo | ( | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer,
 |  | OUT EFI_HEALTH_FLAGS *HealthData | OPTIONAL
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
[out] | HealthData | Return processor health data.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibInitialize ( VOID )

MP Initialize Library initialization.

This service will allocate AP reset vector and wakeup all APs to do APs initialization.

This service must be invoked before all other MP Initialize Library service are invoked.

Return values
EFI_SUCCESS | MP initialization succeeds.
Others | MP initialization fails.
EFI_STATUS EFIAPI MpInitLibWhoAmI ( OUT UINTN * ProcessorNumber )

This return the handle number for the calling processor. This service may be called from the BSP and APs.

Parameters
[out] ProcessorNumber Pointer to the handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.
EFI_NOT_READY | MP Initialize Library is not initialized.
VOID ResetProcessorToIdleState ( IN UINTN ProcessorNumber )

Reset an AP to Idle state.

Any task being executed by the AP will be aborted and the AP will be waiting for a new task in Wait-For-SIPI state.

Parameters
[in] ProcessorNumber The handle number of processor.
VOID RestoreVolatileRegisters | ( | IN CPU_VOLATILE_REGISTERS * | VolatileRegisters,
 |  | IN BOOLEAN | IsRestoreDr
 | ) |  |

Restore the volatile registers following INIT IPI.

Parameters
[in] | VolatileRegisters | Pointer to volatile resisters
[in] | IsRestoreDr | TRUE: Restore DRx if supported FALSE: Do not restore DRx
VOID RestoreWakeupBuffer ( IN CPU_MP_DATA * CpuMpData )

Restore wakeup buffer data.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure.
VOID SaveLocalApicTimerSetting ( IN CPU_MP_DATA * CpuMpData )

Save BSP's local APIC timer setting.

Parameters
[in] CpuMpData Pointer to CPU MP Data
VOID SaveVolatileRegisters ( OUT CPU_VOLATILE_REGISTERS * VolatileRegisters )

Save the volatile registers required to be restored following INIT IPI.

Parameters
[out] VolatileRegisters Returns buffer saved the volatile resisters
VOID SetApState | ( | IN CPU_AP_DATA * | CpuData,
 |  | IN CPU_STATE | State
 | ) |  |

Set the Application Processors state.

Parameters
[in] | CpuData | The pointer to CPU_AP_DATA of specified AP
[in] | State | The AP status
VOID SortApicId ( IN CPU_MP_DATA * CpuMpData )

Sort the APIC ID of all processors.

This function sorts the APIC ID of all processors so that processor number is assigned in the ascending order of APIC ID which eases MP debugging.

Parameters
[in] CpuMpData Pointer to PEI CPU MP Data
EFI_STATUS StartupAllAPsWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

Worker function to execute a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
others | Failed to Startup all APs.
EFI_STATUS StartupThisAPWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

Worker function to let the caller get one enabled AP to execute a caller-provided function.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | ProcessorNumber | The handle number of the AP.
[in] | WaitEvent | The event created by the caller with CreateEvent() service.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | Finished | If AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
others | Failed to Startup AP.
EFI_STATUS SwitchBSPWorker | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

Worker function to switch the requested AP to be the BSP from that point onward.

Parameters
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP.
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
others | Failed to switch BSP.
VOID SyncLocalApicTimerSetting ( IN CPU_MP_DATA * CpuMpData )

Sync local APIC timer setting from BSP to AP.

Parameters
[in] CpuMpData Pointer to CPU MP Data
VOID TimedWaitForApFinish | ( | IN CPU_MP_DATA * | CpuMpData,
 |  | IN UINT32 | FinishedApLimit,
 |  | IN UINT32 | TimeLimit
 | ) |  |

Helper function that waits until the finished AP count reaches the specified limit, or the specified timeout elapses (whichever comes first).

Parameters
[in] | CpuMpData | Pointer to CPU MP Data.
[in] | FinishedApLimit | The number of finished APs to wait for.
[in] | TimeLimit | The number of microseconds to wait for.
VOID WaitApWakeup ( IN volatile UINT32 * ApStartupSignalBuffer )

Wait for AP wakeup and write AP start-up signal till AP is waken up.

Parameters
[in] ApStartupSignalBuffer Pointer to AP wakeup signal
VOID WakeUpAP | ( | IN CPU_MP_DATA * | CpuMpData,
 |  | IN BOOLEAN | Broadcast,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | OPTIONAL IN VOID * | ProcedureArgument,
 |  | OPTIONAL IN BOOLEAN WakeUpDisabledAps |
 | ) |  |

This function will be called by BSP to wakeup AP.

Parameters
[in] | CpuMpData | Pointer to CPU MP Data
[in] | Broadcast | TRUE: Send broadcast IPI to all APs FALSE: Send IPI to AP by ApicId
[in] | ProcessorNumber | The handle number of specified processor
[in] | Procedure | The function to be invoked by AP
[in] | ProcedureArgument | The argument to be passed into AP function
[in] | WakeUpDisabledAps | Whether need to wake up disabled APs in broadcast mode.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/MpLib.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
Data Structures | Typedefs | Enumerations | Functions | Variables
MpLib.h File Reference

Data Structures

struct | CPU_EXCHANGE_ROLE_INFO
struct | CPU_VOLATILE_REGISTERS
struct | CPU_AP_DATA
struct | CPU_INFO_IN_HOB
struct | MP_ASSEMBLY_ADDRESS_MAP
struct | MP_CPU_EXCHANGE_INFO
struct | _CPU_MP_DATA

Typedefs

typedef struct _CPU_MP_DATA | CPU_MP_DATA
typedef IN UINTN | ApTargetCState
typedef IN UINTN IN UINTN | PmCodeSegment
typedef IN UINTN IN UINTN IN UINTN | TopOfApStack
typedef IN UINTN IN UINTN IN
UINTN IN UINTN 		NumberToFinish

Enumerations

enum | AP_LOOP_MODE { ApInHltLoop = 1, ApInMwaitLoop = 2, ApInRunLoop = 3 }
enum | AP_INIT_STATE { ApInitConfig = 1, ApInitReconfig = 2, ApInitDone = 3 }
enum CPU_STATE {
CpuStateIdle, CpuStateReady, CpuStateBusy, CpuStateFinished,
CpuStateDisabled
}

Functions

typedef | VOID (EFIAPI *ASM_RELOCATE_AP_LOOP)(IN BOOLEAN MwaitSupport
VOID EFIAPI | AsmGetAddressMap (OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap)
VOID EFIAPI | AsmExchangeRole (IN CPU_EXCHANGE_ROLE_INFO *MyInfo, IN CPU_EXCHANGE_ROLE_INFO *OthersInfo)
CPU_MP_DATA * GetCpuMpData (VOID)
VOID | SaveCpuMpData (IN CPU_MP_DATA *CpuMpData)
UINTN | GetWakeupBuffer (IN UINTN WakeupBufferSize)
UINTN | GetModeTransitionBuffer (IN UINTN BufferSize)
VOID | WakeUpAP (IN CPU_MP_DATA *CpuMpData, IN BOOLEAN Broadcast, IN UINTN ProcessorNumber, IN EFI_AP_PROCEDURE Procedure, OPTIONAL IN VOID *ProcedureArgument, OPTIONAL IN BOOLEAN WakeUpDisabledAps OPTIONAL)
VOID | InitMpGlobalData (IN CPU_MP_DATA *CpuMpData)
EFI_STATUS | StartupAllAPsWorker (IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS | StartupThisAPWorker (IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
EFI_STATUS | SwitchBSPWorker (IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS | EnableDisableApWorker (IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)
CPU_MP_DATA * GetCpuMpDataFromGuidedHob (VOID)
EFI_STATUS | CheckThisAP (IN UINTN ProcessorNumber)
EFI_STATUS CheckAllAPs (VOID)
VOID CheckAndUpdateApsStatus (VOID)
VOID | MicrocodeDetect (IN CPU_MP_DATA *CpuMpData, IN BOOLEAN IsBspCallIn)
BOOLEAN | IsMwaitSupport (VOID)
VOID EnableDebugAgent (VOID)

Variables

EFI_GUID mCpuInitMpLibHobGuid

Detailed Description

Common header file for MP Initialize Library.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI AsmExchangeRole | ( | IN CPU_EXCHANGE_ROLE_INFO * | MyInfo,
 |  | IN CPU_EXCHANGE_ROLE_INFO * | OthersInfo
 | ) |  |

This function is called by both the BSP and the AP which is to become the BSP to Exchange execution context including stack between them. After return from this function, the BSP becomes AP and the AP becomes the BSP.

Parameters
[in] | MyInfo | Pointer to buffer holding the exchanging information for the executing processor.
[in] | OthersInfo | Pointer to buffer holding the exchanging information for the peer.
VOID EFIAPI AsmGetAddressMap ( OUT MP_ASSEMBLY_ADDRESS_MAP * AddressMap )

Assembly code to get starting address and size of the rendezvous entry for APs. Information for fixing a jump instruction in the code is also returned.

Parameters
[out] AddressMap Output buffer for address map information.
EFI_STATUS CheckAllAPs ( VOID )

Checks status of all APs.

This function checks whether all APs have finished task assigned by StartupAllAPs(), and whether timeout expires.

Return values
EFI_SUCCESS | All APs have finished task assigned by StartupAllAPs().
EFI_TIMEOUT | The timeout expires.
EFI_NOT_READY | APs have not finished task and timeout has not expired.
VOID CheckAndUpdateApsStatus ( VOID )

Checks APs status and updates APs status if needed.

EFI_STATUS CheckThisAP ( IN UINTN ProcessorNumber )

Checks status of specified AP.

This function checks whether the specified AP has finished the task assigned by StartupThisAP(), and whether timeout expires.

Parameters
[in] ProcessorNumber The handle number of processor.
Return values
EFI_SUCCESS | Specified AP has finished task assigned by StartupThisAPs().
EFI_TIMEOUT | The timeout expires.
EFI_NOT_READY | Specified AP has not finished task and timeout has not expired.
VOID EnableDebugAgent ( VOID )

Enable Debug Agent to support source debugging on AP function.

EFI_STATUS EnableDisableApWorker | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

Worker function to let the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP.
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
others | Failed to Enable/Disable AP.
CPU_MP_DATA* GetCpuMpData ( VOID )

Get the pointer to CPU MP Data structure.

Returns
The pointer to CPU MP Data structure.

Get pointer to CPU MP Data structure. For BSP, the pointer is retrieved from HOB. For AP, the structure is just after IDT.

Returns
The pointer to CPU MP Data structure.
CPU_MP_DATA* GetCpuMpDataFromGuidedHob ( VOID )

Get pointer to CPU MP Data structure from GUIDed HOB.

Returns
The pointer to CPU MP Data structure.
UINTN GetModeTransitionBuffer ( IN UINTN BufferSize )

Get available EfiBootServicesCode memory below 4GB by specified size.

This buffer is required to safely transfer AP from real address mode to protected mode or long mode, due to the fact that the buffer returned by GetWakeupBuffer() may be marked as non-executable.

Parameters
[in] BufferSize Wakeup transition buffer size.
Return values
other | Return wakeup transition buffer address below 4GB.
0 | Cannot find free memory below 4GB.
UINTN GetWakeupBuffer ( IN UINTN WakeupBufferSize )

Get available system memory below 1MB by specified size.

Parameters
[in] WakeupBufferSize Wakeup buffer size required
Return values
other | Return wakeup buffer address below 1MB.
-1 | Cannot find free memory below 1MB.
VOID InitMpGlobalData ( IN CPU_MP_DATA * CpuMpData )

Initialize global data for MP support.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure.

Install Notify

BOOLEAN IsMwaitSupport ( VOID )

Detect whether Mwait-monitor feature is supported.

Return values
TRUE | Mwait-monitor feature is supported.
FALSE | Mwait-monitor feature is not supported.
VOID MicrocodeDetect | ( | IN CPU_MP_DATA * | CpuMpData,
 |  | IN BOOLEAN | IsBspCallIn
 | ) |  |

Detect whether specified processor can find matching microcode patch and load it.

Parameters
[in] | CpuMpData | The pointer to CPU MP Data structure.
[in] | IsBspCallIn | Indicate whether the caller is BSP or not.
VOID SaveCpuMpData ( IN CPU_MP_DATA * CpuMpData )

Save the pointer to CPU MP Data structure.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure will be saved.
EFI_STATUS StartupAllAPsWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

Worker function to execute a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
others | Failed to Startup all APs.
EFI_STATUS StartupThisAPWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

Worker function to let the caller get one enabled AP to execute a caller-provided function.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | ProcessorNumber | The handle number of the AP.
[in] | WaitEvent | The event created by the caller with CreateEvent() service.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode.
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | Finished | If AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
others | Failed to Startup AP.
EFI_STATUS SwitchBSPWorker | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

Worker function to switch the requested AP to be the BSP from that point onward.

Parameters
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP.
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
others | Failed to switch BSP.
typedef VOID ( EFIAPI * ASM_RELOCATE_AP_LOOP )

Assembly code to place AP into safe loop mode.

Place AP into targeted C-State if MONITOR is supported, otherwise place AP into hlt state. Place AP in protected mode if the current is long mode. Due to AP maybe wakeup by some hardware event. It could avoid accessing page table that may not available during booting to OS.

Parameters
[in] | MwaitSupport | TRUE indicates MONITOR is supported. FALSE indicates MONITOR is not supported.
[in] | ApTargetCState | Target C-State value.
[in] | PmCodeSegment | Protected mode code segment value.
VOID WakeUpAP | ( | IN CPU_MP_DATA * | CpuMpData,
 |  | IN BOOLEAN | Broadcast,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_AP_PROCEDURE | Procedure,
 |  | OPTIONAL IN VOID * | ProcedureArgument,
 |  | OPTIONAL IN BOOLEAN WakeUpDisabledAps |
 | ) |  |

This function will be called by BSP to wakeup AP.

Parameters
[in] | CpuMpData | Pointer to CPU MP Data
[in] | Broadcast | TRUE: Send broadcast IPI to all APs FALSE: Send IPI to AP by ApicId
[in] | ProcessorNumber | The handle number of specified processor
[in] | Procedure | The function to be invoked by AP
[in] | ProcedureArgument | The argument to be passed into AP function
[in] | WakeUpDisabledAps | Whether need to wake up disabled APs in broadcast mode.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
PeiMpInitLib.uni File Reference

Detailed Description

MP Initialize Library instance for PEI driver.

MP Initialize Library instance for PEI driver.

Copyright (c) 2016, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/PeiMpLib.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MpInitLib
Functions | Variables
PeiMpLib.c File Reference

Functions

EFI_STATUS EFIAPI | NotifyOnS3SmmInitDonePpi (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, IN VOID *InvokePpi)
VOID EnableDebugAgent (VOID)
CPU_MP_DATA * GetCpuMpData (VOID)
VOID | SaveCpuMpData (IN CPU_MP_DATA *CpuMpData)
BOOLEAN | CheckOverlapWithAllocatedBuffer (IN UINT64 WakeupBufferStart, IN UINT64 WakeupBufferEnd)
UINTN | GetWakeupBuffer (IN UINTN WakeupBufferSize)
UINTN | GetModeTransitionBuffer (IN UINTN BufferSize)
VOID CheckAndUpdateApsStatus (VOID)
VOID | InitMpGlobalData (IN CPU_MP_DATA *CpuMpData)
EFI_STATUS EFIAPI | MpInitLibStartupAllAPs (IN EFI_AP_PROCEDURE Procedure, IN BOOLEAN SingleThread, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT UINTN **FailedCpuList OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibStartupThisAP (IN EFI_AP_PROCEDURE Procedure, IN UINTN ProcessorNumber, IN EFI_EVENT WaitEvent OPTIONAL, IN UINTN TimeoutInMicroseconds, IN VOID *ProcedureArgument OPTIONAL, OUT BOOLEAN *Finished OPTIONAL)
EFI_STATUS EFIAPI | MpInitLibSwitchBSP (IN UINTN ProcessorNumber, IN BOOLEAN EnableOldBSP)
EFI_STATUS EFIAPI | MpInitLibEnableDisableAP (IN UINTN ProcessorNumber, IN BOOLEAN EnableAP, IN UINT32 *HealthFlag OPTIONAL)

Variables

EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc

Detailed Description

MP initialize support functions for PEI phase.

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID CheckAndUpdateApsStatus ( VOID )

Checks APs status and updates APs status if needed.

BOOLEAN CheckOverlapWithAllocatedBuffer | ( | IN UINT64 | WakeupBufferStart,
 |  | IN UINT64 | WakeupBufferEnd
 | ) |  |

Check if AP wakeup buffer is overlapped with existing allocated buffer.

Parameters
[in] | WakeupBufferStart | AP wakeup buffer start address.
[in] | WakeupBufferEnd | AP wakeup buffer end address.
Return values
TRUE | There is overlap.
FALSE | There is no overlap.
VOID EnableDebugAgent ( VOID )

Enable Debug Agent to support source debugging on AP function.

CPU_MP_DATA* GetCpuMpData ( VOID )

Get pointer to CPU MP Data structure. For BSP, the pointer is retrieved from HOB. For AP, the structure is just after IDT.

Returns
The pointer to CPU MP Data structure.
UINTN GetModeTransitionBuffer ( IN UINTN BufferSize )

Get available EfiBootServicesCode memory below 4GB by specified size.

This buffer is required to safely transfer AP from real address mode to protected mode or long mode, due to the fact that the buffer returned by GetWakeupBuffer() may be marked as non-executable.

Parameters
[in] BufferSize Wakeup transition buffer size.
Return values
other | Return wakeup transition buffer address below 4GB.
0 | Cannot find free memory below 4GB.
UINTN GetWakeupBuffer ( IN UINTN WakeupBufferSize )

Get available system memory below 1MB by specified size.

Parameters
[in] WakeupBufferSize Wakeup buffer size required
Return values
other | Return wakeup buffer address below 1MB.
-1 | Cannot find free memory below 1MB.
VOID InitMpGlobalData ( IN CPU_MP_DATA * CpuMpData )

Initialize global data for MP support.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure.

Install Notify

EFI_STATUS EFIAPI MpInitLibEnableDisableAP | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableAP,
 |  | IN UINT32 *HealthFlag | OPTIONAL
 | ) |  |

This service lets the caller enable or disable an AP from this point onward. This service may only be called from the BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | EnableAP | Specifies the new state for the processor for enabled, FALSE for disabled.
[in] | HealthFlag | If not NULL, a pointer to a value that specifies the new health status of the AP. This flag corresponds to StatusFlag defined in EFI_MP_SERVICES_PROTOCOL.GetProcessorInfo(). Only the PROCESSOR_HEALTH_STATUS_BIT is used. All other bits are ignored. If it is NULL, this parameter is ignored.
Return values
EFI_SUCCESS | The specified AP was enabled or disabled successfully.
EFI_UNSUPPORTED | Enabling or disabling an AP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Enabling or disabling an AP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | Processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI MpInitLibStartupAllAPs | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN BOOLEAN | SingleThread,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT UINTN **FailedCpuList | OPTIONAL
 | ) |  |

This service executes a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system. See type EFI_AP_PROCEDURE.
[in] | SingleThread | If TRUE, then all the enabled APs execute the function specified by Procedure one by one, in ascending order of processor handle number. If FALSE, then all the enabled APs execute the function specified by Procedure simultaneously.
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until all APs finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on all the enabled APs, and go on executing immediately. If all return from Procedure, or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for APs to return from Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before all APs return from Procedure, then Procedure on the failed APs is terminated. All enabled APs are available for next function assigned by MpInitLibStartupAllAPs() or MPInitLibStartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure for all APs.
[out] | FailedCpuList | If NULL, this parameter is ignored. Otherwise, if all APs finish successfully, then its content is set to NULL. If not all APs finish before timeout expires, then its content is set to address of the buffer holding handle numbers of the failed APs. The buffer is allocated by MP Initialization library, and it's the caller's responsibility to free the buffer with FreePool() service. In blocking mode, it is ready for consumption when the call returns. In non-blocking mode, it is ready when WaitEvent is signaled. The list of failed CPU is terminated by END_OF_CPU_LIST.
Return values
EFI_SUCCESS | In blocking mode, all APs have finished before the timeout expired.
EFI_SUCCESS | In non-blocking mode, function has been dispatched to all enabled APs.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_UNSUPPORTED | WaitEvent is not NULL if non-blocking mode is not supported.
EFI_DEVICE_ERROR | Caller processor is AP.
EFI_NOT_STARTED | No enabled APs exist in the system.
EFI_NOT_READY | Any enabled APs are busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_TIMEOUT | In blocking mode, the timeout expired before all enabled APs have finished.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI MpInitLibStartupThisAP | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | ProcessorNumber,
 |  | IN EFI_EVENT WaitEvent | OPTIONAL,
 |  | IN UINTN | TimeoutInMicroseconds,
 |  | IN VOID *ProcedureArgument | OPTIONAL,
 |  | OUT BOOLEAN *Finished | OPTIONAL
 | ) |  |

This service lets the caller get one enabled AP to execute a caller-provided function.

Parameters
[in] | Procedure | A pointer to the function to be run on the designated AP of the system. See type EFI_AP_PROCEDURE.
[in] | ProcessorNumber | The handle number of the AP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | WaitEvent | The event created by the caller with CreateEvent() service. If it is NULL, then execute in blocking mode. BSP waits until this AP finish or TimeoutInMicroSeconds expires. If it's not NULL, then execute in non-blocking mode. BSP requests the function specified by Procedure to be started on this AP, and go on executing immediately. If this AP return from Procedure or TimeoutInMicroSeconds expires, this event is signaled. The BSP can use the CheckEvent() or WaitForEvent() services to check the state of event. Type EFI_EVENT is defined in CreateEvent() in the Unified Extensible Firmware Interface Specification.
[in] | TimeoutInMicroseconds | Indicates the time limit in microseconds for this AP to finish this Procedure, either for blocking or non-blocking mode. Zero means infinity. If the timeout expires before this AP returns from Procedure, then Procedure on the AP is terminated. The AP is available for next function assigned by MpInitLibStartupAllAPs() or MpInitLibStartupThisAP(). If the timeout expires in blocking mode, BSP returns EFI_TIMEOUT. If the timeout expires in non-blocking mode, WaitEvent is signaled with SignalEvent().
[in] | ProcedureArgument | The parameter passed into Procedure on the specified AP.
[out] | Finished | If NULL, this parameter is ignored. In blocking mode, this parameter is ignored. In non-blocking mode, if AP returns from Procedure before the timeout expires, its content is set to TRUE. Otherwise, the value is set to FALSE. The caller can determine if the AP returned from Procedure by evaluating this value.
Return values
EFI_SUCCESS | In blocking mode, specified AP finished before the timeout expires.
EFI_SUCCESS | In non-blocking mode, the function has been dispatched to specified AP.
EFI_UNSUPPORTED | A non-blocking mode request was made after the UEFI event EFI_EVENT_GROUP_READY_TO_BOOT was signaled.
EFI_UNSUPPORTED | WaitEvent is not NULL if non-blocking mode is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_TIMEOUT | In blocking mode, the timeout expired before the specified AP has finished.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the BSP or disabled AP.
EFI_INVALID_PARAMETER | Procedure is NULL.
EFI_STATUS EFIAPI MpInitLibSwitchBSP | ( | IN UINTN | ProcessorNumber,
 |  | IN BOOLEAN | EnableOldBSP
 | ) |  |

This service switches the requested AP to be the BSP from that point onward. This service changes the BSP for all purposes. This call can only be performed by the current BSP.

Parameters
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP. The range is from 0 to the total number of logical processors minus 1. The total number of logical processors can be retrieved by MpInitLibGetNumberOfProcessors().
[in] | EnableOldBSP | If TRUE, then the old BSP will be listed as an enabled AP. Otherwise, it will be disabled.
Return values
EFI_SUCCESS | BSP successfully switched.
EFI_UNSUPPORTED | Switching the BSP cannot be completed prior to this service returning.
EFI_UNSUPPORTED | Switching the BSP is not supported.
EFI_DEVICE_ERROR | The calling processor is an AP.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber specifies the current BSP or a disabled AP.
EFI_NOT_READY | The specified AP is busy.
EFI_NOT_READY | MP Initialize Library is not initialized.
EFI_STATUS EFIAPI NotifyOnS3SmmInitDonePpi | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDesc,
 |  | IN VOID * | InvokePpi
 | ) |  |

S3 SMM Init Done notification function.

Parameters
PeiServices | Indirect reference to the PEI Services Table.
NotifyDesc | Address of the notification descriptor data structure.
InvokePpi | Address of the PPI that was invoked.
Return values
EFI_SUCCESS The function completes successfully.
VOID SaveCpuMpData ( IN CPU_MP_DATA * CpuMpData )

Save the pointer to CPU MP Data structure.

Parameters
[in] CpuMpData The pointer to CPU MP Data structure will be saved.

Variable Documentation

EFI_PEI_NOTIFY_DESCRIPTOR mS3SmmInitDoneNotifyDesc
Initial value:
= {
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
&gEdkiiS3SmmInitDoneGuid,
NotifyOnS3SmmInitDonePpi
}
NotifyOnS3SmmInitDonePpi
EFI_STATUS EFIAPI NotifyOnS3SmmInitDonePpi(IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, IN VOID *InvokePpi)
Definition: PeiMpLib.c:59
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MtrrLib Directory Reference

  • UefiCpuPkg
  • Library
  • MtrrLib
MtrrLib Directory Reference

Files

file | MtrrLib.c
file | MtrrLib.inf
file | MtrrLib.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MtrrLib/MtrrLib.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MtrrLib
Data Structures | Functions | Variables
MtrrLib.c File Reference

Data Structures

struct | MTRR_CONTEXT
struct | MTRR_LIB_ADDRESS

Functions

VOID | MtrrDebugPrintAllMtrrsWorker (IN MTRR_SETTINGS *MtrrSetting)
UINT32 | GetVariableMtrrCountWorker (VOID)
UINT32 EFIAPI | GetVariableMtrrCount (VOID)
UINT32 | GetFirmwareVariableMtrrCountWorker (VOID)
UINT32 EFIAPI | GetFirmwareVariableMtrrCount (VOID)
MTRR_MEMORY_CACHE_TYPE | MtrrGetDefaultMemoryTypeWorker (IN MTRR_SETTINGS *MtrrSetting)
MTRR_MEMORY_CACHE_TYPE EFIAPI | MtrrGetDefaultMemoryType (VOID)
VOID | MtrrLibPreMtrrChange (OUT MTRR_CONTEXT *MtrrContext)
VOID | MtrrLibPostMtrrChangeEnableCache (IN MTRR_CONTEXT *MtrrContext)
VOID | MtrrLibPostMtrrChange (IN MTRR_CONTEXT *MtrrContext)
MTRR_FIXED_SETTINGS * | MtrrGetFixedMtrrWorker (OUT MTRR_FIXED_SETTINGS *FixedSettings)
MTRR_FIXED_SETTINGS *EFIAPI | MtrrGetFixedMtrr (OUT MTRR_FIXED_SETTINGS *FixedSettings)
MTRR_VARIABLE_SETTINGS * | MtrrGetVariableMtrrWorker (IN MTRR_SETTINGS *MtrrSetting, IN UINT32 VariableMtrrCount, OUT MTRR_VARIABLE_SETTINGS *VariableSettings)
MTRR_VARIABLE_SETTINGS *EFIAPI | MtrrGetVariableMtrr (OUT MTRR_VARIABLE_SETTINGS *VariableSettings)
RETURN_STATUS | MtrrLibProgramFixedMtrr (IN MTRR_MEMORY_CACHE_TYPE Type, IN OUT UINT64 *Base, IN OUT UINT64 *Length, IN OUT UINT32 *LastMsrIndex, OUT UINT64 *ClearMask, OUT UINT64 *OrMask)
UINT32 | MtrrGetMemoryAttributeInVariableMtrrWorker (IN MTRR_VARIABLE_SETTINGS *VariableSettings, IN UINTN VariableMtrrCount, IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT VARIABLE_MTRR *VariableMtrr)
UINT32 | MtrrLibGetRawVariableRanges (IN MTRR_VARIABLE_SETTINGS *VariableSettings, IN UINTN VariableMtrrCount, IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT MTRR_MEMORY_RANGE *VariableMtrr)
UINT32 EFIAPI | MtrrGetMemoryAttributeInVariableMtrr (IN UINT64 MtrrValidBitsMask, IN UINT64 MtrrValidAddressMask, OUT VARIABLE_MTRR *VariableMtrr)
UINT64 | MtrrLibBiggestAlignment (UINT64 Address, UINT64 Alignment0)
BOOLEAN | MtrrLibTypeLeftPrecedeRight (IN MTRR_MEMORY_CACHE_TYPE Left, IN MTRR_MEMORY_CACHE_TYPE Right)
VOID | MtrrLibInitializeMtrrMask (OUT UINT64 *MtrrValidBitsMask, OUT UINT64 *MtrrValidAddressMask)
MTRR_MEMORY_CACHE_TYPE | MtrrLibPrecedence (IN MTRR_MEMORY_CACHE_TYPE MtrrType1, IN MTRR_MEMORY_CACHE_TYPE MtrrType2)
MTRR_MEMORY_CACHE_TYPE | MtrrGetMemoryAttributeByAddressWorker (IN MTRR_SETTINGS *MtrrSetting, IN PHYSICAL_ADDRESS Address)
MTRR_MEMORY_CACHE_TYPE EFIAPI | MtrrGetMemoryAttribute (IN PHYSICAL_ADDRESS Address)
RETURN_STATUS | MtrrLibSetMemoryType (IN MTRR_MEMORY_RANGE *Ranges, IN UINTN Capacity, IN OUT UINTN *Count, IN UINT64 BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Type)
UINT8 | MtrrLibGetNumberOfTypes (IN CONST MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount, IN UINT64 BaseAddress, IN UINT64 Length, IN OUT UINT8 *Types OPTIONAL)
VOID | MtrrLibCalculateLeastMtrrs (IN UINT16 VertexCount, IN MTRR_LIB_ADDRESS *Vertices, IN OUT CONST UINT8 *Weight, IN UINT16 Start, IN UINT16 Stop, IN BOOLEAN IncludeOptional)
RETURN_STATUS | MtrrLibAppendVariableMtrr (IN OUT MTRR_MEMORY_RANGE *Mtrrs, IN UINT32 MtrrCapacity, IN OUT UINT32 *MtrrCount, IN UINT64 BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Type)
MTRR_MEMORY_CACHE_TYPE | MtrrLibLowestType (IN UINT8 TypeBits)
BOOLEAN | MtrrLibIsPowerOfTwo (IN UINT64 Operand)
RETURN_STATUS | MtrrLibCalculateSubtractivePath (IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN UINT64 A0, IN CONST MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount, IN UINT16 VertexCount, IN MTRR_LIB_ADDRESS *Vertices, IN OUT UINT8 *Weight, IN UINT16 Start, IN UINT16 Stop, IN UINT8 Types, IN UINT8 TypeCount, IN OUT MTRR_MEMORY_RANGE *Mtrrs, OPTIONAL IN UINT32 MtrrCapacity, OPTIONAL IN OUT UINT32 *MtrrCount OPTIONAL)
RETURN_STATUS | MtrrLibCalculateMtrrs (IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN UINT64 A0, IN CONST MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount, IN VOID *Scratch, IN OUT UINTN *ScratchSize, IN OUT MTRR_MEMORY_RANGE *Mtrrs, IN UINT32 MtrrCapacity, IN OUT UINT32 *MtrrCount)
RETURN_STATUS | MtrrLibApplyFixedMtrrs (IN MTRR_FIXED_SETTINGS *Fixed, IN OUT MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCapacity, IN OUT UINTN *RangeCount)
RETURN_STATUS | MtrrLibApplyVariableMtrrs (IN CONST MTRR_MEMORY_RANGE *VariableMtrr, IN UINT32 VariableMtrrCount, IN OUT MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCapacity, IN OUT UINTN *RangeCount)
UINT8 | MtrrLibGetCompatibleTypes (IN CONST MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount)
VOID | MtrrLibMergeVariableMtrr (MTRR_MEMORY_RANGE *DstMtrrs, UINT32 DstMtrrCount, MTRR_MEMORY_RANGE *SrcMtrrs, UINT32 SrcMtrrCount, BOOLEAN *Modified)
RETURN_STATUS | MtrrLibSetMemoryRanges (IN MTRR_MEMORY_CACHE_TYPE DefaultType, IN UINT64 A0, IN MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount, IN VOID *Scratch, IN OUT UINTN *ScratchSize, OUT MTRR_MEMORY_RANGE *VariableMtrr, IN UINT32 VariableMtrrCapacity, OUT UINT32 *VariableMtrrCount)
RETURN_STATUS | MtrrLibSetBelow1MBMemoryAttribute (IN OUT MTRR_FIXED_SETTINGS *FixedSettings, OUT BOOLEAN *Modified, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Type)
RETURN_STATUS EFIAPI | MtrrSetMemoryAttributesInMtrrSettings (IN OUT MTRR_SETTINGS *MtrrSetting, IN VOID *Scratch, IN OUT UINTN *ScratchSize, IN CONST MTRR_MEMORY_RANGE *Ranges, IN UINTN RangeCount)
RETURN_STATUS EFIAPI | MtrrSetMemoryAttributeInMtrrSettings (IN OUT MTRR_SETTINGS *MtrrSetting, IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Attribute)
RETURN_STATUS EFIAPI | MtrrSetMemoryAttribute (IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN MTRR_MEMORY_CACHE_TYPE Attribute)
VOID | MtrrSetVariableMtrrWorker (IN MTRR_VARIABLE_SETTINGS *VariableSettings)
MTRR_VARIABLE_SETTINGS *EFIAPI | MtrrSetVariableMtrr (IN MTRR_VARIABLE_SETTINGS *VariableSettings)
VOID | MtrrSetFixedMtrrWorker (IN MTRR_FIXED_SETTINGS *FixedSettings)
MTRR_FIXED_SETTINGS *EFIAPI | MtrrSetFixedMtrr (IN MTRR_FIXED_SETTINGS *FixedSettings)
MTRR_SETTINGS *EFIAPI | MtrrGetAllMtrrs (OUT MTRR_SETTINGS *MtrrSetting)
MTRR_SETTINGS *EFIAPI | MtrrSetAllMtrrs (IN MTRR_SETTINGS *MtrrSetting)
BOOLEAN EFIAPI | IsMtrrSupported (VOID)
VOID EFIAPI | MtrrDebugPrintAllMtrrs (VOID)

Variables

CONST FIXED_MTRR mMtrrLibFixedMtrrTable []
GLOBAL_REMOVE_IF_UNREFERENCED
CONST CHAR8 * 		mMtrrMemoryCacheTypeShortName []

Detailed Description

MTRR setting library

Note:
Most of services in this library instance are suggested to be invoked by BSP only, except for MtrrSetAllMtrrs() which is used to sync BSP's MTRR setting to APs.

Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT32 EFIAPI GetFirmwareVariableMtrrCount ( VOID )

Returns the firmware usable variable MTRR count for the CPU.

Returns
Firmware usable variable MTRR count
UINT32 GetFirmwareVariableMtrrCountWorker ( VOID )

Worker function returns the firmware usable variable MTRR count for the CPU.

Returns
Firmware usable variable MTRR count
UINT32 EFIAPI GetVariableMtrrCount ( VOID )

Returns the variable MTRR count for the CPU.

Returns
Variable MTRR count
UINT32 GetVariableMtrrCountWorker ( VOID )

Worker function returns the variable MTRR count for the CPU.

Returns
Variable MTRR count
BOOLEAN EFIAPI IsMtrrSupported ( VOID )

Checks if MTRR is supported.

Return values
TRUE | MTRR is supported.
FALSE | MTRR is not supported.
VOID EFIAPI MtrrDebugPrintAllMtrrs ( VOID )

This function prints all MTRRs for debugging.

VOID MtrrDebugPrintAllMtrrsWorker ( IN MTRR_SETTINGS * MtrrSetting )

Worker function prints all MTRRs for debugging.

If MtrrSetting is not NULL, print MTRR settings from input MTRR settings buffer. If MtrrSetting is NULL, print MTRR settings from MTRRs.

Parameters
MtrrSetting A buffer holding all MTRRs content.
MTRR_SETTINGS* EFIAPI MtrrGetAllMtrrs ( OUT MTRR_SETTINGS * MtrrSetting )

This function gets the content in all MTRRs (variable and fixed)

Parameters
[out] MtrrSetting A buffer to hold all MTRRs content.
Return values
the pointer of MtrrSetting
MTRR_MEMORY_CACHE_TYPE EFIAPI MtrrGetDefaultMemoryType ( VOID )

Returns the default MTRR cache type for the system.

Returns
The default MTRR cache type.
MTRR_MEMORY_CACHE_TYPE MtrrGetDefaultMemoryTypeWorker ( IN MTRR_SETTINGS * MtrrSetting )

Worker function returns the default MTRR cache type for the system.

If MtrrSetting is not NULL, returns the default MTRR cache type from input MTRR settings buffer. If MtrrSetting is NULL, returns the default MTRR cache type from MSR.

Parameters
[in] MtrrSetting A buffer holding all MTRRs content.
Returns
The default MTRR cache type.
MTRR_FIXED_SETTINGS* EFIAPI MtrrGetFixedMtrr ( OUT MTRR_FIXED_SETTINGS * FixedSettings )

This function gets the content in fixed MTRRs

Parameters
[out] FixedSettings A buffer to hold fixed MTRRs content.
Return values
The pointer of FixedSettings
MTRR_FIXED_SETTINGS* MtrrGetFixedMtrrWorker ( OUT MTRR_FIXED_SETTINGS * FixedSettings )

Worker function gets the content in fixed MTRRs

Parameters
[out] FixedSettings A buffer to hold fixed MTRRs content.
Return values
The pointer of FixedSettings
MTRR_MEMORY_CACHE_TYPE EFIAPI MtrrGetMemoryAttribute ( IN PHYSICAL_ADDRESS Address )

This function will get the memory cache type of the specific address.

This function is mainly for debug purpose.

Parameters
[in] Address The specific address
Returns
Memory cache type of the specific address
MTRR_MEMORY_CACHE_TYPE MtrrGetMemoryAttributeByAddressWorker | ( | IN MTRR_SETTINGS * | MtrrSetting,
 |  | IN PHYSICAL_ADDRESS | Address
 | ) |  |

Worker function will get the memory cache type of the specific address.

If MtrrSetting is not NULL, gets the memory cache type from input MTRR settings buffer. If MtrrSetting is NULL, gets the memory cache type from MTRRs.

Parameters
[in] | MtrrSetting | A buffer holding all MTRRs content.
[in] | Address | The specific address
Returns
Memory cache type of the specific address
UINT32 EFIAPI MtrrGetMemoryAttributeInVariableMtrr | ( | IN UINT64 | MtrrValidBitsMask,
 |  | IN UINT64 | MtrrValidAddressMask,
 |  | OUT VARIABLE_MTRR * | VariableMtrr
 | ) |  |

Gets the attribute of variable MTRRs.

This function shadows the content of variable MTRRs into an internal array: VariableMtrr.

Parameters
[in] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[in] | MtrrValidAddressMask | The valid address mask for MTRR
[out] | VariableMtrr | The array to shadow variable MTRRs content
Returns
The return value of this parameter indicates the number of MTRRs which has been used.
UINT32 MtrrGetMemoryAttributeInVariableMtrrWorker | ( | IN MTRR_VARIABLE_SETTINGS * | VariableSettings,
 |  | IN UINTN | VariableMtrrCount,
 |  | IN UINT64 | MtrrValidBitsMask,
 |  | IN UINT64 | MtrrValidAddressMask,
 |  | OUT VARIABLE_MTRR * | VariableMtrr
 | ) |  |

Worker function gets the attribute of variable MTRRs.

This function shadows the content of variable MTRRs into an internal array: VariableMtrr.

Parameters
[in] | VariableSettings | The variable MTRR values to shadow
[in] | VariableMtrrCount | The number of variable MTRRs
[in] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[in] | MtrrValidAddressMask | The valid address mask for MTRR
[out] | VariableMtrr | The array to shadow variable MTRRs content
Returns
Number of MTRRs which has been used.
MTRR_VARIABLE_SETTINGS* EFIAPI MtrrGetVariableMtrr ( OUT MTRR_VARIABLE_SETTINGS * VariableSettings )

This function will get the raw value in variable MTRRs

Parameters
[out] VariableSettings A buffer to hold variable MTRRs content.
Returns
The VariableSettings input pointer
MTRR_VARIABLE_SETTINGS* MtrrGetVariableMtrrWorker | ( | IN MTRR_SETTINGS * | MtrrSetting,
 |  | IN UINT32 | VariableMtrrCount,
 |  | OUT MTRR_VARIABLE_SETTINGS * | VariableSettings
 | ) |  |

Worker function will get the raw value in variable MTRRs

If MtrrSetting is not NULL, gets the variable MTRRs raw value from input MTRR settings buffer. If MtrrSetting is NULL, gets the variable MTRRs raw value from MTRRs.

Parameters
[in] | MtrrSetting | A buffer holding all MTRRs content.
[in] | VariableMtrrCount | Number of variable MTRRs.
[out] | VariableSettings | A buffer to hold variable MTRRs content.
Returns
The VariableSettings input pointer
RETURN_STATUS MtrrLibAppendVariableMtrr | ( | IN OUT MTRR_MEMORY_RANGE * | Mtrrs,
 |  | IN UINT32 | MtrrCapacity,
 |  | IN OUT UINT32 * | MtrrCount,
 |  | IN UINT64 | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Type
 | ) |  |

Append the MTRR setting to MTRR setting array.

Parameters
Mtrrs | Array holding all MTRR settings.
MtrrCapacity | Capacity of the MTRR array.
MtrrCount | The count of MTRR settings in array.
BaseAddress | Base address.
Length | Length.
Type | Memory type.
Return values
RETURN_SUCCESS | MTRR setting is appended to array.
RETURN_OUT_OF_RESOURCES | Array is full.
RETURN_STATUS MtrrLibApplyFixedMtrrs | ( | IN MTRR_FIXED_SETTINGS * | Fixed,
 |  | IN OUT MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCapacity,
 |  | IN OUT UINTN * | RangeCount
 | ) |  |

Apply the fixed MTRR settings to memory range array.

Parameters
Fixed | The fixed MTRR settings.
Ranges | Return the memory range array holding memory type settings for all memory address.
RangeCapacity | The capacity of memory range array.
RangeCount | Return the count of memory range.
Return values
RETURN_SUCCESS | The memory range array is returned successfully.
RETURN_OUT_OF_RESOURCES | The count of memory ranges exceeds capacity.
RETURN_STATUS MtrrLibApplyVariableMtrrs | ( | IN CONST MTRR_MEMORY_RANGE * | VariableMtrr,
 |  | IN UINT32 | VariableMtrrCount,
 |  | IN OUT MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCapacity,
 |  | IN OUT UINTN * | RangeCount
 | ) |  |

Apply the variable MTRR settings to memory range array.

Parameters
VariableMtrr | The variable MTRR array.
VariableMtrrCount | The count of variable MTRRs.
Ranges | Return the memory range array with new MTRR settings applied.
RangeCapacity | The capacity of memory range array.
RangeCount | Return the count of memory range.
Return values
RETURN_SUCCESS | The memory range array is returned successfully.
RETURN_OUT_OF_RESOURCES | The count of memory ranges exceeds capacity.
UINT64 MtrrLibBiggestAlignment | ( | UINT64 | Address,
 |  | UINT64 | Alignment0
 | ) |  |

Return the biggest alignment (lowest set bit) of address. The function is equivalent to: 1 << LowBitSet64 (Address).

Parameters
Address | The address to return the alignment.
Alignment0 | The alignment to return when Address is 0.
Returns
The least alignment of the Address.
VOID MtrrLibCalculateLeastMtrrs | ( | IN UINT16 | VertexCount,
 |  | IN MTRR_LIB_ADDRESS * | Vertices,
 |  | IN OUT CONST UINT8 * | Weight,
 |  | IN UINT16 | Start,
 |  | IN UINT16 | Stop,
 |  | IN BOOLEAN | IncludeOptional
 | ) |  |

Calculate the least MTRR number from vertex Start to Stop and update the Previous of all vertices from Start to Stop is updated to reflect how the memory range is covered by MTRR.

Parameters
VertexCount | The count of vertices in the graph.
Vertices | Array holding all vertices.
Weight | 2-dimention array holding weights between vertices.
Start | Start vertex.
Stop | Stop vertex.
IncludeOptional | TRUE to count the optional weight.
RETURN_STATUS MtrrLibCalculateMtrrs | ( | IN MTRR_MEMORY_CACHE_TYPE | DefaultType,
 |  | IN UINT64 | A0,
 |  | IN CONST MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount,
 |  | IN VOID * | Scratch,
 |  | IN OUT UINTN * | ScratchSize,
 |  | IN OUT MTRR_MEMORY_RANGE * | Mtrrs,
 |  | IN UINT32 | MtrrCapacity,
 |  | IN OUT UINT32 * | MtrrCount
 | ) |  |

Calculate MTRR settings to cover the specified memory ranges.

Parameters
DefaultType | Default memory type.
A0 | Alignment to use when base address is 0.
Ranges | Memory range array holding the memory type settings for all memory address.
RangeCount | Count of memory ranges.
Scratch | A temporary scratch buffer that is used to perform the calculation. This is an optional parameter that may be NULL.
ScratchSize | Pointer to the size in bytes of the scratch buffer. It may be updated to the actual required size when the calculation needs more scratch buffer.
Mtrrs | Array holding all MTRR settings.
MtrrCapacity | Capacity of the MTRR array.
MtrrCount | The count of MTRR settings in array.
Return values
RETURN_SUCCESS | Variable MTRRs are allocated successfully.
RETURN_OUT_OF_RESOURCES | Count of variable MTRRs exceeds capacity.
RETURN_BUFFER_TOO_SMALL | The scratch buffer is too small for MTRR calculation.
RETURN_STATUS MtrrLibCalculateSubtractivePath | ( | IN MTRR_MEMORY_CACHE_TYPE | DefaultType,
 |  | IN UINT64 | A0,
 |  | IN CONST MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount,
 |  | IN UINT16 | VertexCount,
 |  | IN MTRR_LIB_ADDRESS * | Vertices,
 |  | IN OUT UINT8 * | Weight,
 |  | IN UINT16 | Start,
 |  | IN UINT16 | Stop,
 |  | IN UINT8 | Types,
 |  | IN UINT8 | TypeCount,
 |  | IN OUT MTRR_MEMORY_RANGE * | Mtrrs,
 |  | OPTIONAL IN UINT32 | MtrrCapacity,
 |  | OPTIONAL IN OUT UINT32 *MtrrCount | OPTIONAL
 | ) |  |

Calculate the subtractive path from vertex Start to Stop.

Parameters
DefaultType | Default memory type.
A0 | Alignment to use when base address is 0.
Ranges | Array holding memory type settings for all memory regions.
RangeCount | The count of memory ranges the array holds.
VertexCount | The count of vertices in the graph.
Vertices | Array holding all vertices.
Weight | 2-dimention array holding weights between vertices.
Start | Start vertex.
Stop | Stop vertex.
Types | Type bit mask of memory range from Start to Stop.
TypeCount | Number of different memory types from Start to Stop.
Mtrrs | Array holding all MTRR settings.
MtrrCapacity | Capacity of the MTRR array.
MtrrCount | The count of MTRR settings in array.
Return values
RETURN_SUCCESS | The subtractive path is calculated successfully.
RETURN_OUT_OF_RESOURCES | The MTRR setting array is full.
UINT8 MtrrLibGetCompatibleTypes | ( | IN CONST MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount
 | ) |  |

Return the memory type bit mask that's compatible to first type in the Ranges.

Parameters
Ranges | Memory range array holding the memory type settings for all memory address.
RangeCount | Count of memory ranges.
Returns
Compatible memory type bit mask.
UINT8 MtrrLibGetNumberOfTypes | ( | IN CONST MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount,
 |  | IN UINT64 | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN OUT UINT8 *Types | OPTIONAL
 | ) |  |

Return the number of memory types in range [BaseAddress, BaseAddress + Length).

Parameters
Ranges | Array holding memory type settings for all memory regions.
RangeCount | The count of memory ranges the array holds.
BaseAddress | Base address.
Length | Length.
Types | Return bit mask to indicate all memory types in the specified range.
Return values
Number of memory types.
UINT32 MtrrLibGetRawVariableRanges | ( | IN MTRR_VARIABLE_SETTINGS * | VariableSettings,
 |  | IN UINTN | VariableMtrrCount,
 |  | IN UINT64 | MtrrValidBitsMask,
 |  | IN UINT64 | MtrrValidAddressMask,
 |  | OUT MTRR_MEMORY_RANGE * | VariableMtrr
 | ) |  |

Convert variable MTRRs to a RAW MTRR_MEMORY_RANGE array. One MTRR_MEMORY_RANGE element is created for each MTRR setting. The routine doesn't remove the overlap or combine the near-by region.

Parameters
[in] | VariableSettings | The variable MTRR values to shadow
[in] | VariableMtrrCount | The number of variable MTRRs
[in] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[in] | MtrrValidAddressMask | The valid address mask for MTRR
[out] | VariableMtrr | The array to shadow variable MTRRs content
Returns
Number of MTRRs which has been used.
VOID MtrrLibInitializeMtrrMask | ( | OUT UINT64 * | MtrrValidBitsMask,
 |  | OUT UINT64 * | MtrrValidAddressMask
 | ) |  |

Initializes the valid bits mask and valid address mask for MTRRs.

This function initializes the valid bits mask and valid address mask for MTRRs.

Parameters
[out] | MtrrValidBitsMask | The mask for the valid bit of the MTRR
[out] | MtrrValidAddressMask | The valid address mask for the MTRR
BOOLEAN MtrrLibIsPowerOfTwo ( IN UINT64 Operand )

Return TRUE when the Operand is exactly power of 2.

Return values
TRUE | Operand is exactly power of 2.
FALSE | Operand is not power of 2.
MTRR_MEMORY_CACHE_TYPE MtrrLibLowestType ( IN UINT8 TypeBits )

Return the memory type that has the least precedence.

Parameters
TypeBits Bit mask of memory type.
Return values
Memory type that has the least precedence.
VOID MtrrLibMergeVariableMtrr | ( | MTRR_MEMORY_RANGE * | DstMtrrs,
 |  | UINT32 | DstMtrrCount,
 |  | MTRR_MEMORY_RANGE * | SrcMtrrs,
 |  | UINT32 | SrcMtrrCount,
 |  | BOOLEAN * | Modified
 | ) |  |

Overwrite the destination MTRR settings with the source MTRR settings. This routine is to make sure the modification to destination MTRR settings is as small as possible.

Parameters
DstMtrrs | Destination MTRR settings.
DstMtrrCount | Count of destination MTRR settings.
SrcMtrrs | Source MTRR settings.
SrcMtrrCount | Count of source MTRR settings.
Modified | Flag array to indicate which destination MTRR setting is modified.
VOID MtrrLibPostMtrrChange ( IN MTRR_CONTEXT * MtrrContext )

Cleaning up after programming MTRRs.

This function will do some clean up after programming MTRRs: enable MTRR caching functionality, and enable cache

Parameters
[in] MtrrContext Pointer to context to restore
VOID MtrrLibPostMtrrChangeEnableCache ( IN MTRR_CONTEXT * MtrrContext )

Cleaning up after programming MTRRs.

This function will do some clean up after programming MTRRs: Flush all TLBs, re-enable caching, restore CR4.

Parameters
[in] MtrrContext Pointer to context to restore
MTRR_MEMORY_CACHE_TYPE MtrrLibPrecedence | ( | IN MTRR_MEMORY_CACHE_TYPE | MtrrType1,
 |  | IN MTRR_MEMORY_CACHE_TYPE | MtrrType2
 | ) |  |

Determines the real attribute of a memory range.

This function is to arbitrate the real attribute of the memory when there are 2 MTRRs covers the same memory range. For further details, please refer the IA32 Software Developer's Manual, Volume 3, Section "MTRR Precedences".

Parameters
[in] | MtrrType1 | The first kind of Memory type
[in] | MtrrType2 | The second kind of memory type
VOID MtrrLibPreMtrrChange ( OUT MTRR_CONTEXT * MtrrContext )

Preparation before programming MTRR.

This function will do some preparation for programming MTRRs: disable cache, invalid cache and disable MTRR caching functionality

Parameters
[out] MtrrContext Pointer to context to save
RETURN_STATUS MtrrLibProgramFixedMtrr | ( | IN MTRR_MEMORY_CACHE_TYPE | Type,
 |  | IN OUT UINT64 * | Base,
 |  | IN OUT UINT64 * | Length,
 |  | IN OUT UINT32 * | LastMsrIndex,
 |  | OUT UINT64 * | ClearMask,
 |  | OUT UINT64 * | OrMask
 | ) |  |

Programs fixed MTRRs registers.

Parameters
[in] | Type | The memory type to set.
[in,out] | Base | The base address of memory range.
[in,out] | Length | The length of memory range.
[in,out] | LastMsrIndex | On input, the last index of the fixed MTRR MSR to program. On return, the current index of the fixed MTRR MSR to program.
[out] | ClearMask | The bits to clear in the fixed MTRR MSR.
[out] | OrMask | The bits to set in the fixed MTRR MSR.
Return values
RETURN_SUCCESS | The cache type was updated successfully
RETURN_UNSUPPORTED | The requested range or cache type was invalid for the fixed MTRRs.
RETURN_STATUS MtrrLibSetBelow1MBMemoryAttribute | ( | IN OUT MTRR_FIXED_SETTINGS * | FixedSettings,
 |  | OUT BOOLEAN * | Modified,
 |  | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Type
 | ) |  |

Set the below-1MB memory attribute to fixed MTRR buffer. Modified flag array indicates which fixed MTRR is modified.

Parameters
[in,out] | FixedSettings | Fixed MTRR buffer.
[out] | Modified | Flag array indicating which MTRR is modified.
[in] | BaseAddress | Base address.
[in] | Length | Length.
[in] | Type | Memory type.
Return values
RETURN_SUCCESS | The memory attribute is set successfully.
RETURN_UNSUPPORTED | The requested range or cache type was invalid for the fixed MTRRs.
RETURN_STATUS MtrrLibSetMemoryRanges | ( | IN MTRR_MEMORY_CACHE_TYPE | DefaultType,
 |  | IN UINT64 | A0,
 |  | IN MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount,
 |  | IN VOID * | Scratch,
 |  | IN OUT UINTN * | ScratchSize,
 |  | OUT MTRR_MEMORY_RANGE * | VariableMtrr,
 |  | IN UINT32 | VariableMtrrCapacity,
 |  | OUT UINT32 * | VariableMtrrCount
 | ) |  |

Calculate the variable MTRR settings for all memory ranges.

Parameters
DefaultType | Default memory type.
A0 | Alignment to use when base address is 0.
Ranges | Memory range array holding the memory type settings for all memory address.
RangeCount | Count of memory ranges.
Scratch | Scratch buffer to be used in MTRR calculation.
ScratchSize | Pointer to the size of scratch buffer.
VariableMtrr | Array holding all MTRR settings.
VariableMtrrCapacity | Capacity of the MTRR array.
VariableMtrrCount | The count of MTRR settings in array.
Return values
RETURN_SUCCESS | Variable MTRRs are allocated successfully.
RETURN_OUT_OF_RESOURCES | Count of variable MTRRs exceeds capacity.
RETURN_BUFFER_TOO_SMALL | The scratch buffer is too small for MTRR calculation. The required scratch buffer size is returned through ScratchSize.
RETURN_STATUS MtrrLibSetMemoryType | ( | IN MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | Capacity,
 |  | IN OUT UINTN * | Count,
 |  | IN UINT64 | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Type
 | ) |  |

Update the Ranges array to change the specified range identified by BaseAddress and Length to Type.

Parameters
Ranges | Array holding memory type settings for all memory regions.
Capacity | The maximum count of memory ranges the array can hold.
Count | Return the new memory range count in the array.
BaseAddress | The base address of the memory range to change type.
Length | The length of the memory range to change type.
Type | The new type of the specified memory range.
Return values
RETURN_SUCCESS | The type of the specified memory range is changed successfully.
RETURN_ALREADY_STARTED | The type of the specified memory range equals to the desired type.
RETURN_OUT_OF_RESOURCES | The new type set causes the count of memory range exceeds capacity.
BOOLEAN MtrrLibTypeLeftPrecedeRight | ( | IN MTRR_MEMORY_CACHE_TYPE | Left,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Right
 | ) |  |

Return whether the left MTRR type precedes the right MTRR type.

The MTRR type precedence rules are:

  1. UC precedes any other type
  2. WT precedes WB For further details, please refer the IA32 Software Developer's Manual, Volume 3, Section "MTRR Precedences".
Parameters
Left | The left MTRR type.
Right | The right MTRR type.
Return values
TRUE | Left precedes Right.
FALSE | Left doesn't precede Right.
MTRR_SETTINGS* EFIAPI MtrrSetAllMtrrs ( IN MTRR_SETTINGS * MtrrSetting )

This function sets all MTRRs (variable and fixed)

Parameters
[in] MtrrSetting A buffer holding all MTRRs content.
Return values
The pointer of MtrrSetting
MTRR_FIXED_SETTINGS* EFIAPI MtrrSetFixedMtrr ( IN MTRR_FIXED_SETTINGS * FixedSettings )

This function sets fixed MTRRs

Parameters
[in] FixedSettings A buffer to hold fixed MTRRs content.
Return values
The pointer of FixedSettings
VOID MtrrSetFixedMtrrWorker ( IN MTRR_FIXED_SETTINGS * FixedSettings )

Worker function setting fixed MTRRs

Parameters
[in] FixedSettings A buffer to hold fixed MTRRs content.
RETURN_STATUS EFIAPI MtrrSetMemoryAttribute | ( | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Attribute
 | ) |  |

This function attempts to set the attributes for a memory range.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory range.
[in] | Length | The size in bytes of the memory range.
[in] | Attributes | The bit mask of attributes to set for the memory range.
Return values
RETURN_SUCCESS | The attributes were set for the memory range.
RETURN_INVALID_PARAMETER | Length is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range. Multiple memory range attributes setting by calling this API multiple times may fail with status RETURN_OUT_OF_RESOURCES. It may not mean the number of CPU MTRRs are too small to set such memory attributes. Pass the multiple memory range attributes to one call of MtrrSetMemoryAttributesInMtrrSettings() may succeed.
RETURN_BUFFER_TOO_SMALL | The fixed internal scratch buffer is too small for MTRR calculation. Caller should use MtrrSetMemoryAttributesInMtrrSettings() to specify external scratch buffer.
RETURN_STATUS EFIAPI MtrrSetMemoryAttributeInMtrrSettings | ( | IN OUT MTRR_SETTINGS * | MtrrSetting,
 |  | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN MTRR_MEMORY_CACHE_TYPE | Attribute
 | ) |  |

This function attempts to set the attributes into MTRR setting buffer for a memory range.

Parameters
[in,out] | MtrrSetting | MTRR setting buffer to be set.
[in] | BaseAddress | The physical address that is the start address of a memory range.
[in] | Length | The size in bytes of the memory range.
[in] | Attribute | The bit mask of attributes to set for the memory range.
Return values
RETURN_SUCCESS | The attributes were set for the memory range.
RETURN_INVALID_PARAMETER | Length is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range. Multiple memory range attributes setting by calling this API multiple times may fail with status RETURN_OUT_OF_RESOURCES. It may not mean the number of CPU MTRRs are too small to set such memory attributes. Pass the multiple memory range attributes to one call of MtrrSetMemoryAttributesInMtrrSettings() may succeed.
RETURN_BUFFER_TOO_SMALL | The fixed internal scratch buffer is too small for MTRR calculation. Caller should use MtrrSetMemoryAttributesInMtrrSettings() to specify external scratch buffer.
RETURN_STATUS EFIAPI MtrrSetMemoryAttributesInMtrrSettings | ( | IN OUT MTRR_SETTINGS * | MtrrSetting,
 |  | IN VOID * | Scratch,
 |  | IN OUT UINTN * | ScratchSize,
 |  | IN CONST MTRR_MEMORY_RANGE * | Ranges,
 |  | IN UINTN | RangeCount
 | ) |  |

This function attempts to set the attributes into MTRR setting buffer for multiple memory ranges.

Parameters
[in,out] | MtrrSetting | MTRR setting buffer to be set.
[in] | Scratch | A temporary scratch buffer that is used to perform the calculation.
[in,out] | ScratchSize | Pointer to the size in bytes of the scratch buffer. It may be updated to the actual required size when the calculation needs more scratch buffer.
[in] | Ranges | Pointer to an array of MTRR_MEMORY_RANGE. When range overlap happens, the last one takes higher priority. When the function returns, either all the attributes are set successfully, or none of them is set.
[in] | RangeCount | Count of MTRR_MEMORY_RANGE.
Return values
RETURN_SUCCESS | The attributes were set for all the memory ranges.
RETURN_INVALID_PARAMETER | Length in any range is zero.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length in any range.
RETURN_UNSUPPORTED | The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length in any range.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource ranges.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_BUFFER_TOO_SMALL | The scratch buffer is too small for MTRR calculation.
MTRR_VARIABLE_SETTINGS* EFIAPI MtrrSetVariableMtrr ( IN MTRR_VARIABLE_SETTINGS * VariableSettings )

This function sets variable MTRRs

Parameters
[in] VariableSettings A buffer to hold variable MTRRs content.
Returns
The pointer of VariableSettings
VOID MtrrSetVariableMtrrWorker ( IN MTRR_VARIABLE_SETTINGS * VariableSettings )

Worker function setting variable MTRRs

Parameters
[in] VariableSettings A buffer to hold variable MTRRs content.

Variable Documentation

GLOBAL_REMOVE_IF_UNREFERENCED CONST CHAR8* mMtrrMemoryCacheTypeShortName[]
Initial value:
= {
"UC",
"WC",
"R*",
"R*",
"WT",
"WP",
"WB",
"R*"
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MtrrLib/MtrrLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • MtrrLib
MtrrLib.uni File Reference

Detailed Description

MTRR library provides APIs for MTRR operation.

MTRR library provides APIs for MTRR operation.

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/PlatformSecLibNull Directory Reference

  • UefiCpuPkg
  • Library
  • PlatformSecLibNull
PlatformSecLibNull Directory Reference

Files

file | PlatformSecLibNull.c
file | PlatformSecLibNull.inf
file | PlatformSecLibNull.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.c File Reference

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  • PlatformSecLibNull
Functions
PlatformSecLibNull.c File Reference

Functions

EFI_PEI_PPI_DESCRIPTOR *EFIAPI | SecPlatformMain (IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData)
EFI_STATUS EFIAPI | SecPlatformInformation (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
VOID EFIAPI | SecPlatformDisableTemporaryMemory (VOID)
VOID EFIAPI | _ModuleEntryPoint (VOID)

Detailed Description

Null instance of Platform Sec Lib.

Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI _ModuleEntryPoint ( VOID )

This function provides dummy function so that SecCore can pass build validation. All real platform library instances need to implement the real entry point in assembly.

VOID EFIAPI SecPlatformDisableTemporaryMemory ( VOID )

This interface disables temporary memory in SEC Phase.

EFI_STATUS EFIAPI SecPlatformInformation | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD * | PlatformInformationRecord
 | ) |  |

This interface conveys state information out of the Security (SEC) phase into PEI.

Parameters
PeiServices | Pointer to the PEI Services Table.
StructureSize | Pointer to the variable describing size of the input buffer.
PlatformInformationRecord | Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.
EFI_PEI_PPI_DESCRIPTOR* EFIAPI SecPlatformMain ( IN OUT EFI_SEC_PEI_HAND_OFF * SecCoreData )

A developer supplied function to perform platform specific operations.

It's a developer supplied function to perform any operations appropriate to a given platform. It's invoked just before passing control to PEI core by SEC core. Platform developer may modify the SecCoreData passed to PEI Core. It returns a platform specific PPI list that platform wishes to pass to PEI core. The Generic SEC core module will merge this list to join the final list passed to PEI core.

Parameters
SecCoreData The same parameter as passing to PEI core. It could be overridden by this function.
Returns
The platform specific PPI list to be passed to PEI core or NULL if there is no need of such platform specific PPI list.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • PlatformSecLibNull
PlatformSecLibNull.uni File Reference

Detailed Description

Library functions for PlatformSecLib.

Null instance of Platform Sec Library.

Copyright (c) 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib Directory Reference

  • UefiCpuPkg
  • Library
  • RegisterCpuFeaturesLib
RegisterCpuFeaturesLib Directory Reference

Files

file | CpuFeaturesInitialize.c
file | DxeRegisterCpuFeaturesLib.c
file | DxeRegisterCpuFeaturesLib.inf
file | PeiRegisterCpuFeaturesLib.c
file | PeiRegisterCpuFeaturesLib.inf
file | RegisterCpuFeatures.h
file | RegisterCpuFeaturesLib.c
file | RegisterCpuFeaturesLib.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c File Reference

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  • RegisterCpuFeaturesLib
Functions | Variables
CpuFeaturesInitialize.c File Reference

Functions

VOID | SetCapabilityPcd (IN UINT8 *SupportedFeatureMask)
VOID | SetSettingPcd (IN UINT8 *SupportedFeatureMask)
UINT8 * | GetSupportPcd (VOID)
UINT8 * | GetConfigurationPcd (VOID)
VOID | FillProcessorInfo (IN OUT REGISTER_CPU_FEATURE_INFORMATION *CpuInfo)
VOID | CpuInitDataInitialize (IN UINTN NumberOfCpus)
VOID | SupportedMaskOr (IN UINT8 *SupportedFeatureMask, IN UINT8 *OrFeatureBitMask)
VOID | SupportedMaskAnd (IN UINT8 *SupportedFeatureMask, IN UINT8 *AndFeatureBitMask)
VOID | SupportedMaskCleanBit (IN UINT8 *SupportedFeatureMask, IN UINT8 *AndFeatureBitMask)
BOOLEAN | IsBitMaskMatch (IN UINT8 *SupportedFeatureMask, IN UINT8 *ComparedFeatureBitMask)
VOID EFIAPI | CollectProcessorData (IN OUT VOID *Buffer)
VOID | DumpRegisterTableOnProcessor (IN UINTN ProcessorNumber)
CPU_FEATURE_DEPENDENCE_TYPE | BiggestDep (IN CPU_FEATURE_DEPENDENCE_TYPE BeforeDep, IN CPU_FEATURE_DEPENDENCE_TYPE AfterDep, IN CPU_FEATURE_DEPENDENCE_TYPE NoneNeibBeforeDep, IN CPU_FEATURE_DEPENDENCE_TYPE NoneNeibAfterDep)
VOID | AnalysisProcessorFeatures (IN UINTN NumberOfCpus)
VOID | LibReleaseSemaphore (IN OUT volatile UINT32 *Sem)
VOID | LibWaitForSemaphore (IN OUT volatile UINT32 *Sem)
VOID | ProgramProcessorRegister (IN CPU_REGISTER_TABLE *RegisterTable, IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, IN CPU_STATUS_INFORMATION *CpuStatus, IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags)
VOID EFIAPI | SetProcessorRegister (IN OUT VOID *Buffer)
VOID EFIAPI | CpuFeaturesDetect (VOID)

Variables

CHAR16 * | mDependTypeStr [] = {L"None", L"Thread", L"Core", L"Package", L"Invalid" }
CHAR16 * | mRegisterTypeStr [] = {L"MSR", L"CR", L"MMIO", L"CACHE", L"SEMAP", L"INVALID" }

Detailed Description

CPU Features Initialize functions.

Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID AnalysisProcessorFeatures ( IN UINTN NumberOfCpus )

Analysis register CPU features on each processor and save CPU setting in CPU register table.

Parameters
[in] NumberOfCpus Number of processor in system
CPU_FEATURE_DEPENDENCE_TYPE BiggestDep | ( | IN CPU_FEATURE_DEPENDENCE_TYPE | BeforeDep,
 |  | IN CPU_FEATURE_DEPENDENCE_TYPE | AfterDep,
 |  | IN CPU_FEATURE_DEPENDENCE_TYPE | NoneNeibBeforeDep,
 |  | IN CPU_FEATURE_DEPENDENCE_TYPE | NoneNeibAfterDep
 | ) |  |

Get the biggest dependence type. PackageDepType > CoreDepType > ThreadDepType > NoneDepType.

Parameters
[in] | BeforeDep | Before dependence type.
[in] | AfterDep | After dependence type.
[in] | NoneNeibBeforeDep | Before dependence type for not neighborhood features.
[in] | NoneNeibAfterDep | After dependence type for not neighborhood features.
Return values
Return the biggest dependence type.
VOID EFIAPI CollectProcessorData ( IN OUT VOID * Buffer )

Collects processor data for calling processor.

Parameters
[in,out] Buffer The pointer to private data buffer.
VOID EFIAPI CpuFeaturesDetect ( VOID )

Performs CPU features detection.

This service will invoke MP service to check CPU features' capabilities on BSP/APs.

Note
This service could be called by BSP only.
VOID CpuInitDataInitialize ( IN UINTN NumberOfCpus )

Prepares for private data used for CPU features.

Parameters
[in] NumberOfCpus Number of processor in system
VOID DumpRegisterTableOnProcessor ( IN UINTN ProcessorNumber )

Dump the contents of a CPU register table.

Parameters
[in] ProcessorNumber The index of the CPU to show the register table contents
Note
This service could be called by BSP only.
VOID FillProcessorInfo ( IN OUT REGISTER_CPU_FEATURE_INFORMATION * CpuInfo )

Collects CPU type and feature information.

Parameters
[in,out] CpuInfo The pointer to CPU feature information
UINT8* GetConfigurationPcd ( VOID )

Worker function to get PcdCpuFeaturesUserConfiguration.

Returns
The pointer to CPU feature bits mask buffer.
UINT8* GetSupportPcd ( VOID )

Worker function to get PcdCpuFeaturesSupport.

Returns
The pointer to CPU feature bits mask buffer.
BOOLEAN IsBitMaskMatch | ( | IN UINT8 * | SupportedFeatureMask,
 |  | IN UINT8 * | ComparedFeatureBitMask
 | ) |  |

Worker function to check if the compared CPU feature set in the CPU feature supported bits mask buffer.

Parameters
[in] | SupportedFeatureMask | The pointer to CPU feature bits mask buffer
[in] | ComparedFeatureBitMask | The feature bit mask to be compared
Return values
TRUE | The ComparedFeatureBitMask is set in CPU feature supported bits mask buffer.
FALSE | The ComparedFeatureBitMask is not set in CPU feature supported bits mask buffer.
VOID LibReleaseSemaphore ( IN OUT volatile UINT32 * Sem )

Increment semaphore by 1.

Parameters
Sem IN: 32-bit unsigned integer
VOID LibWaitForSemaphore ( IN OUT volatile UINT32 * Sem )

Decrement the semaphore by 1 if it is not zero.

Performs an atomic decrement operation for semaphore. The compare exchange operation must be performed using MP safe mechanisms.

Parameters
Sem IN: 32-bit unsigned integer
VOID ProgramProcessorRegister | ( | IN CPU_REGISTER_TABLE * | RegisterTable,
 |  | IN EFI_CPU_PHYSICAL_LOCATION * | ApLocation,
 |  | IN CPU_STATUS_INFORMATION * | CpuStatus,
 |  | IN PROGRAM_CPU_REGISTER_FLAGS * | CpuFlags
 | ) |  |

Initialize the CPU registers from a register table.

Parameters
[in] | RegisterTable | The register table for this AP.
[in] | ApLocation | AP location info for this ap.
[in] | CpuStatus | CPU status info for this CPU.
[in] | CpuFlags | Flags data structure used when program the register.
Note
This service could be called by BSP/APs.
VOID SetCapabilityPcd ( IN UINT8 * SupportedFeatureMask )

Worker function to save PcdCpuFeaturesCapability.

Parameters
[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
VOID EFIAPI SetProcessorRegister ( IN OUT VOID * Buffer )

Programs registers for the calling processor.

Parameters
[in,out] Buffer The pointer to private data buffer.
VOID SetSettingPcd ( IN UINT8 * SupportedFeatureMask )

Worker function to save PcdCpuFeaturesSetting.

Parameters
[in] SupportedFeatureMask The pointer to CPU feature bits mask buffer
VOID SupportedMaskAnd | ( | IN UINT8 * | SupportedFeatureMask,
 |  | IN UINT8 * | AndFeatureBitMask
 | ) |  |

Worker function to do AND operation on CPU feature supported bits mask buffer.

Parameters
[in] | SupportedFeatureMask | The pointer to CPU feature bits mask buffer
[in] | AndFeatureBitMask | The feature bit mask to do AND operation
VOID SupportedMaskCleanBit | ( | IN UINT8 * | SupportedFeatureMask,
 |  | IN UINT8 * | AndFeatureBitMask
 | ) |  |

Worker function to clean bit operation on CPU feature supported bits mask buffer.

Parameters
[in] | SupportedFeatureMask | The pointer to CPU feature bits mask buffer
[in] | AndFeatureBitMask | The feature bit mask to do XOR operation
VOID SupportedMaskOr | ( | IN UINT8 * | SupportedFeatureMask,
 |  | IN UINT8 * | OrFeatureBitMask
 | ) |  |

Worker function to do OR operation on CPU feature supported bits mask buffer.

Parameters
[in] | SupportedFeatureMask | The pointer to CPU feature bits mask buffer
[in] | OrFeatureBitMask | The feature bit mask to do OR operation
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib/DxeRegisterCpuFeaturesLib.c File Reference

  • File List
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  • UefiCpuPkg
  • Library
  • RegisterCpuFeaturesLib
Functions | Variables
DxeRegisterCpuFeaturesLib.c File Reference

Functions

CPU_FEATURES_DATA * GetCpuFeaturesData (VOID)
EFI_MP_SERVICES_PROTOCOL * | GetMpProtocol (VOID)
UINTN | GetProcessorIndex (VOID)
EFI_STATUS | GetProcessorInformation (IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
VOID | StartupAPsWorker (IN EFI_AP_PROCEDURE Procedure, IN EFI_EVENT MpEvent)
VOID | SwitchNewBsp (IN UINTN ProcessorNumber)
VOID | GetNumberOfProcessor (OUT UINTN *NumberOfCpus, OUT UINTN *NumberOfEnabledProcessors)
VOID EFIAPI | CpuFeaturesInitialize (VOID)

Variables

CPU_FEATURES_DATA | mCpuFeaturesData = {0}
EFI_MP_SERVICES_PROTOCOL * | mCpuFeaturesMpServices = NULL

Detailed Description

CPU Register Table Library functions.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI CpuFeaturesInitialize ( VOID )

Performs CPU features Initialization.

This service will invoke MP service to perform CPU features initialization on BSP/APs per user configuration.

Note
This service could be called by BSP only.
CPU_FEATURES_DATA* GetCpuFeaturesData ( VOID )

Worker function to get CPU_FEATURES_DATA pointer.

Returns
Pointer to CPU_FEATURES_DATA.
EFI_MP_SERVICES_PROTOCOL* GetMpProtocol ( VOID )

Worker function to get EFI_MP_SERVICES_PROTOCOL pointer.

Returns
Pointer to EFI_MP_SERVICES_PROTOCOL.
VOID GetNumberOfProcessor | ( | OUT UINTN * | NumberOfCpus,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

Worker function to retrieve the number of logical processor in the platform.

Parameters
[out] | NumberOfCpus | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
UINTN GetProcessorIndex ( VOID )

Worker function to return processor index.

Returns
The processor index.
EFI_STATUS GetProcessorInformation | ( | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made.

Parameters
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Returns
Status of MpServices->GetProcessorInfo().
VOID StartupAPsWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN EFI_EVENT | MpEvent
 | ) |  |

Worker function to execute a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | MpEvent | A pointer to the event to be used later to check whether procedure has done.
VOID SwitchNewBsp ( IN UINTN ProcessorNumber )

Worker function to switch the requested AP to be the BSP from that point onward.

Parameters
[in] ProcessorNumber The handle number of AP that is to become the new BSP.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib/PeiRegisterCpuFeaturesLib.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • RegisterCpuFeaturesLib
Functions | Variables
PeiRegisterCpuFeaturesLib.c File Reference

Functions

CPU_FEATURES_DATA * GetCpuFeaturesData (VOID)
EFI_PEI_MP_SERVICES_PPI * | GetMpPpi (VOID)
UINTN | GetProcessorIndex (VOID)
EFI_STATUS | GetProcessorInformation (IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
VOID | StartupAPsWorker (IN EFI_AP_PROCEDURE Procedure, IN EFI_EVENT MpEvent)
VOID | SwitchNewBsp (IN UINTN ProcessorNumber)
VOID | GetNumberOfProcessor (OUT UINTN *NumberOfCpus, OUT UINTN *NumberOfEnabledProcessors)
VOID EFIAPI | CpuFeaturesInitialize (VOID)

Variables

EFI_GUID mRegisterCpuFeaturesHobGuid = REGISTER_CPU_FEATURES_GUID

Detailed Description

CPU Register Table Library functions.

Copyright (c) 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI CpuFeaturesInitialize ( VOID )

Performs CPU features Initialization.

This service will invoke MP service to perform CPU features initialization on BSP/APs per user configuration.

Note
This service could be called by BSP only.
CPU_FEATURES_DATA* GetCpuFeaturesData ( VOID )

Worker function to get CPU_FEATURES_DATA pointer.

Returns
Pointer to CPU_FEATURES_DATA.
EFI_PEI_MP_SERVICES_PPI* GetMpPpi ( VOID )

Worker function to get MP PPI service pointer.

Returns
PEI PPI service pointer.
VOID GetNumberOfProcessor | ( | OUT UINTN * | NumberOfCpus,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

Worker function to retrieve the number of logical processor in the platform.

Parameters
[out] | NumberOfCpus | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
UINTN GetProcessorIndex ( VOID )

Worker function to return processor index.

Returns
The processor index.
EFI_STATUS GetProcessorInformation | ( | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Worker function to MP-related information on the requested processor at the instant this call is made.

Parameters
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Returns
Status of MpServices->GetProcessorInfo().
VOID StartupAPsWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN EFI_EVENT | MpEvent
 | ) |  |

Worker function to execute a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | MpEvent | The Event used to sync the result.
VOID SwitchNewBsp ( IN UINTN ProcessorNumber )

Worker function to switch the requested AP to be the BSP from that point onward.

Parameters
[in] ProcessorNumber The handle number of AP that is to become the new BSP.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeatures.h File Reference

  • File List
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Data Structures | Functions
RegisterCpuFeatures.h File Reference

Data Structures

struct | CPU_FEATURES_INIT_ORDER
struct | CPU_FEATURES_ENTRY
struct | PROGRAM_CPU_REGISTER_FLAGS
struct | CPU_FEATURES_DATA

Functions

CPU_FEATURES_DATA * GetCpuFeaturesData (VOID)
UINTN | GetProcessorIndex (VOID)
EFI_STATUS | GetProcessorInformation (IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
VOID | StartupAPsWorker (IN EFI_AP_PROCEDURE Procedure, IN EFI_EVENT MpEvent)
VOID | GetNumberOfProcessor (OUT UINTN *NumberOfCpus, OUT UINTN *NumberOfEnabledProcessors)
VOID | SwitchNewBsp (IN UINTN ProcessorNumber)
VOID | DumpCpuFeatureMask (IN UINT8 *FeatureMask)
VOID | DumpCpuFeature (IN CPU_FEATURES_ENTRY *CpuFeature)
CPU_FEATURE_DEPENDENCE_TYPE | DetectFeatureScope (IN CPU_FEATURES_ENTRY *CpuFeature, IN BOOLEAN Before, IN UINT8 *NextCpuFeatureMask)
CPU_FEATURE_DEPENDENCE_TYPE | DetectNoneNeighborhoodFeatureScope (IN CPU_FEATURES_ENTRY *CpuFeature, IN BOOLEAN Before, IN LIST_ENTRY *FeatureList)
VOID EFIAPI | SetProcessorRegister (IN OUT VOID *Buffer)
ACPI_CPU_DATA * GetAcpiCpuData (VOID)

Detailed Description

CPU Register Table Library definitions.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

CPU_FEATURE_DEPENDENCE_TYPE DetectFeatureScope | ( | IN CPU_FEATURES_ENTRY * | CpuFeature,
 |  | IN BOOLEAN | Before,
 |  | IN UINT8 * | NextCpuFeatureMask
 | ) |  |

Return feature dependence result.

Parameters
[in] | CpuFeature | Pointer to CPU feature.
[in] | Before | Check before dependence or after.
[in] | NextCpuFeatureMask | Pointer to next CPU feature Mask.
Return values
return the dependence result.
CPU_FEATURE_DEPENDENCE_TYPE DetectNoneNeighborhoodFeatureScope | ( | IN CPU_FEATURES_ENTRY * | CpuFeature,
 |  | IN BOOLEAN | Before,
 |  | IN LIST_ENTRY * | FeatureList
 | ) |  |

Return feature dependence result.

Parameters
[in] | CpuFeature | Pointer to CPU feature.
[in] | Before | Check before dependence or after.
[in] | FeatureList | Pointer to CPU feature list.
Return values
return the dependence result.
VOID DumpCpuFeature ( IN CPU_FEATURES_ENTRY * CpuFeature )

Dump CPU feature name or CPU feature bit mask.

Parameters
[in] CpuFeature Pointer to CPU_FEATURES_ENTRY
VOID DumpCpuFeatureMask ( IN UINT8 * FeatureMask )

Function that uses DEBUG() macros to display the contents of a a CPU feature bit mask.

Parameters
[in] FeatureMask A pointer to the CPU feature bit mask.
ACPI_CPU_DATA* GetAcpiCpuData ( VOID )

Return ACPI_CPU_DATA data.

Returns
Pointer to ACPI_CPU_DATA data.

Get ACPI CPU data.

CPU_FEATURES_DATA* GetCpuFeaturesData ( VOID )

Worker function to get CPU_FEATURES_DATA pointer.

Returns
Pointer to CPU_FEATURES_DATA.
VOID GetNumberOfProcessor | ( | OUT UINTN * | NumberOfCpus,
 |  | OUT UINTN * | NumberOfEnabledProcessors
 | ) |  |

Worker function to retrieve the number of logical processor in the platform.

Parameters
[out] | NumberOfCpus | Pointer to the total number of logical processors in the system, including the BSP and disabled APs.
[out] | NumberOfEnabledProcessors | Pointer to the number of enabled logical processors that exist in system, including the BSP.
UINTN GetProcessorIndex ( VOID )

Worker function to return processor index.

Returns
The processor index.
EFI_STATUS GetProcessorInformation | ( | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets detailed MP-related information on the requested processor at the instant this call is made.

Parameters
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Returns
Status of MpServices->GetProcessorInfo().

Worker function to MP-related information on the requested processor at the instant this call is made.

Parameters
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Returns
Status of MpServices->GetProcessorInfo().
VOID EFIAPI SetProcessorRegister ( IN OUT VOID * Buffer )

Programs registers for the calling processor.

Parameters
[in,out] Buffer The pointer to private data buffer.
VOID StartupAPsWorker | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN EFI_EVENT | MpEvent
 | ) |  |

Worker function to execute a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | MpEvent | A pointer to the event to be used later to check whether procedure has done.

Worker function to execute a caller provided function on all enabled APs.

Parameters
[in] | Procedure | A pointer to the function to be run on enabled APs of the system.
[in] | MpEvent | The Event used to sync the result.
VOID SwitchNewBsp ( IN UINTN ProcessorNumber )

Worker function to switch the requested AP to be the BSP from that point onward.

Parameters
[in] ProcessorNumber The handle number of AP that is to become the new BSP.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c File Reference

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  • UefiCpuPkg
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Functions
RegisterCpuFeaturesLib.c File Reference

Functions

BOOLEAN | IsCpuFeatureMatch (IN UINT8 *FirstFeatureMask, IN UINT8 *SecondFeatureMask)
VOID | DumpCpuFeatureMask (IN UINT8 *FeatureMask)
VOID | DumpCpuFeature (IN CPU_FEATURES_ENTRY *CpuFeature)
BOOLEAN | IsBitMaskMatchCheck (IN UINT8 *FeatureMask, IN UINT8 *DependentBitMask)
BOOLEAN | FindSpecifyFeature (IN LIST_ENTRY *FeatureList, IN LIST_ENTRY *CurrentEntry, IN BOOLEAN SearchFormer, IN UINT8 *FeatureMask)
CPU_FEATURE_DEPENDENCE_TYPE | DetectFeatureScope (IN CPU_FEATURES_ENTRY *CpuFeature, IN BOOLEAN Before, IN UINT8 *NextCpuFeatureMask)
CPU_FEATURE_DEPENDENCE_TYPE | DetectNoneNeighborhoodFeatureScope (IN CPU_FEATURES_ENTRY *CpuFeature, IN BOOLEAN Before, IN LIST_ENTRY *FeatureList)
BOOLEAN | AdjustFeaturesDependence (IN OUT CPU_FEATURES_ENTRY *PreviousFeature, IN OUT CPU_FEATURES_ENTRY *CurrentFeature, IN CPU_FEATURES_ENTRY *FindFeature, IN BOOLEAN Before)
VOID | AdjustEntry (IN LIST_ENTRY *FeatureList, IN OUT LIST_ENTRY *FindEntry, IN OUT LIST_ENTRY *CurrentEntry, IN BOOLEAN Before)
BOOLEAN | InsertToBeforeEntry (IN LIST_ENTRY *FeatureList, IN LIST_ENTRY *CurrentEntry, IN UINT8 *FeatureMask)
BOOLEAN | InsertToAfterEntry (IN LIST_ENTRY *FeatureList, IN LIST_ENTRY *CurrentEntry, IN UINT8 *FeatureMask)
VOID | CheckCpuFeaturesDependency (IN LIST_ENTRY *FeatureList)
RETURN_STATUS | RegisterCpuFeatureWorker (IN CPU_FEATURES_ENTRY *CpuFeature)
VOID | SetCpuFeaturesBitMask (IN UINT8 **FeaturesBitMask, IN UINT32 Feature, IN UINTN BitMaskSize)
RETURN_STATUS EFIAPI | RegisterCpuFeature (IN CHAR8 *FeatureName, OPTIONAL IN CPU_FEATURE_GET_CONFIG_DATA GetConfigDataFunc, OPTIONAL IN CPU_FEATURE_SUPPORT SupportFunc, OPTIONAL IN CPU_FEATURE_INITIALIZE InitializeFunc, OPTIONAL...)
ACPI_CPU_DATA * GetAcpiCpuData (VOID)
STATIC VOID | EnlargeRegisterTable (IN OUT CPU_REGISTER_TABLE *RegisterTable)
VOID | CpuRegisterTableWriteWorker (IN BOOLEAN PreSmmFlag, IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT8 ValidBitStart, IN UINT8 ValidBitLength, IN UINT64 Value)
VOID EFIAPI | CpuRegisterTableWrite (IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value)
VOID EFIAPI | PreSmmCpuRegisterTableWrite (IN UINTN ProcessorNumber, IN REGISTER_TYPE RegisterType, IN UINT64 Index, IN UINT64 ValueMask, IN UINT64 Value)
BOOLEAN | IsCpuFeatureSetInCpuPcd (IN UINT8 *CpuBitMask, IN UINTN CpuBitMaskSize, IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureSupported (IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureInSetting (IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureCapability (IN UINT32 Feature)
BOOLEAN EFIAPI | IsCpuFeatureUserConfiguration (IN UINT32 Feature)
VOID EFIAPI | SwitchBspAfterFeaturesInitialize (IN UINTN ProcessorNumber)

Detailed Description

CPU Register Table Library functions.

Copyright (c) 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID AdjustEntry | ( | IN LIST_ENTRY * | FeatureList,
 |  | IN OUT LIST_ENTRY * | FindEntry,
 |  | IN OUT LIST_ENTRY * | CurrentEntry,
 |  | IN BOOLEAN | Before
 | ) |  |

Base on dependence relationship to asjust feature order.

Parameters
[in] | FeatureList | Pointer to CPU feature list
[in,out] | FindEntry | The entry this feature depend on.
[in,out] | CurrentEntry | The entry for this feature.
[in] | Before | Before or after dependence relationship.
BOOLEAN AdjustFeaturesDependence | ( | IN OUT CPU_FEATURES_ENTRY * | PreviousFeature,
 |  | IN OUT CPU_FEATURES_ENTRY * | CurrentFeature,
 |  | IN CPU_FEATURES_ENTRY * | FindFeature,
 |  | IN BOOLEAN | Before
 | ) |  |

Base on dependence relationship to asjust feature dependence.

ONLY when the feature before(or after) the find feature also has dependence with the find feature. In this case, driver need to base on dependce relationship to decide how to insert current feature and adjust the feature dependence.

Parameters
[in,out] | PreviousFeature | CPU feature current before the find one.
[in,out] | CurrentFeature | Cpu feature need to adjust.
[in] | FindFeature | Cpu feature which current feature depends.
[in] | Before | Before or after dependence relationship.
Return values
TRUE | means the current feature dependence has been adjusted.
FALSE | means the previous feature dependence has been adjusted. or previous feature has no dependence with the find one.
VOID CheckCpuFeaturesDependency ( IN LIST_ENTRY * FeatureList )

Checks and adjusts CPU features order per dependency relationship.

Parameters
[in] FeatureList Pointer to CPU feature list
VOID EFIAPI CpuRegisterTableWrite | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_TYPE | RegisterType,
 |  | IN UINT64 | Index,
 |  | IN UINT64 | ValueMask,
 |  | IN UINT64 | Value
 | ) |  |

Adds an entry in specified register table.

This function adds an entry in specified register table, with given register type, register index, bit section and value.

Parameters
[in] | ProcessorNumber | The index of the CPU to add a register table entry
[in] | RegisterType | Type of the register to program
[in] | Index | Index of the register to program
[in] | ValueMask | Mask of bits in register to write
[in] | Value | Value to write
Note
This service could be called by BSP only.
VOID CpuRegisterTableWriteWorker | ( | IN BOOLEAN | PreSmmFlag,
 |  | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_TYPE | RegisterType,
 |  | IN UINT64 | Index,
 |  | IN UINT8 | ValidBitStart,
 |  | IN UINT8 | ValidBitLength,
 |  | IN UINT64 | Value
 | ) |  |

Add an entry in specified register table.

This function adds an entry in specified register table, with given register type, register index, bit section and value.

Parameters
[in] | PreSmmFlag | If TRUE, entry will be added into PreSmm register table If FALSE, entry will be added into register table
[in] | ProcessorNumber | The index of the CPU to add a register table entry
[in] | RegisterType | Type of the register to program
[in] | Index | Index of the register to program
[in] | ValidBitStart | Start of the bit section
[in] | ValidBitLength | Length of the bit section
[in] | Value | Value to write
CPU_FEATURE_DEPENDENCE_TYPE DetectFeatureScope | ( | IN CPU_FEATURES_ENTRY * | CpuFeature,
 |  | IN BOOLEAN | Before,
 |  | IN UINT8 * | NextCpuFeatureMask
 | ) |  |

Return feature dependence result.

Parameters
[in] | CpuFeature | Pointer to CPU feature.
[in] | Before | Check before dependence or after.
[in] | NextCpuFeatureMask | Pointer to next CPU feature Mask.
Return values
return the dependence result.
CPU_FEATURE_DEPENDENCE_TYPE DetectNoneNeighborhoodFeatureScope | ( | IN CPU_FEATURES_ENTRY * | CpuFeature,
 |  | IN BOOLEAN | Before,
 |  | IN LIST_ENTRY * | FeatureList
 | ) |  |

Return feature dependence result.

Parameters
[in] | CpuFeature | Pointer to CPU feature.
[in] | Before | Check before dependence or after.
[in] | FeatureList | Pointer to CPU feature list.
Return values
return the dependence result.
VOID DumpCpuFeature ( IN CPU_FEATURES_ENTRY * CpuFeature )

Dump CPU feature name or CPU feature bit mask.

Parameters
[in] CpuFeature Pointer to CPU_FEATURES_ENTRY
VOID DumpCpuFeatureMask ( IN UINT8 * FeatureMask )

Function that uses DEBUG() macros to display the contents of a a CPU feature bit mask.

Parameters
[in] FeatureMask A pointer to the CPU feature bit mask.
STATIC VOID EnlargeRegisterTable ( IN OUT CPU_REGISTER_TABLE * RegisterTable )

Enlarges CPU register table for each processor.

Parameters
[in,out] RegisterTable Pointer processor's CPU register table
BOOLEAN FindSpecifyFeature | ( | IN LIST_ENTRY * | FeatureList,
 |  | IN LIST_ENTRY * | CurrentEntry,
 |  | IN BOOLEAN | SearchFormer,
 |  | IN UINT8 * | FeatureMask
 | ) |  |

Try to find the specify cpu featuren in former/after feature list.

Parameters
[in] | FeatureList | Pointer to dependent CPU feature list
[in] | CurrentEntry | Pointer to current CPU feature entry.
[in] | SearchFormer | Find in former feature or after features.
[in] | FeatureMask | Pointer to CPU feature bit mask
Return values
TRUE | The feature bit mask is in dependent CPU feature bit mask buffer.
FALSE | The feature bit mask is not in dependent CPU feature bit mask buffer.
ACPI_CPU_DATA* GetAcpiCpuData ( VOID )

Return ACPI_CPU_DATA data.

Returns
Pointer to ACPI_CPU_DATA data.
BOOLEAN InsertToAfterEntry | ( | IN LIST_ENTRY * | FeatureList,
 |  | IN LIST_ENTRY * | CurrentEntry,
 |  | IN UINT8 * | FeatureMask
 | ) |  |

Checks and adjusts current CPU features per dependency relationship.

Parameters
[in] | FeatureList | Pointer to CPU feature list
[in] | CurrentEntry | Pointer to current checked CPU feature
[in] | FeatureMask | The feature bit mask.
Return values
return Swapped info.
BOOLEAN InsertToBeforeEntry | ( | IN LIST_ENTRY * | FeatureList,
 |  | IN LIST_ENTRY * | CurrentEntry,
 |  | IN UINT8 * | FeatureMask
 | ) |  |

Checks and adjusts current CPU features per dependency relationship.

Parameters
[in] | FeatureList | Pointer to CPU feature list
[in] | CurrentEntry | Pointer to current checked CPU feature
[in] | FeatureMask | The feature bit mask.
Return values
return Swapped info.
BOOLEAN IsBitMaskMatchCheck | ( | IN UINT8 * | FeatureMask,
 |  | IN UINT8 * | DependentBitMask
 | ) |  |

Determines if the feature bit mask is in dependent CPU feature bit mask buffer.

Parameters
[in] | FeatureMask | Pointer to CPU feature bit mask
[in] | DependentBitMask | Pointer to dependent CPU feature bit mask buffer
Return values
TRUE | The feature bit mask is in dependent CPU feature bit mask buffer.
FALSE | The feature bit mask is not in dependent CPU feature bit mask buffer.
BOOLEAN EFIAPI IsCpuFeatureCapability ( IN UINT32 Feature )

Determines if a CPU feature is set in PcdCpuFeaturesCapability bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesCapability
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesCapability.
FALSE | The CPU feature is not set in PcdCpuFeaturesCapability.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI IsCpuFeatureInSetting ( IN UINT32 Feature )

Determines if a CPU feature is set in PcdCpuFeaturesSetting bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesSetting
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSetting.
FALSE | The CPU feature is not set in PcdCpuFeaturesSetting.
Note
This service could be called by BSP only.
BOOLEAN IsCpuFeatureMatch | ( | IN UINT8 * | FirstFeatureMask,
 |  | IN UINT8 * | SecondFeatureMask
 | ) |  |

Checks if two CPU feature bit masks are equal.

Parameters
[in] | FirstFeatureMask | The first input CPU feature bit mask
[in] | SecondFeatureMask | The second input CPU feature bit mask
Return values
TRUE | Two CPU feature bit masks are equal.
FALSE | Two CPU feature bit masks are not equal.
BOOLEAN IsCpuFeatureSetInCpuPcd | ( | IN UINT8 * | CpuBitMask,
 |  | IN UINTN | CpuBitMaskSize,
 |  | IN UINT32 | Feature
 | ) |  |

Worker function to determine if a CPU feature is set in input CPU feature bit mask buffer.

Parameters
[in] | CpuBitMask | CPU feature bit mask buffer
[in] | CpuBitMaskSize | The size of CPU feature bit mask buffer
[in] | Feature | The bit number of the CPU feature
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSupport.
FALSE | The CPU feature is not set in PcdCpuFeaturesSupport.
BOOLEAN EFIAPI IsCpuFeatureSupported ( IN UINT32 Feature )

Determines if a CPU feature is enabled in PcdCpuFeaturesSupport bit mask. If a CPU feature is disabled in PcdCpuFeaturesSupport then all the code/data associated with that feature should be optimized away if compiler optimizations are enabled.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesSupport
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesSupport.
FALSE | The CPU feature is not set in PcdCpuFeaturesSupport.
Note
This service could be called by BSP only.
BOOLEAN EFIAPI IsCpuFeatureUserConfiguration ( IN UINT32 Feature )

Determines if a CPU feature is set in PcdCpuFeaturesUserConfiguration bit mask.

Parameters
[in] Feature The bit number of the CPU feature to check in the PCD PcdCpuFeaturesUserConfiguration
Return values
TRUE | The CPU feature is set in PcdCpuFeaturesUserConfiguration.
FALSE | The CPU feature is not set in PcdCpuFeaturesUserConfiguration.
Note
This service could be called by BSP only.
VOID EFIAPI PreSmmCpuRegisterTableWrite | ( | IN UINTN | ProcessorNumber,
 |  | IN REGISTER_TYPE | RegisterType,
 |  | IN UINT64 | Index,
 |  | IN UINT64 | ValueMask,
 |  | IN UINT64 | Value
 | ) |  |

Adds an entry in specified Pre-SMM register table.

This function adds an entry in specified register table, with given register type, register index, bit section and value.

Parameters
[in] | ProcessorNumber | The index of the CPU to add a register table entry.
[in] | RegisterType | Type of the register to program
[in] | Index | Index of the register to program
[in] | ValueMask | Mask of bits in register to write
[in] | Value | Value to write
Note
This service could be called by BSP only.
RETURN_STATUS EFIAPI RegisterCpuFeature | ( | IN CHAR8 * | FeatureName,
 |  | OPTIONAL IN CPU_FEATURE_GET_CONFIG_DATA | GetConfigDataFunc,
 |  | OPTIONAL IN CPU_FEATURE_SUPPORT | SupportFunc,
 |  | OPTIONAL IN CPU_FEATURE_INITIALIZE | InitializeFunc,
 |  | OPTIONAL... |
 | ) |  |

Registers a CPU Feature.

Parameters
[in] | FeatureName | A Null-terminated Ascii string indicates CPU feature name.
[in] | GetConfigDataFunc | CPU feature get configuration data function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU configuration data for the registered feature is NULL.
[in] | SupportFunc | CPU feature support function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU feature is assumed to be supported by all CPUs.
[in] | InitializeFunc | CPU feature initialize function. This is an optional parameter that may be NULL. If NULL, then the most recently registered function for the CPU feature is used. If no functions are registered for a CPU feature, then the CPU feature initialization is skipped.
[in] ... Variable argument list of UINT32 CPU feature value. Values with no modifiers are the features provided by the registered functions. Values with CPU_FEATURE_BEFORE modifier are features that must be initialized after the features provided by the registered functions are used. Values with CPU_FEATURE_AFTER modifier are features that must be initialized before the features provided by the registered functions are used. The last argument in this variable argument list must always be CPU_FEATURE_END.
Return values
RETURN_SUCCESS | The CPU feature was successfully registered.
RETURN_OUT_OF_RESOURCES | There are not enough resources to register the CPU feature.
RETURN_UNSUPPORTED | Registration of the CPU feature is not supported due to a circular dependency between BEFORE and AFTER features.
RETURN_NOT_READY | CPU feature PCD PcdCpuFeaturesUserConfiguration not updated by Platform driver yet.
Note
This service could be called by BSP only.
RETURN_STATUS RegisterCpuFeatureWorker ( IN CPU_FEATURES_ENTRY * CpuFeature )

Worker function to register CPU Feature.

Parameters
[in] CpuFeature Pointer to CPU feature entry
Return values
RETURN_SUCCESS | The CPU feature was successfully registered.
RETURN_OUT_OF_RESOURCES | There are not enough resources to register the CPU feature.
RETURN_UNSUPPORTED | Registration of the CPU feature is not supported due to a circular dependency between BEFORE and AFTER features.
VOID SetCpuFeaturesBitMask | ( | IN UINT8 ** | FeaturesBitMask,
 |  | IN UINT32 | Feature,
 |  | IN UINTN | BitMaskSize
 | ) |  |

Sets CPU feature bit mask in CPU feature bit mask buffer.

Parameters
[in] | FeaturesBitMask | Pointer to CPU feature bit mask buffer
[in] | Feature | The bit number of the CPU feature
[in] | BitMaskSize | CPU feature bit mask buffer size
VOID EFIAPI SwitchBspAfterFeaturesInitialize ( IN UINTN ProcessorNumber )

Switches to assigned BSP after CPU features initialization.

Parameters
[in] ProcessorNumber The index of the CPU executing this function.
Note
This service could be called by BSP only.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • RegisterCpuFeaturesLib
RegisterCpuFeaturesLib.uni File Reference

Detailed Description

Register CPU Features Library instance.

Register CPU Features Library instance.

Copyright (c) 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu Directory Reference

  • UefiCpuPkg
  • Library
  • SecPeiDxeTimerLibUefiCpu
SecPeiDxeTimerLibUefiCpu Directory Reference

Files

file | SecPeiDxeTimerLibUefiCpu.inf
file | SecPeiDxeTimerLibUefiCpu.uni
file | X86TimerLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.uni File Reference

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  • SecPeiDxeTimerLibUefiCpu
SecPeiDxeTimerLibUefiCpu.uni File Reference

Detailed Description

Instance of Timer Library only using CPU resources.

Timer Library that only uses CPU resources to provide calibrated delays on IA-32, x64, and IPF. Note: A driver of type DXE_RUNTIME_DRIVER and DXE_SMM_DRIVER can use this TimerLib in their initialization without any issues. They only have to be careful in the implementation of runtime services and SMI handlers. Because CPU Local APIC and ITC could be programmed by OS, it cannot be used by SMM drivers and runtime drivers, ACPI timer is recommended for SMM drivers and runtime drivers.

This library differs with the SecPeiDxeTimerLibCpu library in the MdePkg in that it uses the local APIC library so that it supports x2APIC mode.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/X86TimerLib.c File Reference

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Functions
X86TimerLib.c File Reference

Functions

UINT32 EFIAPI | InternalX86GetTimerFrequency (VOID)
VOID EFIAPI | InternalX86Delay (IN UINT32 Delay)
UINTN EFIAPI | MicroSecondDelay (IN UINTN MicroSeconds)
UINTN EFIAPI | NanoSecondDelay (IN UINTN NanoSeconds)
UINT64 EFIAPI | GetPerformanceCounter (VOID)
UINT64 EFIAPI | GetPerformanceCounterProperties (OUT UINT64 *StartValue, OPTIONAL OUT UINT64 *EndValue OPTIONAL)
UINT64 EFIAPI | GetTimeInNanoSecond (IN UINT64 Ticks)

Detailed Description

Timer Library functions built upon local APIC on IA32/x64.

This library uses the local APIC library so that it supports x2APIC mode.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT64 EFIAPI GetPerformanceCounter ( VOID )

Retrieves the current value of a 64-bit free running performance counter.

The counter can either count up by 1 or count down by 1. If the physical performance counter counts by a larger increment, then the counter values must be translated. The properties of the counter can be retrieved from GetPerformanceCounterProperties().

Returns
The current value of the free running performance counter.
UINT64 EFIAPI GetPerformanceCounterProperties | ( | OUT UINT64 * | StartValue,
 |  | OPTIONAL OUT UINT64 *EndValue | OPTIONAL
 | ) |  |

Retrieves the 64-bit frequency in Hz and the range of performance counter values.

If StartValue is not NULL, then the value that the performance counter starts with immediately after is it rolls over is returned in StartValue. If EndValue is not NULL, then the value that the performance counter end with immediately before it rolls over is returned in EndValue. The 64-bit frequency of the performance counter in Hz is always returned. If StartValue is less than EndValue, then the performance counter counts up. If StartValue is greater than EndValue, then the performance counter counts down. For example, a 64-bit free running counter that counts up would have a StartValue of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.

Parameters
StartValue | The value the performance counter starts with when it rolls over.
EndValue | The value that the performance counter ends with before it rolls over.
Returns
The frequency in Hz.
UINT64 EFIAPI GetTimeInNanoSecond ( IN UINT64 Ticks )

Converts elapsed ticks of performance counter to time in nanoseconds.

This function converts the elapsed ticks of running performance counter to time value in unit of nanoseconds.

Parameters
Ticks The number of elapsed ticks of running performance counter.
Returns
The elapsed time in nanoseconds.
VOID EFIAPI InternalX86Delay ( IN UINT32 Delay )

Stalls the CPU for at least the given number of ticks.

Stalls the CPU for at least the given number of ticks. It's invoked by MicroSecondDelay() and NanoSecondDelay().

This function will ASSERT if the APIC timer intial count returned from GetApicTimerInitCount() is zero.

Parameters
Delay A period of time to delay in ticks.
UINT32 EFIAPI InternalX86GetTimerFrequency ( VOID )

Internal function to return the frequency of the local APIC timer.

Returns
The frequency of the timer in Hz.
UINTN EFIAPI MicroSecondDelay ( IN UINTN MicroSeconds )

Stalls the CPU for at least the given number of microseconds.

Stalls the CPU for the number of microseconds specified by MicroSeconds.

Parameters
MicroSeconds The minimum number of microseconds to delay.
Returns
The value of MicroSeconds inputted.
UINTN EFIAPI NanoSecondDelay ( IN UINTN NanoSeconds )

Stalls the CPU for at least the given number of nanoseconds.

Stalls the CPU for the number of nanoseconds specified by NanoSeconds.

Parameters
NanoSeconds The minimum number of nanoseconds to delay.
Returns
The value of NanoSeconds inputted.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib Directory Reference

  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
SmmCpuFeaturesLib Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | SmmCpuFeaturesLib.c
file | SmmCpuFeaturesLib.inf
file | SmmCpuFeaturesLib.uni
file | SmmCpuFeaturesLibNoStm.c
file | SmmCpuFeaturesLibStm.inf
file | SmmStm.c
file | SmmStm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32 Directory Reference

  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
  • Ia32
Ia32 Directory Reference

Files

file | SmiEntry.nasm
file | SmiEntry.S
file | SmiException.nasm
file | SmiException.S
file | SmmStmSupport.c
file | StuffRsb.inc
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmmStmSupport.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
  • Ia32
Functions
SmmStmSupport.c File Reference

Functions

VOID | StmGen4GPageTable (IN UINTN PageTableBase)
UINT32 EFIAPI | SmmStmExceptionHandler (IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context)

Detailed Description

SMM STM support functions

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT32 EFIAPI SmmStmExceptionHandler ( IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context )

This is SMM exception handle. Consumed by STM when exception happen.

Parameters
Context STM protection exception stack frame
Returns
the EBX value for STM reference. EBX = 0: resume SMM guest using register state found on exception stack. EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the TXT.ERRORCODE register and subsequently reset the system via TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
VOID StmGen4GPageTable ( IN UINTN PageTableBase )

Create 4G page table for STM. 4M Non-PAE page table in IA32 version.

Parameters
PageTableBase The page table base in MSEG
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/X64 Directory Reference

  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
  • X64
X64 Directory Reference

Files

file | SmiEntry.nasm
file | SmiEntry.S
file | SmiException.nasm
file | SmiException.S
file | SmmStmSupport.c
file | StuffRsb.inc
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmmStmSupport.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
  • X64
Functions
SmmStmSupport.c File Reference

Functions

VOID | StmGen4GPageTable (IN UINTN PageTableBase)
UINT32 EFIAPI | SmmStmExceptionHandler (IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context)

Detailed Description

SMM STM support functions

Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT32 EFIAPI SmmStmExceptionHandler ( IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context )

This is SMM exception handle. Consumed by STM when exception happen.

Parameters
Context STM protection exception stack frame
Returns
the EBX value for STM reference. EBX = 0: resume SMM guest using register state found on exception stack. EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the TXT.ERRORCODE register and subsequently reset the system via TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
VOID StmGen4GPageTable ( IN UINTN PageTableBase )

Create 4G page table for STM. 2M PAE page table in X64 version.

Parameters
PageTableBase The page table base in MSEG
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c File Reference

  • File List
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  • Library
  • SmmCpuFeaturesLib
Data Structures | Functions | Variables
SmmCpuFeaturesLib.c File Reference

Data Structures

struct AMD_X64_FORMAT

Functions

VOID FinishSmmCpuFeaturesInitializeProcessor (VOID)
EFI_STATUS EFIAPI | SmmCpuFeaturesLibConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
VOID EFIAPI | SmmCpuFeaturesInitializeProcessor (IN UINTN CpuIndex, IN BOOLEAN IsMonarch, IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, IN CPU_HOT_PLUG_DATA *CpuHotPlugData)
UINT64 EFIAPI | SmmCpuFeaturesHookReturnFromSmm (IN UINTN CpuIndex, IN SMRAM_SAVE_STATE_MAP *CpuState, IN UINT64 NewInstructionPointer32, IN UINT64 NewInstructionPointer)
VOID EFIAPI | SmmCpuFeaturesSmmRelocationComplete (VOID)
BOOLEAN EFIAPI | SmmCpuFeaturesNeedConfigureMtrrs (VOID)
VOID EFIAPI | SmmCpuFeaturesDisableSmrr (VOID)
VOID EFIAPI | SmmCpuFeaturesReenableSmrr (VOID)
VOID EFIAPI | SmmCpuFeaturesRendezvousEntry (IN UINTN CpuIndex)
VOID EFIAPI | SmmCpuFeaturesRendezvousExit (IN UINTN CpuIndex)
BOOLEAN EFIAPI | SmmCpuFeaturesIsSmmRegisterSupported (IN UINTN CpuIndex, IN SMM_REG_NAME RegName)
UINT64 EFIAPI | SmmCpuFeaturesGetSmmRegister (IN UINTN CpuIndex, IN SMM_REG_NAME RegName)
VOID EFIAPI | SmmCpuFeaturesSetSmmRegister (IN UINTN CpuIndex, IN SMM_REG_NAME RegName, IN UINT64 Value)
EFI_STATUS EFIAPI | SmmCpuFeaturesReadSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, OUT VOID *Buffer)
EFI_STATUS EFIAPI | SmmCpuFeaturesWriteSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer)
VOID EFIAPI | SmmCpuFeaturesCompleteSmmReadyToLock (VOID)
VOID *EFIAPI | SmmCpuFeaturesAllocatePageTableMemory (IN UINTN Pages)

Variables

BOOLEAN | mSmrrSupported = FALSE
BOOLEAN | mSmmFeatureControlSupported = FALSE
UINT32 | mSmrrPhysBaseMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSBASE
UINT32 | mSmrrPhysMaskMsr = SMM_FEATURES_LIB_IA32_SMRR_PHYSMASK
BOOLEAN | mNeedConfigureMtrrs = TRUE
BOOLEAN * | mSmrrEnabled
CPU_HOT_PLUG_DATA | mCpuHotPlugData
AMD_X64_FORMAT | gAmdX64Format []

Detailed Description

The CPU specific programming for PiSmmCpuDxeSmm module.

Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID FinishSmmCpuFeaturesInitializeProcessor ( VOID )

Internal worker function that is called to complete CPU initialization at the end of SmmCpuFeaturesInitializeProcessor().

VOID* EFIAPI SmmCpuFeaturesAllocatePageTableMemory ( IN UINTN Pages )

This API provides a method for a CPU to allocate a specific region for storing page tables.

This API can be called more once to allocate memory for page tables.

Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

This function can also return NULL if there is no preference on where the page tables are allocated in SMRAM.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer for page tables.
Return values
NULL Fail to allocate a specific region for storing page tables, Or there is no preference on where the page tables are allocated in SMRAM.
VOID EFIAPI SmmCpuFeaturesCompleteSmmReadyToLock ( VOID )

This function is hook point called after the gEfiSmmReadyToLockProtocolGuid notification is completely processed.

VOID EFIAPI SmmCpuFeaturesDisableSmrr ( VOID )

Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.

UINT64 EFIAPI SmmCpuFeaturesGetSmmRegister | ( | IN UINTN | CpuIndex,
 |  | IN SMM_REG_NAME | RegName
 | ) |  |

Returns the current value of the SMM register for the specified CPU. If the SMM register is not supported, then 0 is returned.

Parameters
[in] | CpuIndex | The index of the CPU to read the SMM register. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | RegName | Identifies the SMM register to read.
Returns
The value of the SMM register specified by RegName from the CPU specified by CpuIndex.
UINT64 EFIAPI SmmCpuFeaturesHookReturnFromSmm | ( | IN UINTN | CpuIndex,
 |  | IN SMRAM_SAVE_STATE_MAP * | CpuState,
 |  | IN UINT64 | NewInstructionPointer32,
 |  | IN UINT64 | NewInstructionPointer
 | ) |  |

This function updates the SMRAM save state on the currently executing CPU to resume execution at a specific address after an RSM instruction. This function must evaluate the SMRAM save state to determine the execution mode the RSM instruction resumes and update the resume execution address with either NewInstructionPointer32 or NewInstructionPoint. The auto HALT restart flag in the SMRAM save state must always be cleared. This function returns the value of the instruction pointer from the SMRAM save state that was replaced. If this function returns 0, then the SMRAM save state was not modified.

This function is called during the very first SMI on each CPU after SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mode to signal that the SMBASE of each CPU has been updated before the default SMBASE address is used for the first SMI to the next CPU.

Parameters
[in] | CpuIndex | The index of the CPU to hook. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | CpuState | Pointer to SMRAM Save State Map for the currently executing CPU.
[in] | NewInstructionPointer32 | Instruction pointer to use if resuming to 32-bit execution mode from 64-bit SMM.
[in] | NewInstructionPointer | Instruction pointer to use if resuming to same execution mode as SMM.
Return values
0 This function did modify the SMRAM save state.
> 0 The original instruction pointer value from the SMRAM save state before it was replaced.
VOID EFIAPI SmmCpuFeaturesInitializeProcessor | ( | IN UINTN | CpuIndex,
 |  | IN BOOLEAN | IsMonarch,
 |  | IN EFI_PROCESSOR_INFORMATION * | ProcessorInfo,
 |  | IN CPU_HOT_PLUG_DATA * | CpuHotPlugData
 | ) |  |

Called during the very first SMI into System Management Mode to initialize CPU features, including SMBASE, for the currently executing CPU. Since this is the first SMI, the SMRAM Save State Map is at the default address of SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently executing CPU is specified by CpuIndex and CpuIndex can be used to access information about the currently executing CPU in the ProcessorInfo array and the HotPlugCpuData data structure.

Parameters
[in] | CpuIndex | The index of the CPU to initialize. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | IsMonarch | TRUE if the CpuIndex is the index of the CPU that was elected as monarch during System Management Mode initialization. FALSE if the CpuIndex is not the index of the CPU that was elected as monarch during System Management Mode initialization.
[in] | ProcessorInfo | Pointer to an array of EFI_PROCESSOR_INFORMATION structures. ProcessorInfo[CpuIndex] contains the information for the currently executing CPU.
[in] | CpuHotPlugData | Pointer to the CPU_HOT_PLUG_DATA structure that contains the ApidId and SmBase arrays.
BOOLEAN EFIAPI SmmCpuFeaturesIsSmmRegisterSupported | ( | IN UINTN | CpuIndex,
 |  | IN SMM_REG_NAME | RegName
 | ) |  |

Check to see if an SMM register is supported by a specified CPU.

Parameters
[in] | CpuIndex | The index of the CPU to check for SMM register support. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | RegName | Identifies the SMM register to check for support.
Return values
TRUE | The SMM register specified by RegName is supported by the CPU specified by CpuIndex.
FALSE | The SMM register specified by RegName is not supported by the CPU specified by CpuIndex.
EFI_STATUS EFIAPI SmmCpuFeaturesLibConstructor | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The constructor function

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS The constructor always returns EFI_SUCCESS.
BOOLEAN EFIAPI SmmCpuFeaturesNeedConfigureMtrrs ( VOID )

Determines if MTRR registers must be configured to set SMRAM cache-ability when executing in System Management Mode.

Return values
TRUE | MTRR registers must be configured to set SMRAM cache-ability.
FALSE | MTRR registers do not need to be configured to set SMRAM cache-ability.
EFI_STATUS EFIAPI SmmCpuFeaturesReadSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | OUT VOID * | Buffer
 | ) |  |

Read an SMM Save State register on the target processor. If this function returns EFI_UNSUPPORTED, then the caller is responsible for reading the SMM Save Sate register.

Parameters
[in] | CpuIndex | The index of the CPU to read the SMM Save State. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | Register | The SMM Save State register to read.
[in] | Width | The number of bytes to read from the CPU save state.
[out] | Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State.
EFI_INVALID_PARAMTER | Buffer is NULL.
EFI_UNSUPPORTED | This function does not support reading Register.
VOID EFIAPI SmmCpuFeaturesReenableSmrr ( VOID )

Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigureMtrrs() returns TRUE.

VOID EFIAPI SmmCpuFeaturesRendezvousEntry ( IN UINTN CpuIndex )

Processor specific hook point each time a CPU enters System Management Mode.

Parameters
[in] CpuIndex The index of the CPU that has entered SMM. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
VOID EFIAPI SmmCpuFeaturesRendezvousExit ( IN UINTN CpuIndex )

Processor specific hook point each time a CPU exits System Management Mode.

Parameters
[in] CpuIndex The index of the CPU that is exiting SMM. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
VOID EFIAPI SmmCpuFeaturesSetSmmRegister | ( | IN UINTN | CpuIndex,
 |  | IN SMM_REG_NAME | RegName,
 |  | IN UINT64 | Value
 | ) |  |

Sets the value of an SMM register on a specified CPU. If the SMM register is not supported, then no action is performed.

Parameters
[in] | CpuIndex | The index of the CPU to write the SMM register. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | RegName | Identifies the SMM register to write. registers are read-only.
[in] | Value | The value to write to the SMM register.
VOID EFIAPI SmmCpuFeaturesSmmRelocationComplete ( VOID )

Hook point in normal execution mode that allows the one CPU that was elected as monarch during System Management Mode initialization to perform additional initialization actions immediately after all of the CPUs have processed their first SMI and called SmmCpuFeaturesInitializeProcessor() relocating SMBASE into a buffer in SMRAM and called SmmCpuFeaturesHookReturnFromSmm().

EFI_STATUS EFIAPI SmmCpuFeaturesWriteSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | IN CONST VOID * | Buffer
 | ) |  |

Writes an SMM Save State register on the target processor. If this function returns EFI_UNSUPPORTED, then the caller is responsible for writing the SMM Save Sate register.

Parameters
[in] | CpuIndex | The index of the CPU to write the SMM Save State. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | Register | The SMM Save State register to write.
[in] | Width | The number of bytes to write to the CPU save state.
[in] | Buffer | Upon entry, this holds the new CPU register value.
Return values
EFI_SUCCESS | The register was written to Save State.
EFI_INVALID_PARAMTER | Buffer is NULL.
EFI_UNSUPPORTED | This function does not support writing Register.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
SmmCpuFeaturesLib.uni File Reference

Detailed Description

The CPU specific programming for PiSmmCpuDxeSmm module.

Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibNoStm.c File Reference

  • File List
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Functions
SmmCpuFeaturesLibNoStm.c File Reference

Functions

VOID FinishSmmCpuFeaturesInitializeProcessor (VOID)
UINTN EFIAPI | SmmCpuFeaturesGetSmiHandlerSize (VOID)
VOID EFIAPI | SmmCpuFeaturesInstallSmiHandler (IN UINTN CpuIndex, IN UINT32 SmBase, IN VOID *SmiStack, IN UINTN StackSize, IN UINTN GdtBase, IN UINTN GdtSize, IN UINTN IdtBase, IN UINTN IdtSize, IN UINT32 Cr3)

Detailed Description

The CPU specific programming for PiSmmCpuDxeSmm module when STM support is not included.

Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID FinishSmmCpuFeaturesInitializeProcessor ( VOID )

Internal worker function that is called to complete CPU initialization at the end of SmmCpuFeaturesInitializeProcessor().

UINTN EFIAPI SmmCpuFeaturesGetSmiHandlerSize ( VOID )

Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is returned, then a custom SMI handler is not provided by this library, and the default SMI handler must be used.

Return values
0 Use the default SMI handler.
> 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler() The caller is required to allocate enough SMRAM for each CPU to support the size of the custom SMI handler.
VOID EFIAPI SmmCpuFeaturesInstallSmiHandler | ( | IN UINTN | CpuIndex,
 |  | IN UINT32 | SmBase,
 |  | IN VOID * | SmiStack,
 |  | IN UINTN | StackSize,
 |  | IN UINTN | GdtBase,
 |  | IN UINTN | GdtSize,
 |  | IN UINTN | IdtBase,
 |  | IN UINTN | IdtSize,
 |  | IN UINT32 | Cr3
 | ) |  |

Install a custom SMI handler for the CPU specified by CpuIndex. This function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater than zero and is called by the CPU that was elected as monarch during System Management Mode initialization.

Parameters
[in] | CpuIndex | The index of the CPU to install the custom SMI handler. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | SmBase | The SMBASE address for the CPU specified by CpuIndex.
[in] | SmiStack | The stack to use when an SMI is processed by the the CPU specified by CpuIndex.
[in] | StackSize | The size, in bytes, if the stack used when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtBase | The base address of the GDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtSize | The size, in bytes, of the GDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtBase | The base address of the IDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtSize | The size, in bytes, of the IDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | Cr3 | The base address of the page tables to use when an SMI is processed by the CPU specified by CpuIndex.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.c File Reference

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  • SmmCpuFeaturesLib
Functions | Variables
SmmStm.c File Reference

Functions

EFI_STATUS EFIAPI | SmmCpuFeaturesLibConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
EFI_STATUS EFIAPI | SmmCpuFeaturesLibStmConstructor (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
VOID FinishSmmCpuFeaturesInitializeProcessor (VOID)
UINTN EFIAPI | SmmCpuFeaturesGetSmiHandlerSize (VOID)
VOID EFIAPI | SmmCpuFeaturesInstallSmiHandler (IN UINTN CpuIndex, IN UINT32 SmBase, IN VOID *SmiStack, IN UINTN StackSize, IN UINTN GdtBase, IN UINTN GdtSize, IN UINTN IdtBase, IN UINTN IdtSize, IN UINT32 Cr3)
EFI_STATUS EFIAPI | SmmEndOfDxeEventNotify (IN CONST EFI_GUID *Protocol, IN VOID *Interface, IN EFI_HANDLE Handle)
VOID StmSmmConfigurationTableInit (VOID)
EFI_SM_MONITOR_STATE EFIAPI | GetMonitorState (VOID)
BOOLEAN | HandleSingleResource (IN STM_RSC *Resource, IN STM_RSC *Record)
VOID | AddSingleResource (IN STM_RSC *Resource)
VOID | AddResource (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
BOOLEAN | ValidateResource (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
UINTN | GetResourceSize (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
EFI_STATUS EFIAPI | AddPiResource (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
EFI_STATUS EFIAPI | DeletePiResource (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
EFI_STATUS EFIAPI | GetPiResource (OUT STM_RSC *ResourceList, IN OUT UINT32 *ResourceSize)
VOID EFIAPI | EnableMsegMsr (IN VOID *Buffer)
UINT32 | GetVmcsSize (VOID)
BOOLEAN | StmCheckStmImage (IN EFI_PHYSICAL_ADDRESS StmImage, IN UINTN StmImageSize)
VOID | StmLoadStmImage (IN EFI_PHYSICAL_ADDRESS StmImage, IN UINTN StmImageSize)
EFI_STATUS EFIAPI | LoadMonitor (IN EFI_PHYSICAL_ADDRESS StmImage, IN UINTN StmImageSize)
VOID * GetStmResource (VOID)
VOID | NotifyStmResourceChange (VOID *StmResource)
VOID EFIAPI | SmmStmSetup (VOID)
VOID EFIAPI | SmmStmTeardown (VOID)

Variables

EFI_HANDLE | mStmSmmCpuHandle = NULL
BOOLEAN | mLockLoadMonitor = FALSE
GLOBAL_REMOVE_IF_UNREFERENCED
STM_RSC_END 		mRscEndNode
GLOBAL_REMOVE_IF_UNREFERENCED
UINT8 * 		mStmResourcesPtr = NULL
GLOBAL_REMOVE_IF_UNREFERENCED UINTN | mStmResourceTotalSize = 0x0
GLOBAL_REMOVE_IF_UNREFERENCED UINTN | mStmResourceSizeUsed = 0x0
GLOBAL_REMOVE_IF_UNREFERENCED UINTN | mStmResourceSizeAvailable = 0x0
GLOBAL_REMOVE_IF_UNREFERENCED
UINT32 		mStmState = 0
GLOBAL_REMOVE_IF_UNREFERENCED
EFI_SM_MONITOR_INIT_PROTOCOL 		mSmMonitorInitProtocol
CONST TXT_PROCESSOR_SMM_DESCRIPTOR | gcStmPsd
UINT32 | gStmSmbase
volatile UINT32 | gStmSmiStack
UINT32 | gStmSmiCr3
volatile UINT8 | gcStmSmiHandlerTemplate []
CONST UINT16 | gcStmSmiHandlerSize
UINT16 | gcStmSmiHandlerOffset
BOOLEAN | gStmXdSupported
IA32_DESCRIPTOR | gStmSmiHandlerIdtr
EFI_MP_SERVICES_PROTOCOL * | mSmmCpuFeaturesLibMpService = NULL
UINTN | mMsegBase = 0
UINTN | mMsegSize = 0
BOOLEAN | mStmConfigurationTableInitialized = FALSE

Detailed Description

SMM STM support functions

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI AddPiResource | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Add resources in list to database. Allocate new memory areas as needed.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are added
EFI_INVALID_PARAMETER | If nested procedure detected resource failer
EFI_OUT_OF_RESOURCES | If nested procedure returned it and we cannot allocate more areas.
VOID AddResource | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Add resource list.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
VOID AddSingleResource ( IN STM_RSC * Resource )

Add resource node.

Parameters
Resource A pointer to resource node to be added
EFI_STATUS EFIAPI DeletePiResource | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Delete resources in list to database.

Parameters
ResourceList | A pointer to resource list to be deleted NULL means delete all resources.
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are deleted
EFI_INVALID_PARAMETER | If nested procedure detected resource failer
VOID EFIAPI EnableMsegMsr ( IN VOID * Buffer )

Set valid bit for MSEG MSR.

Parameters
Buffer Ap function buffer. (not used)
VOID FinishSmmCpuFeaturesInitializeProcessor ( VOID )

Internal worker function that is called to complete CPU initialization at the end of SmmCpuFeaturesInitializeProcessor().

EFI_SM_MONITOR_STATE EFIAPI GetMonitorState ( VOID )

Get STM state.

Returns
STM state
EFI_STATUS EFIAPI GetPiResource | ( | OUT STM_RSC * | ResourceList,
 |  | IN OUT UINT32 * | ResourceSize
 | ) |  |

Get BIOS resources.

Parameters
ResourceList | A pointer to resource list to be filled
ResourceSize | On input it means size of resource list input. On output it means size of resource list filled, or the size of resource list to be filled if size of too small.
Return values
EFI_SUCCESS | If resources are returned.
EFI_BUFFER_TOO_SMALL | If resource list buffer is too small to hold the whole resources.
UINTN GetResourceSize | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Get resource list. EndResource is excluded.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
TRUE | resource valid
FALSE | resource invalid
VOID* GetStmResource ( VOID )

This function return BIOS STM resource. Produced by SmmStm. Comsumed by SmmMpService when Init.

Returns
BIOS STM resource
UINT32 GetVmcsSize ( VOID )

Get 4K page aligned VMCS size.

Returns
4K page aligned VMCS size
BOOLEAN HandleSingleResource | ( | IN STM_RSC * | Resource,
 |  | IN STM_RSC * | Record
 | ) |  |

Handle single Resource to see if it can be merged into Record.

Parameters
Resource | A pointer to resource node to be added
Record | A pointer to record node to be merged
Return values
TRUE | resource handled
FALSE | resource is not handled
EFI_STATUS EFIAPI LoadMonitor | ( | IN EFI_PHYSICAL_ADDRESS | StmImage,
 |  | IN UINTN | StmImageSize
 | ) |  |

Load STM image to MSEG.

Parameters
StmImage | STM image
StmImageSize | STM image size
Return values
EFI_SUCCESS | Load STM to MSEG successfully
EFI_ALREADY_STARTED | STM image is already loaded to MSEG
EFI_BUFFER_TOO_SMALL | MSEG is smaller than minimal requirement of STM image
EFI_UNSUPPORTED | MSEG is not enabled
VOID NotifyStmResourceChange ( VOID * StmResource )

This function notify STM resource change.

Parameters
StmResource BIOS STM resource
UINTN EFIAPI SmmCpuFeaturesGetSmiHandlerSize ( VOID )

Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is returned, then a custom SMI handler is not provided by this library, and the default SMI handler must be used.

Return values
0 Use the default SMI handler.
> 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHandler() The caller is required to allocate enough SMRAM for each CPU to support the size of the custom SMI handler.
VOID EFIAPI SmmCpuFeaturesInstallSmiHandler | ( | IN UINTN | CpuIndex,
 |  | IN UINT32 | SmBase,
 |  | IN VOID * | SmiStack,
 |  | IN UINTN | StackSize,
 |  | IN UINTN | GdtBase,
 |  | IN UINTN | GdtSize,
 |  | IN UINTN | IdtBase,
 |  | IN UINTN | IdtSize,
 |  | IN UINT32 | Cr3
 | ) |  |

Install a custom SMI handler for the CPU specified by CpuIndex. This function is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is greater than zero and is called by the CPU that was elected as monarch during System Management Mode initialization.

Parameters
[in] | CpuIndex | The index of the CPU to install the custom SMI handler. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | SmBase | The SMBASE address for the CPU specified by CpuIndex.
[in] | SmiStack | The stack to use when an SMI is processed by the the CPU specified by CpuIndex.
[in] | StackSize | The size, in bytes, if the stack used when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtBase | The base address of the GDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtSize | The size, in bytes, of the GDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtBase | The base address of the IDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtSize | The size, in bytes, of the IDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | Cr3 | The base address of the page tables to use when an SMI is processed by the CPU specified by CpuIndex.
EFI_STATUS EFIAPI SmmCpuFeaturesLibConstructor | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The constructor function

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS The constructor always returns EFI_SUCCESS.
EFI_STATUS EFIAPI SmmCpuFeaturesLibStmConstructor | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The constructor function

Parameters
[in] | ImageHandle | The firmware allocated handle for the EFI image.
[in] | SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS The constructor always returns EFI_SUCCESS.
EFI_STATUS EFIAPI SmmEndOfDxeEventNotify | ( | IN CONST EFI_GUID * | Protocol,
 |  | IN VOID * | Interface,
 |  | IN EFI_HANDLE | Handle
 | ) |  |

SMM End Of Dxe event notification handler.

STM support need patch AcpiRsdp in TXT_PROCESSOR_SMM_DESCRIPTOR.

Parameters
[in] | Protocol | Points to the protocol's unique identifier.
[in] | Interface | Points to the interface instance.
[in] | Handle | The handle on which the interface was installed.
Return values
EFI_SUCCESS Notification handler runs successfully.
VOID EFIAPI SmmStmSetup ( VOID )

This is STM setup BIOS callback.

VOID EFIAPI SmmStmTeardown ( VOID )

This is STM teardown BIOS callback.

BOOLEAN StmCheckStmImage | ( | IN EFI_PHYSICAL_ADDRESS | StmImage,
 |  | IN UINTN | StmImageSize
 | ) |  |

Check STM image size.

Parameters
StmImage | STM image
StmImageSize | STM image size
Return values
TRUE | check pass
FALSE | check fail
VOID StmLoadStmImage | ( | IN EFI_PHYSICAL_ADDRESS | StmImage,
 |  | IN UINTN | StmImageSize
 | ) |  |

Load STM image to MSEG.

Parameters
StmImage | STM image
StmImageSize | STM image size
VOID StmSmmConfigurationTableInit ( VOID )

This function initializes the STM configuration table.

BOOLEAN ValidateResource | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Validate resource list.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
TRUE | resource valid
FALSE | resource invalid

Variable Documentation

GLOBAL_REMOVE_IF_UNREFERENCED STM_RSC_END mRscEndNode
Initial value:
= {
{END_OF_RESOURCES, sizeof (STM_RSC_END)},
}
STM_RSC_END
Definition: StmResourceDescriptor.h:53
GLOBAL_REMOVE_IF_UNREFERENCED EFI_SM_MONITOR_INIT_PROTOCOL mSmMonitorInitProtocol
Initial value:
= {
LoadMonitor,
AddPiResource,
DeletePiResource,
GetPiResource,
GetMonitorState,
}
GetMonitorState
EFI_SM_MONITOR_STATE EFIAPI GetMonitorState(VOID)
Definition: SmmStm.c:473
GetPiResource
EFI_STATUS EFIAPI GetPiResource(OUT STM_RSC *ResourceList, IN OUT UINT32 *ResourceSize)
Definition: SmmStm.c:1024
LoadMonitor
EFI_STATUS EFIAPI LoadMonitor(IN EFI_PHYSICAL_ADDRESS StmImage, IN UINTN StmImageSize)
Definition: SmmStm.c:1205
DeletePiResource
EFI_STATUS EFIAPI DeletePiResource(IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
Definition: SmmStm.c:990
AddPiResource
EFI_STATUS EFIAPI AddPiResource(IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
Definition: SmmStm.c:883
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmStm.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • SmmCpuFeaturesLib
Functions
SmmStm.h File Reference

Functions

VOID | StmGen4GPageTable (IN UINTN PageTableBase)
UINT32 EFIAPI | SmmStmExceptionHandler (IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context)
EFI_SM_MONITOR_STATE EFIAPI | GetMonitorState (VOID)
EFI_STATUS EFIAPI | LoadMonitor (IN EFI_PHYSICAL_ADDRESS StmImage, IN UINTN StmImageSize)
EFI_STATUS EFIAPI | AddPiResource (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
EFI_STATUS EFIAPI | DeletePiResource (IN STM_RSC *ResourceList, IN UINT32 NumEntries OPTIONAL)
EFI_STATUS EFIAPI | GetPiResource (OUT STM_RSC *ResourceList, IN OUT UINT32 *ResourceSize)
VOID StmSmmConfigurationTableInit (VOID)
VOID | NotifyStmResourceChange (IN VOID *StmResource)
VOID * GetStmResource (VOID)
VOID EFIAPI | SmmCpuFeaturesLibStmSmiEntryFixupAddress ()

Detailed Description

SMM STM support

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php.

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI AddPiResource | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Add resources in list to database. Allocate new memory areas as needed.

Parameters
ResourceList | A pointer to resource list to be added
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are added
EFI_INVALID_PARAMETER | If nested procedure detected resource failer
EFI_OUT_OF_RESOURCES | If nested procedure returned it and we cannot allocate more areas.
EFI_STATUS EFIAPI DeletePiResource | ( | IN STM_RSC * | ResourceList,
 |  | IN UINT32 NumEntries | OPTIONAL
 | ) |  |

Delete resources in list to database.

Parameters
ResourceList | A pointer to resource list to be deleted NULL means delete all resources.
NumEntries | Optional number of entries. If 0, list must be terminated by END_OF_RESOURCES.
Return values
EFI_SUCCESS | If resources are deleted
EFI_INVALID_PARAMETER | If nested procedure detected resource failer
EFI_SM_MONITOR_STATE EFIAPI GetMonitorState ( VOID )

Get STM state.

Returns
STM state
EFI_STATUS EFIAPI GetPiResource | ( | OUT STM_RSC * | ResourceList,
 |  | IN OUT UINT32 * | ResourceSize
 | ) |  |

Get BIOS resources.

Parameters
ResourceList | A pointer to resource list to be filled
ResourceSize | On input it means size of resource list input. On output it means size of resource list filled, or the size of resource list to be filled if size of too small.
Return values
EFI_SUCCESS | If resources are returned.
EFI_BUFFER_TOO_SMALL | If resource list buffer is too small to hold the whole resources.
VOID* GetStmResource ( VOID )

This function return BIOS STM resource.

Returns
BIOS STM resource

This function return BIOS STM resource. Produced by SmmStm. Comsumed by SmmMpService when Init.

Returns
BIOS STM resource
EFI_STATUS EFIAPI LoadMonitor | ( | IN EFI_PHYSICAL_ADDRESS | StmImage,
 |  | IN UINTN | StmImageSize
 | ) |  |

Load STM image to MSEG.

Parameters
StmImage | STM image
StmImageSize | STM image size
Return values
EFI_SUCCESS | Load STM to MSEG successfully
EFI_BUFFER_TOO_SMALL | MSEG is smaller than minimal requirement of STM image

Load STM image to MSEG.

Parameters
StmImage | STM image
StmImageSize | STM image size
Return values
EFI_SUCCESS | Load STM to MSEG successfully
EFI_ALREADY_STARTED | STM image is already loaded to MSEG
EFI_BUFFER_TOO_SMALL | MSEG is smaller than minimal requirement of STM image
EFI_UNSUPPORTED | MSEG is not enabled
VOID NotifyStmResourceChange ( IN VOID * StmResource )

This function notify STM resource change.

Parameters
StmResource BIOS STM resource
VOID EFIAPI SmmCpuFeaturesLibStmSmiEntryFixupAddress ( )

This function fixes up the address of the global variable or function referred in SmiEntry assembly files to be the absoute address.

UINT32 EFIAPI SmmStmExceptionHandler ( IN OUT STM_PROTECTION_EXCEPTION_STACK_FRAME Context )

This is SMM exception handle. Consumed by STM when exception happen.

Parameters
Context STM protection exception stack frame
Returns
the EBX value for STM reference. EBX = 0: resume SMM guest using register state found on exception stack. EBX = 1 to 0x0F: EBX contains a BIOS error code which the STM must record in the TXT.ERRORCODE register and subsequently reset the system via TXT.CMD.SYS_RESET. The value of the TXT.ERRORCODE register is calculated as follows: TXT.ERRORCODE = (EBX & 0x0F) | STM_CRASH_BIOS_PANIC EBX = 0x10 to 0xFFFFFFFF - reserved, do not use.
VOID StmGen4GPageTable ( IN UINTN PageTableBase )

Create 4G page table for STM. 2M PAE page table in X64 version.

Parameters
PageTableBase The page table base in MSEG

Create 4G page table for STM. 4M Non-PAE page table in IA32 version.

Parameters
PageTableBase The page table base in MSEG
VOID StmSmmConfigurationTableInit ( VOID )

This functin initialize STM configuration table.

This function initializes the STM configuration table.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuPlatformHookLibNull Directory Reference

  • UefiCpuPkg
  • Library
  • SmmCpuPlatformHookLibNull
SmmCpuPlatformHookLibNull Directory Reference

Files

file | SmmCpuPlatformHookLibNull.c
file | SmmCpuPlatformHookLibNull.inf
file | SmmCpuPlatformHookLibNull.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • SmmCpuPlatformHookLibNull
Functions
SmmCpuPlatformHookLibNull.c File Reference

Functions

BOOLEAN EFIAPI | PlatformValidSmi (VOID)
BOOLEAN EFIAPI | ClearTopLevelSmiStatus (VOID)
EFI_STATUS EFIAPI | PlatformSmmBspElection (OUT BOOLEAN *IsBsp)
EFI_STATUS EFIAPI | GetPlatformPageTableAttribute (IN UINT64 Address, IN OUT SMM_PAGE_SIZE_TYPE *PageSize, IN OUT UINTN *NumOfPages, IN OUT UINTN *PageAttribute)

Detailed Description

SMM CPU Platform Hook NULL library instance.

Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

BOOLEAN EFIAPI ClearTopLevelSmiStatus ( VOID )

Clears platform top level SMI status bit.

This function clears platform top level SMI status bit.

Return values
TRUE | The platform top level SMI status is cleared.
FALSE | The platform top level SMI status cannot be cleared.
EFI_STATUS EFIAPI GetPlatformPageTableAttribute | ( | IN UINT64 | Address,
 |  | IN OUT SMM_PAGE_SIZE_TYPE * | PageSize,
 |  | IN OUT UINTN * | NumOfPages,
 |  | IN OUT UINTN * | PageAttribute
 | ) |  |

Get platform page table attribute.

This function gets page table attribute of platform.

Parameters
Address | Input parameter. Obtain the page table entries attribute on this address.
PageSize | Output parameter. The size of the page.
NumOfPages | Output parameter. Number of page.
PageAttribute | Output parameter. Paging Attributes (WB, UC, etc).
Return values
EFI_SUCCESS | The platform page table attribute from the address is determined.
EFI_UNSUPPORTED | The platform does not support getting page table attribute for the address.
EFI_STATUS EFIAPI PlatformSmmBspElection ( OUT BOOLEAN * IsBsp )

Performs platform specific way of SMM BSP election.

This function performs platform specific way of SMM BSP election.

Parameters
IsBsp Output parameter. TRUE: the CPU this function executes on is elected to be the SMM BSP. FALSE: the CPU this function executes on is to be SMM AP.
Return values
EFI_SUCCESS | The function executes successfully.
EFI_NOT_READY | The function does not determine whether this CPU should be BSP or AP. This may occur if hardware init sequence to enable the determination is yet to be done, or the function chooses not to do BSP election and will let SMM CPU driver to use its default BSP election process.
EFI_DEVICE_ERROR | The function cannot determine whether this CPU should be BSP or AP due to hardware error.
BOOLEAN EFIAPI PlatformValidSmi ( VOID )

Checks if platform produces a valid SMI.

This function checks if platform produces a valid SMI. This function is called at SMM entry to detect if this is a spurious SMI. This function must be implemented in an MP safe way because it is called by multiple CPU threads.

Return values
TRUE | There is a valid SMI
FALSE | There is no valid SMI
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Library
  • SmmCpuPlatformHookLibNull
SmmCpuPlatformHookLibNull.uni File Reference

Detailed Description

SMM CPU Platform Hook NULL library instance.

Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication Directory Reference

  • UefiCpuPkg
  • PiSmmCommunication
PiSmmCommunication Directory Reference

Files

file | PiSmmCommunicationPei.c
file | PiSmmCommunicationPei.inf
file | PiSmmCommunicationPei.uni
file | PiSmmCommunicationPeiExtra.uni
file | PiSmmCommunicationPrivate.h
file | PiSmmCommunicationSmm.c
file | PiSmmCommunicationSmm.inf
file | PiSmmCommunicationSmm.uni
file | PiSmmCommunicationSmmExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCommunication
Data Structures | Typedefs | Functions | Variables
PiSmmCommunicationPei.c File Reference

Data Structures

struct | EFI_SMM_SYSTEM_TABLE2_64
struct | EFI_CONFIGURATION_TABLE64

Typedefs

typedef EFI_SMM_SYSTEM_TABLE2 | EFI_SMM_SYSTEM_TABLE2_64
typedef EFI_CONFIGURATION_TABLE | EFI_CONFIGURATION_TABLE64

Functions

EFI_STATUS EFIAPI | Communicate (IN CONST EFI_PEI_SMM_COMMUNICATION_PPI *This, IN OUT VOID *CommBuffer, IN OUT UINTN *CommSize)
EFI_SMM_COMMUNICATION_CONTEXT * GetCommunicationContext (VOID)
VOID | SetCommunicationContext (IN EFI_SMM_COMMUNICATION_CONTEXT *SmmCommunicationContext)
VOID * | InternalSmstGetVendorTableByGuid (IN UINT64 Signature, IN EFI_SMM_SYSTEM_TABLE2 *Smst, IN EFI_GUID *VendorGuid)
VOID InitCommunicationContext (VOID)
EFI_STATUS EFIAPI | PiSmmCommunicationPeiEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

Variables

EFI_PEI_SMM_COMMUNICATION_PPI | mSmmCommunicationPpi = { Communicate }
EFI_PEI_PPI_DESCRIPTOR | mPpiList

Detailed Description

PiSmmCommunication PEI Driver.

Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI Communicate | ( | IN CONST EFI_PEI_SMM_COMMUNICATION_PPI * | This,
 |  | IN OUT VOID * | CommBuffer,
 |  | IN OUT UINTN * | CommSize
 | ) |  |

Communicates with a registered handler.

This function provides a service to send and receive messages from a registered UEFI service.

Parameters
[in] | This | The EFI_PEI_SMM_COMMUNICATION_PPI instance.
[in,out] | CommBuffer | A pointer to the buffer to convey into SMRAM.
[in,out] | CommSize | The size of the data buffer being passed in.On exit, the size of data being returned. Zero if the handler does not wish to reply with any data.
Return values
EFI_SUCCESS | The message was successfully posted.
EFI_INVALID_PARAMETER | The CommBuffer was NULL.
EFI_NOT_STARTED | The service is NOT started.
EFI_SMM_COMMUNICATION_CONTEXT* GetCommunicationContext ( VOID )

Get SMM communication context.

Returns
SMM communication context.
VOID InitCommunicationContext ( VOID )

Init SMM communication context.

VOID* InternalSmstGetVendorTableByGuid | ( | IN UINT64 | Signature,
 |  | IN EFI_SMM_SYSTEM_TABLE2 * | Smst,
 |  | IN EFI_GUID * | VendorGuid
 | ) |  |

Get VendorTable by VendorGuid in Smst.

Parameters
Signature | Signature of SMM_S3_RESUME_STATE
Smst | SMM system table
VendorGuid | vendor guid
Returns
vendor table.
EFI_STATUS EFIAPI PiSmmCommunicationPeiEntryPoint | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

Entry Point for PI SMM communication PEIM.

Parameters
FileHandle | Handle of the file being invoked.
PeiServices | Pointer to PEI Services table.
Return values
EFI_SUCEESS
Returns
Others Some error occurs.
VOID SetCommunicationContext ( IN EFI_SMM_COMMUNICATION_CONTEXT * SmmCommunicationContext )

Set SMM communication context.

Parameters
SmmCommunicationContext SMM communication context.

Variable Documentation

EFI_PEI_PPI_DESCRIPTOR mPpiList
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiSmmCommunicationPpiGuid,
&mSmmCommunicationPpi
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCommunication
PiSmmCommunicationPei.uni File Reference

Detailed Description

PI SMM Communication PEIM which produces PEI SMM Communication PPI.

This PEIM retrieves the SMM communication context and produces PEI SMM Communication PPIin the S3 boot mode.

Copyright (c) 2010 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPeiExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCommunication
PiSmmCommunicationPeiExtra.uni File Reference

Detailed Description

PiSmmCommunicationPei Localized Strings and Content

Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPrivate.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCommunication
Data Structures
PiSmmCommunicationPrivate.h File Reference

Data Structures

struct EFI_SMM_COMMUNICATION_CONTEXT

Detailed Description

PiSmmCommunication private data structure

Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.c File Reference

  • File List
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Functions | Variables
PiSmmCommunicationSmm.c File Reference

Functions

VOID SetCommunicationContext (VOID)
EFI_STATUS EFIAPI | PiSmmCommunicationHandler (IN EFI_HANDLE DispatchHandle, IN CONST VOID *Context OPTIONAL, IN OUT VOID *CommBuffer OPTIONAL, IN OUT UINTN *CommBufferSize OPTIONAL)
VOID * | AllocateAcpiNvsMemoryBelow4G (IN UINTN Size)
EFI_STATUS EFIAPI | GetSmramInfoByHob (IN OUT EFI_PHYSICAL_ADDRESS *ReservedAddress)
EFI_STATUS EFIAPI | GetSmramInfoByProtocol (IN OUT EFI_PHYSICAL_ADDRESS *ReservedAddress)
VOID InitSmmS3ResumeState (VOID)
EFI_STATUS EFIAPI | PiSmmCommunicationSmmEntryPoint (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)

Variables

EFI_SMM_COMMUNICATION_CONTEXT mSmmCommunicationContext

Detailed Description

PiSmmCommunication SMM Driver.

Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* AllocateAcpiNvsMemoryBelow4G ( IN UINTN Size )

Allocate EfiACPIMemoryNVS below 4G memory address.

This function allocates EfiACPIMemoryNVS below 4G memory address.

Parameters
Size Size of memory to allocate.
Returns
Allocated address for output.
EFI_STATUS EFIAPI GetSmramInfoByHob ( IN OUT EFI_PHYSICAL_ADDRESS * ReservedAddress )

Get SMRAM information form HOB(gEfiSmmPeiSmramMemoryReserveGuid).

Parameters
[in] SmmS3ResumeState The information which is saved for SMM S3
Return values
EFI_SUCEESS
Returns
Others Some error occurs.
EFI_STATUS EFIAPI GetSmramInfoByProtocol ( IN OUT EFI_PHYSICAL_ADDRESS * ReservedAddress )

Get SMRAM information form protocol(gEfiSmmAccess2ProtocolGuid).

Parameters
[in] SmmS3ResumeState The information which is saved for SMM S3
Return values
EFI_SUCEESS
Returns
Others Some error occurs.
VOID InitSmmS3ResumeState ( VOID )

Initialize SMM S3 resume state structure used during S3 Resume.

EFI_STATUS EFIAPI PiSmmCommunicationHandler | ( | IN EFI_HANDLE | DispatchHandle,
 |  | IN CONST VOID *Context | OPTIONAL,
 |  | IN OUT VOID *CommBuffer | OPTIONAL,
 |  | IN OUT UINTN *CommBufferSize | OPTIONAL
 | ) |  |

Dispatch function for a Software SMI handler.

Parameters
DispatchHandle | The unique handle assigned to this handler by SmiHandlerRegister().
Context | Points to an optional handler context which was specified when the handler was registered.
CommBuffer | A pointer to a collection of data in memory that will be conveyed from a non-SMM environment into an SMM environment.
CommBufferSize | The size of the CommBuffer.
Return values
EFI_SUCCESS Command is handled successfully.
EFI_STATUS EFIAPI PiSmmCommunicationSmmEntryPoint | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

Entry Point for PI SMM communication SMM driver.

Parameters
[in] | ImageHandle | Image handle of this driver.
[in] | SystemTable | A Pointer to the EFI System Table.
Return values
EFI_SUCEESS
Returns
Others Some error occurs.
VOID SetCommunicationContext ( VOID )

Set SMM communication context.

Variable Documentation

EFI_SMM_COMMUNICATION_CONTEXT mSmmCommunicationContext
Initial value:
= {
SMM_COMMUNICATION_SIGNATURE
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCommunication
PiSmmCommunicationSmm.uni File Reference

Detailed Description

PI SMM Communication SMM driver that saves SMM communication context for use by SMM Communication PEIM in the S3 boot mode.

Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmmExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCommunication
PiSmmCommunicationSmmExtra.uni File Reference

Detailed Description

PiSmmCommunicationSmm Localized Strings and Content

Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm Directory Reference

  • UefiCpuPkg
  • PiSmmCpuDxeSmm
PiSmmCpuDxeSmm Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | CpuS3.c
file | CpuService.c
file | CpuService.h
file | MpService.c
file | PiSmmCpuDxeSmm.c
file | PiSmmCpuDxeSmm.h
file | PiSmmCpuDxeSmm.inf
file | PiSmmCpuDxeSmm.uni
file | PiSmmCpuDxeSmmExtra.uni
file | SmmCpuMemoryManagement.c
file | SmmProfile.c
file | SmmProfile.h
file | SmmProfileInternal.h
file | SmramSaveState.c
file | SyncTimer.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/Ia32 Directory Reference

  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • Ia32
Ia32 Directory Reference

Files

file | MpFuncs.nasm
file | PageTbl.c
file | Semaphore.c
file | SmiEntry.nasm
file | SmiException.nasm
file | SmmFuncsArch.c
file | SmmInit.nasm
file | SmmProfileArch.c
file | SmmProfileArch.h
file | StuffRsb.inc
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c File Reference

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  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • Ia32
Functions
PageTbl.c File Reference

Functions

UINT32 | SmmInitPageTable (VOID)
VOID SmiDefaultPFHandler (VOID)
VOID EFIAPI | SmiPFHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID SetPageTableAttributes (VOID)

Detailed Description

Page table manipulation functions for IA-32 processors

Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID SetPageTableAttributes ( VOID )

This function sets memory attribute for page table.

VOID SmiDefaultPFHandler ( VOID )

Page Fault handler for SMM use.

VOID EFIAPI SmiPFHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

ThePage Fault handler wrapper for SMM use.

Parameters
InterruptType | Defines the type of interrupt or exception that occurred on the processor.This parameter is processor architecture specific.
SystemContext | A pointer to the processor context when the interrupt occurred on the processor.
UINT32 SmmInitPageTable ( VOID )

Create PageTable for SMM use.

Returns
PageTable Address
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/Semaphore.c File Reference

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Functions | Variables
Semaphore.c File Reference

Functions

VOID SemaphoreHook (IN UINTN CpuIndex, IN volatile BOOLEAN *RebasedFlag)

Variables

UINTN | mSmmRelocationOriginalAddress
volatile BOOLEAN * | mRebasedFlag

Detailed Description

Semaphore mechanism to indicate to the BSP that an AP has exited SMM after SMBASE relocation.

Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID SemaphoreHook | ( | IN UINTN | CpuIndex,
 |  | IN volatile BOOLEAN * | RebasedFlag
 | ) |  |

Hook return address of SMM Save State so that semaphore code can be executed immediately after AP exits SMM to indicate to the BSP that an AP has exited SMM after SMBASE relocation.

Parameters
[in] | CpuIndex | The processor index.
[in] | RebasedFlag | A pointer to a flag that is set to TRUE immediately after AP exits SMM.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmFuncsArch.c File Reference

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  • Ia32
Functions | Variables
SmmFuncsArch.c File Reference

Functions

VOID EFIAPI | InitializeIDTSmmStackGuard (VOID)
VOID * | InitGdt (IN UINTN Cr3, OUT UINTN *GdtStepSize)
VOID | TransferApToSafeState (IN UINTN ApHltLoopCode, IN UINTN TopOfStack, IN UINTN NumberToFinishAddress)

Variables

UINT64 | gTaskGateDescriptor
EFI_PHYSICAL_ADDRESS | mGdtBuffer
UINTN | mGdtBufferSize

Detailed Description

SMM CPU misc functions for Ia32 arch specific.

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* InitGdt | ( | IN UINTN | Cr3,
 |  | OUT UINTN * | GdtStepSize
 | ) |  |

Initialize Gdt for all processors.

Parameters
[in] | Cr3 | CR3 value.
[out] | GdtStepSize | The step size for GDT table.
Returns
GdtBase for processor 0. GdtBase for processor X is: GdtBase + (GdtStepSize * X)
VOID EFIAPI InitializeIDTSmmStackGuard ( VOID )

Initialize IDT for SMM Stack Guard.

VOID TransferApToSafeState | ( | IN UINTN | ApHltLoopCode,
 |  | IN UINTN | TopOfStack,
 |  | IN UINTN | NumberToFinishAddress
 | ) |  |

Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.

Parameters
[in] | ApHltLoopCode | The address of the safe hlt-loop function.
[in] | TopOfStack | A pointer to the new stack to use for the ApHltLoopCode.
[in] | NumberToFinishAddress | Address of Semaphore of APs finish count.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.c File Reference

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Functions
SmmProfileArch.c File Reference

Functions

VOID InitSmmS3Cr3 (VOID)
VOID InitPagesForPFHandler (VOID)
VOID | RestorePageTableAbove4G (UINT64 *PageTable, UINT64 PFAddress, UINTN CpuIndex, UINTN ErrorCode, BOOLEAN *IsValidPFAddress)
VOID | ClearTrapFlag (IN OUT EFI_SYSTEM_CONTEXT SystemContext)

Detailed Description

IA-32 processor specific functions to enable SMM profile.

Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID ClearTrapFlag ( IN OUT EFI_SYSTEM_CONTEXT SystemContext )

Clear TF in FLAGS.

Parameters
SystemContext A pointer to the processor context when the interrupt occurred on the processor.
VOID InitPagesForPFHandler ( VOID )

Allocate pages for creating 4KB-page based on 2MB-page when page fault happens. 32-bit firmware does not need it.

VOID InitSmmS3Cr3 ( VOID )

Create SMM page table for S3 path.

VOID RestorePageTableAbove4G | ( | UINT64 * | PageTable,
 |  | UINT64 | PFAddress,
 |  | UINTN | CpuIndex,
 |  | UINTN | ErrorCode,
 |  | BOOLEAN * | IsValidPFAddress
 | ) |  |

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception. 32-bit firmware does not need it.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
IsValidPFAddress | The flag indicates if SMM profile data need be added.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmProfileArch.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • Ia32
Data Structures | Typedefs | Functions
SmmProfileArch.h File Reference

Data Structures

struct | _MSR_DS_AREA_STRUCT
struct | _BRANCH_TRACE_RECORD
struct | _PEBS_RECORD

Typedefs

typedef struct _MSR_DS_AREA_STRUCT | MSR_DS_AREA_STRUCT
typedef struct _BRANCH_TRACE_RECORD | BRANCH_TRACE_RECORD
typedef struct _PEBS_RECORD | PEBS_RECORD

Functions

VOID RestorePageTableAbove4G (UINT64 *PageTable, UINT64 PFAddress, UINTN CpuIndex, UINTN ErrorCode, BOOLEAN *IsValidPFAddress)
VOID InitSmmS3Cr3 (VOID)
VOID InitPagesForPFHandler (VOID)

Detailed Description

IA-32 processor specific header file to enable SMM profile.

Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID InitPagesForPFHandler ( VOID )

Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.

Allocate pages for creating 4KB-page based on 2MB-page when page fault happens. 32-bit firmware does not need it.

VOID InitSmmS3Cr3 ( VOID )

Create SMM page table for S3 path.

VOID RestorePageTableAbove4G | ( | UINT64 * | PageTable,
 |  | UINT64 | PFAddress,
 |  | UINTN | CpuIndex,
 |  | UINTN | ErrorCode,
 |  | BOOLEAN * | IsValidPFAddress
 | ) |  |

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception. 32-bit firmware does not need it.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
IsValidPFAddress | The flag indicates if SMM profile data need be added.

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
IsValidPFAddress | The flag indicates if SMM profile data need be added.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/X64 Directory Reference

  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • X64
X64 Directory Reference

Files

file | MpFuncs.nasm
file | PageTbl.c
file | Semaphore.c
file | SmiEntry.nasm
file | SmiException.nasm
file | SmiRendezvous.nasm
file | SmmFuncsArch.c
file | SmmInit.nasm
file | SmmProfileArch.c
file | SmmProfileArch.h
file | StuffRsb.inc
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c File Reference

  • File List
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  • PiSmmCpuDxeSmm
  • X64
Functions | Variables
PageTbl.c File Reference

Functions

BOOLEAN | Is1GPageSupport (VOID)
VOID | SetSubEntriesNum (IN OUT UINT64 *Entry, IN UINT64 SubEntryNum)
UINT64 | GetSubEntriesNum (IN UINT64 *Entry)
UINT8 | CalculateMaximumSupportAddress (VOID)
VOID | SetStaticPageTable (IN UINTN PageTable)
UINT32 | SmmInitPageTable (VOID)
VOID | SetAccNum (IN OUT UINT64 *Entry, IN UINT64 Acc)
UINT64 | GetAccNum (IN UINT64 *Entry)
UINT64 | GetAndUpdateAccNum (IN OUT UINT64 *Entry)
VOID ReclaimPages (VOID)
UINT64 | AllocPage (VOID)
VOID SmiDefaultPFHandler (VOID)
VOID EFIAPI | SmiPFHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID SetPageTableAttributes (VOID)

Variables

LIST_ENTRY | mPagePool = INITIALIZE_LIST_HEAD_VARIABLE (mPagePool)
BOOLEAN | m1GPageTableSupport = FALSE
BOOLEAN | mCpuSmmStaticPageTable

Detailed Description

Page Fault (#PF) handler for X64 processors

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT64 AllocPage ( VOID )

Allocate free Page for PageFault handler use.

Returns
Page address.
UINT8 CalculateMaximumSupportAddress ( VOID )

Calculate the maximum support address.

Returns
the maximum support address.
UINT64 GetAccNum ( IN UINT64 * Entry )

Return access record in entry.

Parameters
[in] Entry Pointer to entry
Returns
Access record value.
UINT64 GetAndUpdateAccNum ( IN OUT UINT64 * Entry )

Return and update the access record in entry.

Parameters
[in,out] Entry Pointer to entry
Returns
Access record value.
UINT64 GetSubEntriesNum ( IN UINT64 * Entry )

Return sub-entries number in entry.

Parameters
[in] Entry Pointer to entry
Returns
Sub-entries number based on 0: 0 means there is 1 sub-entry under this entry 0x1ff means there is 512 sub-entries under this entry
BOOLEAN Is1GPageSupport ( VOID )

Check if 1-GByte pages is supported by processor or not.

Return values
TRUE | 1-GByte pages is supported.
FALSE | 1-GByte pages is not supported.
VOID ReclaimPages ( VOID )

Reclaim free pages for PageFault handler.

Search the whole entries tree to find the leaf entry that has the smallest access record value. Insert the page pointed by this leaf entry into the page pool. And check its upper entries if need to be inserted into the page pool or not.

VOID SetAccNum | ( | IN OUT UINT64 * | Entry,
 |  | IN UINT64 | Acc
 | ) |  |

Set access record in entry.

Parameters
[in,out] | Entry | Pointer to entry
[in] | Acc | Access record value
VOID SetPageTableAttributes ( VOID )

This function sets memory attribute for page table.

VOID SetStaticPageTable ( IN UINTN PageTable )

Set static page table.

Parameters
[in] PageTable Address of page table.
VOID SetSubEntriesNum | ( | IN OUT UINT64 * | Entry,
 |  | IN UINT64 | SubEntryNum
 | ) |  |

Set sub-entries number in entry.

Parameters
[in,out] | Entry | Pointer to entry
[in] | SubEntryNum | Sub-entries number based on 0: 0 means there is 1 sub-entry under this entry 0x1ff means there is 512 sub-entries under this entry
VOID SmiDefaultPFHandler ( VOID )

Page Fault handler for SMM use.

VOID EFIAPI SmiPFHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

ThePage Fault handler wrapper for SMM use.

Parameters
InterruptType | Defines the type of interrupt or exception that occurred on the processor.This parameter is processor architecture specific.
SystemContext | A pointer to the processor context when the interrupt occurred on the processor.
UINT32 SmmInitPageTable ( VOID )

Create PageTable for SMM use.

Returns
The address of PML4 (to set CR3).
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/X64/Semaphore.c File Reference

  • File List
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  • PiSmmCpuDxeSmm
  • X64
Functions | Variables
Semaphore.c File Reference

Functions

VOID SmmRelocationSemaphoreComplete32 (VOID)
VOID SemaphoreHook (IN UINTN CpuIndex, IN volatile BOOLEAN *RebasedFlag)

Variables

X86_ASSEMBLY_PATCH_LABEL | gPatchSmmRelocationOriginalAddressPtr32
X86_ASSEMBLY_PATCH_LABEL | gPatchRebasedFlagAddr32
UINTN | mSmmRelocationOriginalAddress
volatile BOOLEAN * | mRebasedFlag

Detailed Description

Semaphore mechanism to indicate to the BSP that an AP has exited SMM after SMBASE relocation.

Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID SemaphoreHook | ( | IN UINTN | CpuIndex,
 |  | IN volatile BOOLEAN * | RebasedFlag
 | ) |  |

Hook return address of SMM Save State so that semaphore code can be executed immediately after AP exits SMM to indicate to the BSP that an AP has exited SMM after SMBASE relocation.

Parameters
[in] | CpuIndex | The processor index.
[in] | RebasedFlag | A pointer to a flag that is set to TRUE immediately after AP exits SMM.
VOID SmmRelocationSemaphoreComplete32 ( VOID )

AP Semaphore operation in 32-bit mode while BSP runs in 64-bit mode.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • X64
Functions | Variables
SmmFuncsArch.c File Reference

Functions

VOID EFIAPI | InitializeIDTSmmStackGuard (VOID)
VOID * | InitGdt (IN UINTN Cr3, OUT UINTN *GdtStepSize)
UINT16 | GetProtectedModeCS (VOID)
VOID | TransferApToSafeState (IN UINTN ApHltLoopCode, IN UINTN TopOfStack, IN UINTN NumberToFinishAddress)

Variables

EFI_PHYSICAL_ADDRESS | mGdtBuffer
UINTN | mGdtBufferSize

Detailed Description

SMM CPU misc functions for x64 arch specific.

Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINT16 GetProtectedModeCS ( VOID )

Get Protected mode code segment from current GDT table.

Returns
Protected mode code segment value.
VOID* InitGdt | ( | IN UINTN | Cr3,
 |  | OUT UINTN * | GdtStepSize
 | ) |  |

Initialize Gdt for all processors.

Parameters
[in] | Cr3 | CR3 value.
[out] | GdtStepSize | The step size for GDT table.
Returns
GdtBase for processor 0. GdtBase for processor X is: GdtBase + (GdtStepSize * X)
VOID EFIAPI InitializeIDTSmmStackGuard ( VOID )

Initialize IDT for SMM Stack Guard.

VOID TransferApToSafeState | ( | IN UINTN | ApHltLoopCode,
 |  | IN UINTN | TopOfStack,
 |  | IN UINTN | NumberToFinishAddress
 | ) |  |

Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.

Parameters
[in] | ApHltLoopCode | The address of the safe hlt-loop function.
[in] | TopOfStack | A pointer to the new stack to use for the ApHltLoopCode.
[in] | NumberToFinishAddress | Address of Semaphore of APs finish count.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • X64
Functions | Variables
SmmProfileArch.c File Reference

Functions

VOID InitSmmS3Cr3 (VOID)
VOID InitPagesForPFHandler (VOID)
VOID | AcquirePage (UINT64 *Uplink)
VOID | RestorePageTableAbove4G (UINT64 *PageTable, UINT64 PFAddress, UINTN CpuIndex, UINTN ErrorCode, BOOLEAN *IsValidPFAddress)
VOID | ClearTrapFlag (IN OUT EFI_SYSTEM_CONTEXT SystemContext)

Variables

UINTN | mPFPageIndex
UINT64 | mPFPageBuffer
UINT64 * | mPFPageUplink [MAX_PF_PAGE_COUNT]

Detailed Description

X64 processor specific functions to enable SMM profile.

Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID AcquirePage ( UINT64 * Uplink )

Allocate one page for creating 4KB-page based on 2MB-page.

Parameters
Uplink The address of Page-Directory entry.
VOID ClearTrapFlag ( IN OUT EFI_SYSTEM_CONTEXT SystemContext )

Clear TF in FLAGS.

Parameters
SystemContext A pointer to the processor context when the interrupt occurred on the processor.
VOID InitPagesForPFHandler ( VOID )

Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.

VOID InitSmmS3Cr3 ( VOID )

Create SMM page table for S3 path.

VOID RestorePageTableAbove4G | ( | UINT64 * | PageTable,
 |  | UINT64 | PFAddress,
 |  | UINTN | CpuIndex,
 |  | UINTN | ErrorCode,
 |  | BOOLEAN * | IsValidPFAddress
 | ) |  |

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
IsValidPFAddress | The flag indicates if SMM profile data need be added.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmProfileArch.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
  • X64
Data Structures | Typedefs | Functions
SmmProfileArch.h File Reference

Data Structures

struct | _MSR_DS_AREA_STRUCT
struct | _BRANCH_TRACE_RECORD
struct | _PEBS_RECORD

Typedefs

typedef struct _MSR_DS_AREA_STRUCT | MSR_DS_AREA_STRUCT
typedef struct _BRANCH_TRACE_RECORD | BRANCH_TRACE_RECORD
typedef struct _PEBS_RECORD | PEBS_RECORD

Functions

VOID RestorePageTableAbove4G (UINT64 *PageTable, UINT64 PFAddress, UINTN CpuIndex, UINTN ErrorCode, BOOLEAN *IsValidPFAddress)
VOID InitSmmS3Cr3 (VOID)
VOID InitPagesForPFHandler (VOID)

Detailed Description

X64 processor specific header file to enable SMM profile.

Copyright (c) 2012 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID InitPagesForPFHandler ( VOID )

Allocate pages for creating 4KB-page based on 2MB-page when page fault happens.

Allocate pages for creating 4KB-page based on 2MB-page when page fault happens. 32-bit firmware does not need it.

VOID InitSmmS3Cr3 ( VOID )

Create SMM page table for S3 path.

VOID RestorePageTableAbove4G | ( | UINT64 * | PageTable,
 |  | UINT64 | PFAddress,
 |  | UINTN | CpuIndex,
 |  | UINTN | ErrorCode,
 |  | BOOLEAN * | IsValidPFAddress
 | ) |  |

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
IsValidPFAddress | The flag indicates if SMM profile data need be added.

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception. 32-bit firmware does not need it.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
IsValidPFAddress | The flag indicates if SMM profile data need be added.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Data Structures | Functions | Variables
CpuS3.c File Reference

Data Structures

struct | MP_CPU_EXCHANGE_INFO
struct | MP_ASSEMBLY_ADDRESS_MAP
struct | PROGRAM_CPU_REGISTER_FLAGS

Functions

VOID *EFIAPI | AsmGetAddressMap (MP_ASSEMBLY_ADDRESS_MAP *AddressMap)
VOID EFIAPI | LoadMtrrData (EFI_PHYSICAL_ADDRESS MtrrTable)
VOID | S3ReleaseSemaphore (IN OUT volatile UINT32 *Sem)
VOID | S3WaitForSemaphore (IN OUT volatile UINT32 *Sem)
VOID | ProgramProcessorRegister (IN CPU_REGISTER_TABLE *RegisterTable, IN EFI_CPU_PHYSICAL_LOCATION *ApLocation, IN CPU_STATUS_INFORMATION *CpuStatus, IN PROGRAM_CPU_REGISTER_FLAGS *CpuFlags)
VOID | SetRegister (IN BOOLEAN PreSmmRegisterTable)
VOID InitializeAp (VOID)
VOID | PrepareApStartupVector (EFI_PHYSICAL_ADDRESS WorkingBuffer)
VOID InitializeCpuBeforeRebase (VOID)
VOID InitializeCpuAfterRebase (VOID)
VOID RestoreSmmConfigurationInS3 (VOID)
VOID EFIAPI | SmmRestoreCpu (VOID)
VOID | InitSmmS3ResumeState (IN UINT32 Cr3)
VOID | CopyRegisterTable (IN CPU_REGISTER_TABLE *DestinationRegisterTableList, IN CPU_REGISTER_TABLE *SourceRegisterTableList, IN UINT32 NumberOfCpus)
VOID GetAcpiCpuData (VOID)
VOID GetAcpiS3EnableFlag (VOID)

Variables

volatile BOOLEAN | mInitApsAfterSmmBaseReloc
PROGRAM_CPU_REGISTER_FLAGS | mCpuFlags
ACPI_CPU_DATA | mAcpiCpuData
volatile UINT32 | mNumberToFinish
MP_CPU_EXCHANGE_INFO * | mExchangeInfo
BOOLEAN | mRestoreSmmConfigurationInS3 = FALSE
BOOLEAN | mSmmS3Flag = FALSE
SMM_S3_RESUME_STATE * | mSmmS3ResumeState = NULL
BOOLEAN | mAcpiS3Enable = TRUE
UINT8 * | mApHltLoopCode = NULL
UINT8 | mApHltLoopCodeTemplate []
CHAR16 * | mRegisterTypeStr [] = {L"MSR", L"CR", L"MMIO", L"CACHE", L"SEMAP", L"INVALID" }

Detailed Description

Code for Processor S3 restoration

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* EFIAPI AsmGetAddressMap ( MP_ASSEMBLY_ADDRESS_MAP * AddressMap )

Get starting address and size of the rendezvous entry for APs. Information for fixing a jump instruction in the code is also returned.

Parameters
AddressMap Output buffer for address map information.
VOID CopyRegisterTable | ( | IN CPU_REGISTER_TABLE * | DestinationRegisterTableList,
 |  | IN CPU_REGISTER_TABLE * | SourceRegisterTableList,
 |  | IN UINT32 | NumberOfCpus
 | ) |  |

Copy register table from ACPI NVS memory into SMRAM.

Parameters
[in] | DestinationRegisterTableList | Points to destination register table.
[in] | SourceRegisterTableList | Points to source register table.
[in] | NumberOfCpus | Number of CPUs.
VOID GetAcpiCpuData ( VOID )

Get ACPI CPU data.

VOID GetAcpiS3EnableFlag ( VOID )

Get ACPI S3 enable flag.

VOID InitializeAp ( VOID )

AP initialization before then after SMBASE relocation in the S3 boot path.

VOID InitializeCpuAfterRebase ( VOID )

The function is invoked after SMBASE relocation in S3 path to restores CPU status.

The function is invoked after SMBASE relocation in S3 path. It restores configuration according to data saved by normal boot path for both BSP and APs.

VOID InitializeCpuBeforeRebase ( VOID )

The function is invoked before SMBASE relocation in S3 path to restores CPU status.

The function is invoked before SMBASE relocation in S3 path. It does first time microcode load and restores MTRRs for both BSP and APs.

VOID InitSmmS3ResumeState ( IN UINT32 Cr3 )

Initialize SMM S3 resume state structure used during S3 Resume.

Parameters
[in] Cr3 The base address of the page tables to use in SMM.
VOID EFIAPI LoadMtrrData ( EFI_PHYSICAL_ADDRESS MtrrTable )

Sync up the MTRR values for all processors.

Parameters
MtrrTable Table holding fixed/variable MTRR values to be loaded.
VOID PrepareApStartupVector ( EFI_PHYSICAL_ADDRESS WorkingBuffer )

Prepares startup vector for APs.

This function prepares startup vector for APs.

Parameters
WorkingBuffer The address of the work buffer.
VOID ProgramProcessorRegister | ( | IN CPU_REGISTER_TABLE * | RegisterTable,
 |  | IN EFI_CPU_PHYSICAL_LOCATION * | ApLocation,
 |  | IN CPU_STATUS_INFORMATION * | CpuStatus,
 |  | IN PROGRAM_CPU_REGISTER_FLAGS * | CpuFlags
 | ) |  |

Initialize the CPU registers from a register table.

Parameters
[in] | RegisterTable | The register table for this AP.
[in] | ApLocation | AP location info for this ap.
[in] | CpuStatus | CPU status info for this CPU.
[in] | CpuFlags | Flags data structure used when program the register.
Note
This service could be called by BSP/APs.
VOID RestoreSmmConfigurationInS3 ( VOID )

Restore SMM Configuration in S3 boot path.

VOID S3ReleaseSemaphore ( IN OUT volatile UINT32 * Sem )

Increment semaphore by 1.

Parameters
Sem IN: 32-bit unsigned integer
VOID S3WaitForSemaphore ( IN OUT volatile UINT32 * Sem )

Decrement the semaphore by 1 if it is not zero.

Performs an atomic decrement operation for semaphore. The compare exchange operation must be performed using MP safe mechanisms.

Parameters
Sem IN: 32-bit unsigned integer
VOID SetRegister ( IN BOOLEAN PreSmmRegisterTable )

Set Processor register for one AP.

Parameters
PreSmmRegisterTable Use pre Smm register table or register table.
VOID EFIAPI SmmRestoreCpu ( VOID )

Perform SMM initialization for all processors in the S3 boot path.

For a native platform, MP initialization in the S3 boot path is also performed in this function.

Variable Documentation

UINT8 mApHltLoopCodeTemplate[]
Initial value:
= {
0x8B, 0x44, 0x24, 0x04,
0xF0, 0xFF, 0x08,
0xFA,
0xF4,
0xEB, 0xFC
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.c File Reference

  • File List
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  • UefiCpuPkg
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Functions | Variables
CpuService.c File Reference

Functions

EFI_STATUS EFIAPI | SmmGetProcessorInfo (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
EFI_STATUS EFIAPI | SmmSwitchBsp (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber)
EFI_STATUS EFIAPI | SmmAddProcessor (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINT64 ProcessorId, OUT UINTN *ProcessorNumber)
EFI_STATUS EFIAPI | SmmRemoveProcessor (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber)
EFI_STATUS EFIAPI | SmmWhoAmI (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, OUT UINTN *ProcessorNumber)
VOID SmmCpuUpdate (VOID)
EFI_STATUS EFIAPI | SmmRegisterExceptionHandler (IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
EFI_STATUS | InitializeSmmCpuServices (IN EFI_HANDLE Handle)

Variables

EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService

Detailed Description

Implementation of SMM CPU Services Protocol.

Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS InitializeSmmCpuServices ( IN EFI_HANDLE Handle )

Initialize SMM CPU Services.

It installs EFI SMM CPU Services Protocol.

Parameters
ImageHandle The firmware allocated handle for the EFI image.
Return values
EFI_SUCCESS EFI SMM CPU Services Protocol was installed successfully.
EFI_STATUS EFIAPI SmmAddProcessor | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINT64 | ProcessorId,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

Notify that a processor was hot-added.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorId | Local APIC ID of the hot-added processor.
[out] | ProcessorNumber | The handle number of the hot-added processor.
Return values
EFI_SUCCESS | The hot-addition of the specified processors was successfully notified.
EFI_UNSUPPORTED | Hot addition of processor is not supported.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_ALREADY_STARTED | The processor is already online in the system.
VOID SmmCpuUpdate ( VOID )

Update the SMM CPU list per the pending operation.

This function is called after return from SMI handlers.

EFI_STATUS EFIAPI SmmGetProcessorInfo | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets processor information on the requested processor at the instant this call is made.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
EFI_STATUS EFIAPI SmmRegisterExceptionHandler | ( | IN EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Register exception handler.

Parameters
This | A pointer to the SMM_CPU_SERVICE_PROTOCOL instance.
ExceptionType | Defines which interrupt or exception to hook. Type EFI_EXCEPTION_TYPE and the valid values for this parameter are defined in EFI_DEBUG_SUPPORT_PROTOCOL of the UEFI 2.0 specification.
InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported.
EFI_STATUS EFIAPI SmmRemoveProcessor | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber
 | ) |  |

Notify that a processor was hot-removed.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of the hot-added processor.
Return values
EFI_SUCCESS | The hot-removal of the specified processors was successfully notified.
EFI_UNSUPPORTED | Hot removal of processor is not supported.
EFI_UNSUPPORTED | Hot removal of BSP is not supported.
EFI_UNSUPPORTED | Hot removal of a processor with pending hot-plug operation is not supported.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_STATUS EFIAPI SmmSwitchBsp | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber
 | ) |  |

This service switches the requested AP to be the BSP since the next SMI.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP.
Return values
EFI_SUCCESS | BSP will be switched in next SMI.
EFI_UNSUPPORTED | Switching the BSP or a processor to be hot-removed is not supported.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_STATUS EFIAPI SmmWhoAmI | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

This return the handle number for the calling processor.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[out] | ProcessorNumber | The handle number of currently executing processor.
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.

Variable Documentation

EFI_SMM_CPU_SERVICE_PROTOCOL mSmmCpuService
Initial value:
= {
SmmGetProcessorInfo,
SmmSwitchBsp,
SmmAddProcessor,
SmmRemoveProcessor,
SmmWhoAmI,
SmmRegisterExceptionHandler
}
SmmRemoveProcessor
EFI_STATUS EFIAPI SmmRemoveProcessor(IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber)
Definition: CpuService.c:194
SmmWhoAmI
EFI_STATUS EFIAPI SmmWhoAmI(IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, OUT UINTN *ProcessorNumber)
Definition: CpuService.c:245
SmmRegisterExceptionHandler
EFI_STATUS EFIAPI SmmRegisterExceptionHandler(IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
Definition: CpuService.c:338
SmmAddProcessor
EFI_STATUS EFIAPI SmmAddProcessor(IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINT64 ProcessorId, OUT UINTN *ProcessorNumber)
Definition: CpuService.c:126
SmmGetProcessorInfo
EFI_STATUS EFIAPI SmmGetProcessorInfo(IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
Definition: CpuService.c:46
SmmSwitchBsp
EFI_STATUS EFIAPI SmmSwitchBsp(IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber)
Definition: CpuService.c:83
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/CpuService.h File Reference

  • File List
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  • PiSmmCpuDxeSmm
Enumerations | Functions
CpuService.h File Reference

Enumerations

enum SMM_CPU_OPERATION { SmmCpuNone, SmmCpuAdd, SmmCpuRemove, SmmCpuSwitchBsp }

Functions

EFI_STATUS EFIAPI | SmmGetProcessorInfo (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber, OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer)
EFI_STATUS EFIAPI | SmmSwitchBsp (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber)
EFI_STATUS EFIAPI | SmmAddProcessor (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINT64 ProcessorId, OUT UINTN *ProcessorNumber)
EFI_STATUS EFIAPI | SmmRemoveProcessor (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN UINTN ProcessorNumber)
EFI_STATUS EFIAPI | SmmWhoAmI (IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL *This, OUT UINTN *ProcessorNumber)
EFI_STATUS EFIAPI | SmmRegisterExceptionHandler (IN EFI_SMM_CPU_SERVICE_PROTOCOL *This, IN EFI_EXCEPTION_TYPE ExceptionType, IN EFI_CPU_INTERRUPT_HANDLER InterruptHandler)
VOID SmmCpuUpdate (VOID)
EFI_STATUS | InitializeSmmCpuServices (IN EFI_HANDLE Handle)

Detailed Description

Include file for SMM CPU Services protocol implementation.

Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS InitializeSmmCpuServices ( IN EFI_HANDLE Handle )

Initialize SMM CPU Services.

It installs EFI SMM CPU Services Protocol.

Parameters
ImageHandle The firmware allocated handle for the EFI image.
Return values
EFI_SUCCESS EFI SMM CPU Services Protocol was installed successfully.
EFI_STATUS EFIAPI SmmAddProcessor | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINT64 | ProcessorId,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

Notify that a processor was hot-added.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorId | Local APIC ID of the hot-added processor.
[out] | ProcessorNumber | The handle number of the hot-added processor.
Return values
EFI_SUCCESS | The hot-addition of the specified processors was successfully notified.
EFI_UNSUPPORTED | Hot addition of processor is not supported.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_ALREADY_STARTED | The processor is already online in the system.
VOID SmmCpuUpdate ( VOID )

Update the SMM CPU list per the pending operation.

This function is called after return from SMI handlers.

EFI_STATUS EFIAPI SmmGetProcessorInfo | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber,
 |  | OUT EFI_PROCESSOR_INFORMATION * | ProcessorInfoBuffer
 | ) |  |

Gets processor information on the requested processor at the instant this call is made.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of processor.
[out] | ProcessorInfoBuffer | A pointer to the buffer where information for the requested processor is deposited.
Return values
EFI_SUCCESS | Processor information was returned.
EFI_INVALID_PARAMETER | ProcessorInfoBuffer is NULL.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist in the platform.
EFI_STATUS EFIAPI SmmRegisterExceptionHandler | ( | IN EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN EFI_EXCEPTION_TYPE | ExceptionType,
 |  | IN EFI_CPU_INTERRUPT_HANDLER | InterruptHandler
 | ) |  |

Register exception handler.

Parameters
This | A pointer to the SMM_CPU_SERVICE_PROTOCOL instance.
ExceptionType | Defines which interrupt or exception to hook. Type EFI_EXCEPTION_TYPE and the valid values for this parameter are defined in EFI_DEBUG_SUPPORT_PROTOCOL of the UEFI 2.0 specification.
InterruptHandler | A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called when a processor interrupt occurs. If this parameter is NULL, then the handler will be uninstalled.
Return values
EFI_SUCCESS | The handler for the processor interrupt was successfully installed or uninstalled.
EFI_ALREADY_STARTED | InterruptHandler is not NULL, and a handler for InterruptType was previously installed.
EFI_INVALID_PARAMETER | InterruptHandler is NULL, and a handler for InterruptType was not previously installed.
EFI_UNSUPPORTED | The interrupt specified by InterruptType is not supported.
EFI_STATUS EFIAPI SmmRemoveProcessor | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber
 | ) |  |

Notify that a processor was hot-removed.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of the hot-added processor.
Return values
EFI_SUCCESS | The hot-removal of the specified processors was successfully notified.
EFI_UNSUPPORTED | Hot removal of processor is not supported.
EFI_UNSUPPORTED | Hot removal of BSP is not supported.
EFI_UNSUPPORTED | Hot removal of a processor with pending hot-plug operation is not supported.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_STATUS EFIAPI SmmSwitchBsp | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | IN UINTN | ProcessorNumber
 | ) |  |

This service switches the requested AP to be the BSP since the next SMI.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[in] | ProcessorNumber | The handle number of AP that is to become the new BSP.
Return values
EFI_SUCCESS | BSP will be switched in next SMI.
EFI_UNSUPPORTED | Switching the BSP or a processor to be hot-removed is not supported.
EFI_NOT_FOUND | The processor with the handle specified by ProcessorNumber does not exist.
EFI_INVALID_PARAMETER | ProcessorNumber is invalid.
EFI_STATUS EFIAPI SmmWhoAmI | ( | IN CONST EFI_SMM_CPU_SERVICE_PROTOCOL * | This,
 |  | OUT UINTN * | ProcessorNumber
 | ) |  |

This return the handle number for the calling processor.

Parameters
[in] | This | A pointer to the EFI_SMM_CPU_SERVICE_PROTOCOL instance.
[out] | ProcessorNumber | The handle number of currently executing processor.
Return values
EFI_SUCCESS | The current processor handle number was returned in ProcessorNumber.
EFI_INVALID_PARAMETER | ProcessorNumber is NULL.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Functions | Variables
MpService.c File Reference

Functions

UINT32 | WaitForSemaphore (IN OUT volatile UINT32 *Sem)
UINT32 | ReleaseSemaphore (IN OUT volatile UINT32 *Sem)
UINT32 | LockdownSemaphore (IN OUT volatile UINT32 *Sem)
VOID | WaitForAllAPs (IN UINTN NumberOfAPs)
VOID ReleaseAllAPs (VOID)
BOOLEAN | AllCpusInSmmWithExceptions (SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions)
BOOLEAN | IsLmceOsEnabled (VOID)
BOOLEAN | IsLmceSignaled (VOID)
VOID SmmWaitForApArrival (VOID)
VOID | ReplaceOSMtrrs (IN UINTN CpuIndex)
VOID | BSPHandler (IN UINTN CpuIndex, IN SMM_CPU_SYNC_MODE SyncMode)
VOID | APHandler (IN UINTN CpuIndex, IN BOOLEAN ValidSmi, IN SMM_CPU_SYNC_MODE SyncMode)
UINT32 | Gen4GPageTable (IN BOOLEAN Is32BitPageTable)
EFI_STATUS | InternalSmmStartupThisAp (IN EFI_AP_PROCEDURE Procedure, IN UINTN CpuIndex, IN OUT VOID *ProcArguments OPTIONAL, IN BOOLEAN BlockingMode)
EFI_STATUS EFIAPI | SmmBlockingStartupThisAp (IN EFI_AP_PROCEDURE Procedure, IN UINTN CpuIndex, IN OUT VOID *ProcArguments OPTIONAL)
EFI_STATUS EFIAPI | SmmStartupThisAp (IN EFI_AP_PROCEDURE Procedure, IN UINTN CpuIndex, IN OUT VOID *ProcArguments OPTIONAL)
VOID EFIAPI | CpuSmmDebugEntry (IN UINTN CpuIndex)
VOID EFIAPI | CpuSmmDebugExit (IN UINTN CpuIndex)
VOID EFIAPI | SmiRendezvous (IN UINTN CpuIndex)
VOID InitializeSmmCpuSemaphores (VOID)
VOID EFIAPI | InitializeMpSyncData (VOID)
UINT32 | InitializeMpServiceData (IN VOID *Stacks, IN UINTN StackSize)
EFI_STATUS EFIAPI | RegisterSmmEntry (IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This, IN EFI_SMM_ENTRY_POINT SmmEntryPoint)

Variables

MTRR_SETTINGS | gSmiMtrrs
UINT64 | gPhyMask
SMM_DISPATCHER_MP_SYNC_DATA * | mSmmMpSyncData = NULL
UINTN | mSmmMpSyncDataSize
SMM_CPU_SEMAPHORES | mSmmCpuSemaphores
UINTN | mSemaphoreSize
SPIN_LOCK * | mPFLock = NULL
SMM_CPU_SYNC_MODE | mCpuSmmSyncMode
BOOLEAN | mMachineCheckSupported = FALSE
EFI_GUID | gAmiMpSyncDataProtocolGuid
BOOLEAN | mPcdSmmIsolationSupport

Detailed Description

SMM MP service implementation

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

BOOLEAN AllCpusInSmmWithExceptions ( SMM_CPU_ARRIVAL_EXCEPTIONS Exceptions )

Checks if all CPUs (with certain exceptions) have checked in for this SMI run

Parameters
Exceptions CPU Arrival exception flags.
Return values
TRUE | if all CPUs the have checked in.
FALSE | if at least one Normal AP hasn't checked in.
VOID APHandler | ( | IN UINTN | CpuIndex,
 |  | IN BOOLEAN | ValidSmi,
 |  | IN SMM_CPU_SYNC_MODE | SyncMode
 | ) |  |

SMI handler for AP.

Parameters
CpuIndex | AP processor Index.
ValidSmi | Indicates that current SMI is a valid SMI or not.
SyncMode | SMM MP sync mode.
VOID BSPHandler | ( | IN UINTN | CpuIndex,
 |  | IN SMM_CPU_SYNC_MODE | SyncMode
 | ) |  |

SMI handler for BSP.

Parameters
CpuIndex | BSP processor Index
SyncMode | SMM MP sync mode
VOID EFIAPI CpuSmmDebugEntry ( IN UINTN CpuIndex )

This function sets DR6 & DR7 according to SMM save state, before running SMM C code. They are useful when you want to enable hardware breakpoints in SMM without entry SMM mode.

NOTE: It might not be appreciated in runtime since it might conflict with OS debugging facilities. Turn them off in RELEASE.

Parameters
CpuIndex CPU Index
VOID EFIAPI CpuSmmDebugExit ( IN UINTN CpuIndex )

This function restores DR6 & DR7 to SMM save state.

NOTE: It might not be appreciated in runtime since it might conflict with OS debugging facilities. Turn them off in RELEASE.

Parameters
CpuIndex CPU Index
UINT32 Gen4GPageTable ( IN BOOLEAN Is32BitPageTable )

Create 4G PageTable in SMRAM.

Parameters
[in] Is32BitPageTable Whether the page table is 32-bit PAE
Returns
PageTable Address
UINT32 InitializeMpServiceData | ( | IN VOID * | Stacks,
 |  | IN UINTN | StackSize
 | ) |  |

Initialize global data for MP synchronization.

Parameters
Stacks | Base address of SMI stack buffer for all processors.
StackSize | Stack size for each processor in SMM.
VOID EFIAPI InitializeMpSyncData ( VOID )

Initialize un-cacheable data.

VOID InitializeSmmCpuSemaphores ( VOID )

Allocate buffer for all semaphores and spin locks.

EFI_STATUS InternalSmmStartupThisAp | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | CpuIndex,
 |  | IN OUT VOID *ProcArguments | OPTIONAL,
 |  | IN BOOLEAN | BlockingMode
 | ) |  |

Schedule a procedure to run on the specified CPU.

Parameters
[in] | Procedure | The address of the procedure to run
[in] | CpuIndex | Target CPU Index
[in,out] | ProcArguments | The parameter to pass to the procedure
[in] | BlockingMode | Startup AP in blocking mode or not
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | The procedure has been successfully scheduled
BOOLEAN IsLmceOsEnabled ( VOID )

Has OS enabled Lmce in the MSR_IA32_MCG_EXT_CTL

Return values
TRUE | Os enable lmce.
FALSE | Os not enable lmce.
BOOLEAN IsLmceSignaled ( VOID )

Return if Local machine check exception signaled.

Indicates (when set) that a local machine check exception was generated. This indicates that the current machine-check event was delivered to only the logical processor.

Return values
TRUE | LMCE was signaled.
FALSE | LMCE was not signaled.
UINT32 LockdownSemaphore ( IN OUT volatile UINT32 * Sem )

Performs an atomic compare exchange operation to lock semaphore. The compare exchange operation must be performed using MP safe mechanisms.

Parameters
Sem IN: 32-bit unsigned integer OUT: -1
Returns
Original integer
EFI_STATUS EFIAPI RegisterSmmEntry | ( | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL * | This,
 |  | IN EFI_SMM_ENTRY_POINT | SmmEntryPoint
 | ) |  |

Register the SMM Foundation entry point.

Parameters
This | Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
SmmEntryPoint | SMM Foundation EntryPoint
Return values
EFI_SUCCESS Successfully to register SMM foundation entry point
VOID ReleaseAllAPs ( VOID )

Performs an atomic compare exchange operation to release semaphore for each AP.

UINT32 ReleaseSemaphore ( IN OUT volatile UINT32 * Sem )

Performs an atomic compare exchange operation to release semaphore. The compare exchange operation must be performed using MP safe mechanisms.

Parameters
Sem IN: 32-bit unsigned integer OUT: original integer + 1
Returns
Original integer + 1
VOID ReplaceOSMtrrs ( IN UINTN CpuIndex )

Replace OS MTRR's with SMI MTRR's.

Parameters
CpuIndex Processor Index
VOID EFIAPI SmiRendezvous ( IN UINTN CpuIndex )

C function for SMI entry, each processor comes here upon SMI trigger.

Parameters
CpuIndex CPU Index
EFI_STATUS EFIAPI SmmBlockingStartupThisAp | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | CpuIndex,
 |  | IN OUT VOID *ProcArguments | OPTIONAL
 | ) |  |

Schedule a procedure to run on the specified CPU in blocking mode.

Parameters
[in] | Procedure | The address of the procedure to run
[in] | CpuIndex | Target CPU Index
[in,out] | ProcArguments | The parameter to pass to the procedure
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | The procedure has been successfully scheduled
EFI_STATUS EFIAPI SmmStartupThisAp | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | CpuIndex,
 |  | IN OUT VOID *ProcArguments | OPTIONAL
 | ) |  |

Schedule a procedure to run on the specified CPU.

Parameters
Procedure | The address of the procedure to run
CpuIndex | Target CPU Index
ProcArguments | The parameter to pass to the procedure
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | The procedure has been successfully scheduled
VOID SmmWaitForApArrival ( VOID )

Given timeout constraint, wait for all APs to arrive, and insure when this function returns, no AP will execute normal mode code before entering SMM, except SMI disabled APs.

VOID WaitForAllAPs ( IN UINTN NumberOfAPs )

Wait all APs to performs an atomic compare exchange operation to release semaphore.

Parameters
NumberOfAPs AP number
UINT32 WaitForSemaphore ( IN OUT volatile UINT32 * Sem )

Performs an atomic compare exchange operation to get semaphore. The compare exchange operation must be performed using MP safe mechanisms.

Parameters
Sem IN: 32-bit unsigned integer OUT: original integer - 1
Returns
Original integer - 1
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Functions | Variables
PiSmmCpuDxeSmm.c File Reference

Functions

VOID InitializeSmmIdt (VOID)
VOID | DumpModuleInfoByIp (IN UINTN CallerIpAddress)
EFI_STATUS EFIAPI | SmmReadSaveState (IN CONST EFI_SMM_CPU_PROTOCOL *This, IN UINTN Width, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, OUT VOID *Buffer)
EFI_STATUS EFIAPI | SmmWriteSaveState (IN CONST EFI_SMM_CPU_PROTOCOL *This, IN UINTN Width, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer)
VOID EFIAPI | SmmInitHandler (VOID)
VOID EFIAPI | SmmRelocateBases (VOID)
EFI_STATUS EFIAPI | SmmReadyToLockEventNotify (IN CONST EFI_GUID *Protocol, IN VOID *Interface, IN EFI_HANDLE Handle)
EFI_STATUS EFIAPI | PiCpuSmmEntry (IN EFI_HANDLE ImageHandle, IN EFI_SYSTEM_TABLE *SystemTable)
VOID | FindSmramInfo (OUT UINT32 *SmrrBase, OUT UINT32 *SmrrSize)
VOID EFIAPI | ConfigSmmCodeAccessCheckOnCurrentProcessor (IN OUT VOID *Buffer)
VOID ConfigSmmCodeAccessCheck (VOID)
VOID * | AllocatePageTableMemory (IN UINTN Pages)
VOID * | AllocateCodePages (IN UINTN Pages)
VOID * | AllocateAlignedCodePages (IN UINTN Pages, IN UINTN Alignment)
VOID PerformRemainingTasks (VOID)
VOID PerformPreTasks (VOID)

Variables

SMM_CPU_PRIVATE_DATA | mSmmCpuPrivateData
CPU_HOT_PLUG_DATA | mCpuHotPlugData
SMM_CPU_PRIVATE_DATA * | gSmmCpuPrivate = &mSmmCpuPrivateData
SMM_SUPERVISOR_PROTOCOL * | SmmSupervisor = NULL
volatile BOOLEAN * | mRebased
volatile BOOLEAN | mIsBsp
EFI_HANDLE | mSmmCpuHandle = NULL
EFI_SMM_CPU_PROTOCOL | mSmmCpu
EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL | mSmmMemoryAttribute
EFI_CPU_INTERRUPT_HANDLER | mExternalVectorTable [EXCEPTION_VECTOR_NUMBER]
UINTN | mSmmStackArrayBase
UINTN | mSmmStackArrayEnd
UINTN | mSmmStackSize
UINTN | mMaxNumberOfCpus = 1
UINTN | mNumberOfCpus = 1
BOOLEAN | mSmmReadyToLock = FALSE
BOOLEAN | mSmmCodeAccessCheckEnable = FALSE
UINT64 | mAddressEncMask = 0
SPIN_LOCK * | mConfigSmmCodeAccessCheckLock = NULL
EFI_SMRAM_DESCRIPTOR * | mSmmCpuSmramRanges
UINTN | mSmmCpuSmramRangeCount
UINT8 | mPhysicalAddressBits
UINT32 | mSmmCr0
UINT32 | mSmmCr4
BOOLEAN | SmmAmiBufferValidationLibCsmEnabled = FALSE
BOOLEAN | mPcdSmmIsolationSupport = FALSE

Detailed Description

Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* AllocateAlignedCodePages | ( | IN UINTN | Pages,
 |  | IN UINTN | Alignment
 | ) |  |

Allocate aligned pages for code.

Parameters
[in] | Pages | Number of pages to be allocated.
[in] | Alignment | The requested alignment of the allocation. Must be a power of two. If Alignment is zero, then byte alignment is used.
Returns
Allocated memory.
VOID* AllocateCodePages ( IN UINTN Pages )

Allocate pages for code.

Parameters
[in] Pages Number of pages to be allocated.
Returns
Allocated memory.
VOID* AllocatePageTableMemory ( IN UINTN Pages )

This API provides a way to allocate memory for page table.

This API can be called more once to allocate memory for page tables.

Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.
VOID ConfigSmmCodeAccessCheck ( VOID )

Configure SMM Code Access Check feature for all processors. SMM Feature Control MSR will be locked after configuration.

VOID EFIAPI ConfigSmmCodeAccessCheckOnCurrentProcessor ( IN OUT VOID * Buffer )

Configure SMM Code Access Check feature on an AP. SMM Feature Control MSR will be locked after configuration.

Parameters
[in,out] Buffer Pointer to private data buffer.
VOID DumpModuleInfoByIp ( IN UINTN CallerIpAddress )

Search module name by input IP address and output it.

Parameters
CallerIpAddress Caller instruction pointer.
VOID FindSmramInfo | ( | OUT UINT32 * | SmrrBase,
 |  | OUT UINT32 * | SmrrSize
 | ) |  |

Find out SMRAM information including SMRR base and SMRR size.

Parameters
SmrrBase | SMRR base
SmrrSize | SMRR size
VOID InitializeSmmIdt ( VOID )

Initialize IDT to setup exception handlers for SMM.

VOID PerformPreTasks ( VOID )

Perform the pre tasks.

VOID PerformRemainingTasks ( VOID )

Perform the remaining tasks.

EFI_STATUS EFIAPI PiCpuSmmEntry | ( | IN EFI_HANDLE | ImageHandle,
 |  | IN EFI_SYSTEM_TABLE * | SystemTable
 | ) |  |

The module Entry Point of the CPU SMM driver.

Parameters
ImageHandle | The firmware allocated handle for the EFI image.
SystemTable | A pointer to the EFI System Table.
Return values
EFI_SUCCESS | The entry point is executed successfully.
Other | Some error occurs when executing this entry point.
VOID EFIAPI SmmInitHandler ( VOID )

C function for SMI handler. To change all processor's SMMBase Register.

EFI_STATUS EFIAPI SmmReadSaveState | ( | IN CONST EFI_SMM_CPU_PROTOCOL * | This,
 |  | IN UINTN | Width,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | CpuIndex,
 |  | OUT VOID * | Buffer
 | ) |  |

Read information from the CPU save state.

Parameters
This | EFI_SMM_CPU_PROTOCOL instance
Width | The number of bytes to read from the CPU save state.
Register | Specifies the CPU register to read form the save state.
CpuIndex | Specifies the zero-based index of the CPU save state.
Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State
EFI_NOT_FOUND | The register is not defined for the Save State of Processor
EFI_INVALID_PARAMTER | This or Buffer is NULL.
EFI_STATUS EFIAPI SmmReadyToLockEventNotify | ( | IN CONST EFI_GUID * | Protocol,
 |  | IN VOID * | Interface,
 |  | IN EFI_HANDLE | Handle
 | ) |  |

SMM Ready To Lock event notification handler.

The CPU S3 data is copied to SMRAM for security and mSmmReadyToLock is set to perform additional lock actions that must be performed from SMM on the next SMI.

Parameters
[in] | Protocol | Points to the protocol's unique identifier.
[in] | Interface | Points to the interface instance.
[in] | Handle | The handle on which the interface was installed.
Return values
EFI_SUCCESS Notification handler runs successfully.
VOID EFIAPI SmmRelocateBases ( VOID )

Relocate SmmBases for each processor.

Execute on first boot and all S3 resumes

EFI_STATUS EFIAPI SmmWriteSaveState | ( | IN CONST EFI_SMM_CPU_PROTOCOL * | This,
 |  | IN UINTN | Width,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | CpuIndex,
 |  | IN CONST VOID * | Buffer
 | ) |  |

Write data to the CPU save state.

Parameters
This | EFI_SMM_CPU_PROTOCOL instance
Width | The number of bytes to read from the CPU save state.
Register | Specifies the CPU register to write to the save state.
CpuIndex | Specifies the zero-based index of the CPU save state
Buffer | Upon entry, this holds the new CPU register value.
Return values
EFI_SUCCESS | The register was written from Save State
EFI_NOT_FOUND | The register is not defined for the Save State of Processor
EFI_INVALID_PARAMTER | ProcessorIndex or Width is not correct

Variable Documentation

CPU_HOT_PLUG_DATA mCpuHotPlugData
Initial value:
= {
CPU_HOT_PLUG_DATA_REVISION_1,
0,
NULL,
NULL,
0,
0,
0
}
EFI_SMM_CPU_PROTOCOL mSmmCpu
Initial value:
= {
SmmReadSaveState,
SmmWriteSaveState
}
SmmReadSaveState
EFI_STATUS EFIAPI SmmReadSaveState(IN CONST EFI_SMM_CPU_PROTOCOL *This, IN UINTN Width, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, OUT VOID *Buffer)
Definition: PiSmmCpuDxeSmm.c:242
SmmWriteSaveState
EFI_STATUS EFIAPI SmmWriteSaveState(IN CONST EFI_SMM_CPU_PROTOCOL *This, IN UINTN Width, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer)
Definition: PiSmmCpuDxeSmm.c:314

SMM CPU Protocol instance

EFI_HANDLE mSmmCpuHandle = NULL

Handle for the SMM CPU Protocol

SMM_CPU_PRIVATE_DATA mSmmCpuPrivateData
Initial value:
= {
SMM_CPU_PRIVATE_DATA_SIGNATURE,
NULL,
NULL,
NULL,
NULL,
NULL,
{ {0} },
{
SmmStartupThisAp,
0,
0,
NULL,
NULL
},
NULL,
{
mSmmCpuPrivateData.SmmReservedSmramRegion,
RegisterSmmEntry
},
}
SmmStartupThisAp
EFI_STATUS EFIAPI SmmStartupThisAp(IN EFI_AP_PROCEDURE Procedure, IN UINTN CpuIndex, IN OUT VOID *ProcArguments OPTIONAL)
Definition: MpService.c:1033
RegisterSmmEntry
EFI_STATUS EFIAPI RegisterSmmEntry(IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This, IN EFI_SMM_ENTRY_POINT SmmEntryPoint)
Definition: MpService.c:1497
EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute
Initial value:
= {
EdkiiSmmGetMemoryAttributes,
EdkiiSmmSetMemoryAttributes,
EdkiiSmmClearMemoryAttributes
}
EdkiiSmmClearMemoryAttributes
EFI_STATUS EFIAPI EdkiiSmmClearMemoryAttributes(IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
Definition: SmmCpuMemoryManagement.c:1431
EdkiiSmmGetMemoryAttributes
EFI_STATUS EFIAPI EdkiiSmmGetMemoryAttributes(IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 *Attributes)
EdkiiSmmSetMemoryAttributes
EFI_STATUS EFIAPI EdkiiSmmSetMemoryAttributes(IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
Definition: SmmCpuMemoryManagement.c:1396

SMM Memory Attribute Protocol instance

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Data Structures | Typedefs | Enumerations | Functions | Variables
PiSmmCpuDxeSmm.h File Reference

Data Structures

struct | PAGE_ATTRIBUTE_TABLE
struct | SMM_CPU_PRIVATE_DATA
struct | _SMM_SUPERVISOR_PROTOCOL
struct | SMM_CPU_DATA_BLOCK
struct | SMM_DISPATCHER_MP_SYNC_DATA
struct | SMM_CPU_SEMAPHORE_GLOBAL
struct | SMM_CPU_SEMAPHORE_CPU
struct | SMM_CPU_SEMAPHORES

Typedefs

typedef UINT32 | SMM_CPU_ARRIVAL_EXCEPTIONS
typedef struct
_SMM_SUPERVISOR_PROTOCOL 		SMM_SUPERVISOR_PROTOCOL
typedef VOID(EFIAPI * | SMM_SV_INSTALL_SMI_HANDLER )(IN UINTN CpuIndex, IN UINT32 SmBase, IN VOID *SmiStack, IN UINTN StackSize, IN UINT32 Cr3, IN UINT64 SmiHandlerGdtBase, IN UINT64 SmiHandlerGdtSize, IN UINT64 SmiHandlerIdtrPtr, IN UINT64 SmiRendezvousPtr, OUT UINT8 **SmmEntryAddr, OUT UINT32 *SmmEntrySize)

Enumerations

enum PAGE_ATTRIBUTE {
PageNone, Page4K, Page2M, Page1G,
PageNone = 0, PageMin = 1, Page4K = PageMin, Page2M = 2,
Page1G = 3, Page512G = 4, PageMax = Page512G, PageNone,
Page4K, Page2M, Page1G
}
enum SMM_SYS_CALL {
SMM_SC_RDMSR = 0, SMM_SC_WRMSR = 1, SMM_SC_CLI = 2, SMM_SC_IO_READ = 3,
SMM_SC_IO_WRITE = 4, SMM_SC_WBINVD = 5, SMM_SC_HLT = 6, SMM_SC_SVST_READ = 7
}
enum SMM_CPU_SYNC_MODE { SmmCpuSyncModeTradition, SmmCpuSyncModeRelaxedAp, SmmCpuSyncModeMax }

Functions

EFI_STATUS EFIAPI | SmmReadSaveState (IN CONST EFI_SMM_CPU_PROTOCOL *This, IN UINTN Width, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, OUT VOID *Buffer)
EFI_STATUS EFIAPI | SmmWriteSaveState (IN CONST EFI_SMM_CPU_PROTOCOL *This, IN UINTN Width, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN CpuIndex, IN CONST VOID *Buffer)
EFI_STATUS EFIAPI | ReadSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, OUT VOID *Buffer)
EFI_STATUS EFIAPI | WriteSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer)
VOID EFIAPI | SmmRelocationSemaphoreComplete (VOID)
UINT32 | Gen4GPageTable (IN BOOLEAN Is32BitPageTable)
UINT32 | InitializeMpServiceData (IN VOID *Stacks, IN UINTN StackSize)
VOID InitializeSmmTimer (VOID)
UINT64 EFIAPI | StartSyncTimer (VOID)
BOOLEAN EFIAPI | IsSyncTimerTimeout (IN UINT64 Timer)
VOID EFIAPI | InitializeIDTSmmStackGuard (VOID)
VOID * | InitGdt (IN UINTN Cr3, OUT UINTN *GdtStepSize)
EFI_STATUS EFIAPI | RegisterSmmEntry (IN CONST EFI_SMM_CONFIGURATION_PROTOCOL *This, IN EFI_SMM_ENTRY_POINT SmmEntryPoint)
UINT32 | SmmInitPageTable (VOID)
EFI_STATUS EFIAPI | SmmStartupThisAp (IN EFI_AP_PROCEDURE Procedure, IN UINTN CpuIndex, IN OUT VOID *ProcArguments OPTIONAL)
EFI_STATUS EFIAPI | SmmBlockingStartupThisAp (IN EFI_AP_PROCEDURE Procedure, IN UINTN CpuIndex, IN OUT VOID *ProcArguments OPTIONAL)
EFI_STATUS EFIAPI | SmmSetMemoryAttributes (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | SmmClearMemoryAttributes (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
VOID EFIAPI | InitializeMpSyncData (VOID)
VOID | FindSmramInfo (OUT UINT32 *SmrrBase, OUT UINT32 *SmrrSize)
VOID EFIAPI | SmmRelocateBases (VOID)
VOID EFIAPI | SmiPFHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_SYSTEM_CONTEXT SystemContext)
VOID PerformRemainingTasks (VOID)
VOID PerformPreTasks (VOID)
VOID | InitMsrSpinLockByIndex (IN UINT32 MsrIndex)
VOID | SemaphoreHook (IN UINTN CpuIndex, IN volatile BOOLEAN *RebasedFlag)
VOID ConfigSmmCodeAccessCheck (VOID)
UINT64 EFIAPI | HookReturnFromSmm (IN UINTN CpuIndex, SMRAM_SAVE_STATE_MAP *CpuState, UINT64 NewInstructionPointer32, UINT64 NewInstructionPointer)
UINTN EFIAPI | GetSmiHandlerSize (VOID)
VOID EFIAPI | InstallSmiHandler (IN UINTN CpuIndex, IN UINT32 SmBase, IN VOID *SmiStack, IN UINTN StackSize, IN UINTN GdtBase, IN UINTN GdtSize, IN UINTN IdtBase, IN UINTN IdtSize, IN UINT32 Cr3)
VOID | DumpModuleInfoByIp (IN UINTN CallerIpAddress)
VOID SetMemMapAttributes (VOID)
VOID SetUefiMemMapAttributes (VOID)
BOOLEAN | IsSmmCommBufferForbiddenAddress (IN UINT64 Address)
VOID GetUefiMemoryMap (VOID)
VOID SetPageTableAttributes (VOID)
UINTN | GetPageTableBase (VOID)
EFI_STATUS EFIAPI | SmmSetMemoryAttributesEx (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, OUT BOOLEAN *IsSplitted OPTIONAL)
EFI_STATUS EFIAPI | SmmClearMemoryAttributesEx (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, OUT BOOLEAN *IsSplitted OPTIONAL)
VOID * | AllocatePageTableMemory (IN UINTN Pages)
VOID * | AllocateCodePages (IN UINTN Pages)
VOID * | AllocateAlignedCodePages (IN UINTN Pages, IN UINTN Alignment)
VOID | InitSmmS3ResumeState (IN UINT32 Cr3)
VOID GetAcpiCpuData (VOID)
VOID RestoreSmmConfigurationInS3 (VOID)
VOID GetAcpiS3EnableFlag (VOID)
VOID | TransferApToSafeState (IN UINTN ApHltLoopCode, IN UINTN TopOfStack, IN UINTN NumberToFinishAddress)
EFI_STATUS EFIAPI | EdkiiSmmSetMemoryAttributes (IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | EdkiiSmmClearMemoryAttributes (IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | EdkiiSmmGetMemoryAttributes (IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 *Attributes)
VOID EFIAPI | PiSmmCpuSmmInitFixupAddress ()
VOID EFIAPI | PiSmmCpuSmiEntryFixupAddress ()

Variables

SMM_CPU_PRIVATE_DATA * | gSmmCpuPrivate
CPU_HOT_PLUG_DATA | mCpuHotPlugData
UINTN | mMaxNumberOfCpus
UINTN | mNumberOfCpus
EFI_SMM_CPU_PROTOCOL | mSmmCpu
UINT8 | mSmmSaveStateRegisterLma
SMM_SUPERVISOR_PROTOCOL * | SmmSupervisor
EFI_GUID | gSmmSupervisorProtocolGuid = SMM_SUPERVISOR_GUID
BOOLEAN | SmmAmiBufferValidationLibCsmEnabled
CONST UINT8 | gcSmmInitTemplate []
CONST UINT16 | gcSmmInitSize
X86_ASSEMBLY_PATCH_LABEL | gPatchSmmCr0
UINT32 | mSmmCr0
X86_ASSEMBLY_PATCH_LABEL | gPatchSmmCr3
UINT32 | mSmmCr4
X86_ASSEMBLY_PATCH_LABEL | gPatchSmmCr4
X86_ASSEMBLY_PATCH_LABEL | gPatchSmmInitStack
IA32_DESCRIPTOR | gcSmiGdtr
EFI_PHYSICAL_ADDRESS | mGdtBuffer
UINTN | mGdtBufferSize
IA32_DESCRIPTOR | gcSmiIdtr
VOID * | gcSmiIdtrPtr
UINT64 | gPhyMask
SMM_DISPATCHER_MP_SYNC_DATA * | mSmmMpSyncData
UINTN | mSmmStackArrayBase
UINTN | mSmmStackArrayEnd
UINTN | mSmmStackSize
EFI_SMM_CPU_SERVICE_PROTOCOL | mSmmCpuService
IA32_DESCRIPTOR | gcSmiInitGdtr
SMM_CPU_SEMAPHORES | mSmmCpuSemaphores
UINTN | mSemaphoreSize
SPIN_LOCK * | mPFLock
SPIN_LOCK * | mConfigSmmCodeAccessCheckLock
EFI_SMRAM_DESCRIPTOR * | mSmmCpuSmramRanges
UINTN | mSmmCpuSmramRangeCount
UINT8 | mPhysicalAddressBits
UINT64 | mAddressEncMask

Detailed Description

Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.

Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID* AllocateAlignedCodePages | ( | IN UINTN | Pages,
 |  | IN UINTN | Alignment
 | ) |  |

Allocate aligned pages for code.

Parameters
[in] | Pages | Number of pages to be allocated.
[in] | Alignment | The requested alignment of the allocation. Must be a power of two. If Alignment is zero, then byte alignment is used.
Returns
Allocated memory.
VOID* AllocateCodePages ( IN UINTN Pages )

Allocate pages for code.

Parameters
[in] Pages Number of pages to be allocated.
Returns
Allocated memory.
VOID* AllocatePageTableMemory ( IN UINTN Pages )

This API provides a way to allocate memory for page table.

This API can be called more once to allocate memory for page tables.

Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.

This API provides a way to allocate memory for page table.

This API can be called more than once to allocate memory for page tables.

Allocates the number of 4KB pages and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary.

If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.

This API provides a way to allocate memory for page table.

Parameters
Pages The number of 4 KB pages to allocate.
Returns
A pointer to the allocated buffer or NULL if allocation fails.
VOID ConfigSmmCodeAccessCheck ( VOID )

Configure SMM Code Access Check feature for all processors. SMM Feature Control MSR will be locked after configuration.

VOID DumpModuleInfoByIp ( IN UINTN CallerIpAddress )

Search module name by input IP address and output it.

Parameters
CallerIpAddress Caller instruction pointer.
EFI_STATUS EFIAPI EdkiiSmmClearMemoryAttributes | ( | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function clears given attributes of the memory region specified by BaseAddress and Length.

Parameters
This | The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to clear for the memory region.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be cleared together.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI EdkiiSmmGetMemoryAttributes | ( | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 * | Attributes
 | ) |  |

This function retrieves the attributes of the memory region specified by BaseAddress and Length. If different attributes are got from different part of the memory region, EFI_NO_MAPPING will be returned.

Parameters
This | The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | Pointer to attributes returned.
Return values
EFI_SUCCESS | The attributes got for the memory region.
EFI_INVALID_PARAMETER | Length is zero. Attributes is NULL.
EFI_NO_MAPPING | Attributes are not consistent cross the memory region.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI EdkiiSmmSetMemoryAttributes | ( | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function set given attributes of the memory region specified by BaseAddress and Length.

Parameters
This | The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
VOID FindSmramInfo | ( | OUT UINT32 * | SmrrBase,
 |  | OUT UINT32 * | SmrrSize
 | ) |  |

Find out SMRAM information including SMRR base and SMRR size.

Parameters
SmrrBase | SMRR base
SmrrSize | SMRR size
UINT32 Gen4GPageTable ( IN BOOLEAN Is32BitPageTable )

Create 4G PageTable in SMRAM.

Parameters
[in] Is32BitPageTable Whether the page table is 32-bit PAE
Returns
PageTable Address
VOID GetAcpiCpuData ( VOID )

Get ACPI CPU data.

Return ACPI_CPU_DATA data.

Returns
Pointer to ACPI_CPU_DATA data.
VOID GetAcpiS3EnableFlag ( VOID )

Get ACPI S3 enable flag.

UINTN GetPageTableBase ( VOID )

Return page table base.

Returns
page table base.
UINTN EFIAPI GetSmiHandlerSize ( VOID )

Get the size of the SMI Handler in bytes.

Return values
The size, in bytes, of the SMI Handler.
VOID GetUefiMemoryMap ( VOID )

This function caches the UEFI memory map information.

UINT64 EFIAPI HookReturnFromSmm | ( | IN UINTN | CpuIndex,
 |  | SMRAM_SAVE_STATE_MAP * | CpuState,
 |  | UINT64 | NewInstructionPointer32,
 |  | UINT64 | NewInstructionPointer
 | ) |  |

Hook the code executed immediately after an RSM instruction on the currently executing CPU. The mode of code executed immediately after RSM must be detected, and the appropriate hook must be selected. Always clear the auto HALT restart flag if it is set.

Parameters
[in] | CpuIndex | The processor index for the currently executing CPU.
[in] | CpuState | Pointer to SMRAM Save State Map for the currently executing CPU.
[in] | NewInstructionPointer32 | Instruction pointer to use if resuming to 32-bit mode from 64-bit SMM.
[in] | NewInstructionPointer | Instruction pointer to use if resuming to same mode as SMM.
Return values
The value of the original instruction pointer before it was hooked.
VOID* InitGdt | ( | IN UINTN | Cr3,
 |  | OUT UINTN * | GdtStepSize
 | ) |  |

Initialize Gdt for all processors.

Parameters
[in] | Cr3 | CR3 value.
[out] | GdtStepSize | The step size for GDT table.
Returns
GdtBase for processor 0. GdtBase for processor X is: GdtBase + (GdtStepSize * X)
VOID EFIAPI InitializeIDTSmmStackGuard ( VOID )

Initialize IDT for SMM Stack Guard.

UINT32 InitializeMpServiceData | ( | IN VOID * | Stacks,
 |  | IN UINTN | StackSize
 | ) |  |

Initialize global data for MP synchronization.

Parameters
Stacks | Base address of SMI stack buffer for all processors.
StackSize | Stack size for each processor in SMM.
VOID EFIAPI InitializeMpSyncData ( VOID )

Initialize MP synchronization data.

Initialize un-cacheable data.

VOID InitializeSmmTimer ( VOID )

Initialize Timer for SMM AP Sync.

VOID InitMsrSpinLockByIndex ( IN UINT32 MsrIndex )

Initialize MSR spin lock by MSR index.

Parameters
MsrIndex MSR index value.
VOID InitSmmS3ResumeState ( IN UINT32 Cr3 )

Initialize SMM S3 resume state structure used during S3 Resume.

Parameters
[in] Cr3 The base address of the page tables to use in SMM.
VOID EFIAPI InstallSmiHandler | ( | IN UINTN | CpuIndex,
 |  | IN UINT32 | SmBase,
 |  | IN VOID * | SmiStack,
 |  | IN UINTN | StackSize,
 |  | IN UINTN | GdtBase,
 |  | IN UINTN | GdtSize,
 |  | IN UINTN | IdtBase,
 |  | IN UINTN | IdtSize,
 |  | IN UINT32 | Cr3
 | ) |  |

Install the SMI handler for the CPU specified by CpuIndex. This function is called by the CPU that was elected as monarch during System Management Mode initialization.

Parameters
[in] | CpuIndex | The index of the CPU to install the custom SMI handler. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | SmBase | The SMBASE address for the CPU specified by CpuIndex.
[in] | SmiStack | The stack to use when an SMI is processed by the the CPU specified by CpuIndex.
[in] | StackSize | The size, in bytes, if the stack used when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtBase | The base address of the GDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtSize | The size, in bytes, of the GDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtBase | The base address of the IDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtSize | The size, in bytes, of the IDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | Cr3 | The base address of the page tables to use when an SMI is processed by the CPU specified by CpuIndex.
BOOLEAN IsSmmCommBufferForbiddenAddress ( IN UINT64 Address )

Return if the Address is forbidden as SMM communication buffer.

Parameters
[in] Address the address to be checked
Returns
TRUE The address is forbidden as SMM communication buffer.
FALSE The address is allowed as SMM communication buffer.
BOOLEAN EFIAPI IsSyncTimerTimeout ( IN UINT64 Timer )

Check if the SMM AP Sync timer is timeout.

Parameters
Timer The start timer from the begin.
VOID PerformPreTasks ( VOID )

Perform the pre tasks.

VOID PerformRemainingTasks ( VOID )

Perform the remaining tasks.

VOID EFIAPI PiSmmCpuSmiEntryFixupAddress ( )

This function fixes up the address of the global variable or function referred in SmiEntry assembly files to be the absoute address.

VOID EFIAPI PiSmmCpuSmmInitFixupAddress ( )

This function fixes up the address of the global variable or function referred in SmmInit assembly files to be the absoute address.

EFI_STATUS EFIAPI ReadSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | OUT VOID * | Buffer
 | ) |  |

Read a CPU Save State register on the target processor.

This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map.

This function supports reading a CPU Save State register in SMBase relocation handler.

Parameters
[in] | CpuIndex | Specifies the zero-based index of the CPU save state.
[in] | RegisterIndex | Index into mSmmCpuWidthOffset[] look up table.
[in] | Width | The number of bytes to read from the CPU save state.
[out] | Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State.
EFI_NOT_FOUND | The register is not defined for the Save State of Processor.
EFI_INVALID_PARAMTER | This or Buffer is NULL.
EFI_STATUS EFIAPI RegisterSmmEntry | ( | IN CONST EFI_SMM_CONFIGURATION_PROTOCOL * | This,
 |  | IN EFI_SMM_ENTRY_POINT | SmmEntryPoint
 | ) |  |

Register the SMM Foundation entry point.

Parameters
This | Pointer to EFI_SMM_CONFIGURATION_PROTOCOL instance
SmmEntryPoint | SMM Foundation EntryPoint
Return values
EFI_SUCCESS Successfully to register SMM foundation entry point
VOID RestoreSmmConfigurationInS3 ( VOID )

Restore SMM Configuration in S3 boot path.

VOID SemaphoreHook | ( | IN UINTN | CpuIndex,
 |  | IN volatile BOOLEAN * | RebasedFlag
 | ) |  |

Hook return address of SMM Save State so that semaphore code can be executed immediately after AP exits SMM to indicate to the BSP that an AP has exited SMM after SMBASE relocation.

Parameters
[in] | CpuIndex | The processor index.
[in] | RebasedFlag | A pointer to a flag that is set to TRUE immediately after AP exits SMM.
VOID SetMemMapAttributes ( VOID )

This function sets memory attribute according to MemoryAttributesTable.

VOID SetPageTableAttributes ( VOID )

This function sets memory attribute for page table.

VOID SetUefiMemMapAttributes ( VOID )

This function sets UEFI memory attribute according to UEFI memory map.

This function sets UEFI memory attribute according to UEFI memory map.

The normal memory region is marked as not present, such as EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory, EfiUnusableMemory, EfiACPIReclaimMemory.

VOID EFIAPI SmiPFHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

Page Fault handler for SMM use.

Parameters
InterruptType | Defines the type of interrupt or exception that occurred on the processor.This parameter is processor architecture specific.
SystemContext | A pointer to the processor context when the interrupt occurred on the processor.

ThePage Fault handler wrapper for SMM use.

Parameters
InterruptType | Defines the type of interrupt or exception that occurred on the processor.This parameter is processor architecture specific.
SystemContext | A pointer to the processor context when the interrupt occurred on the processor.
EFI_STATUS EFIAPI SmmBlockingStartupThisAp | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | CpuIndex,
 |  | IN OUT VOID *ProcArguments | OPTIONAL
 | ) |  |

Schedule a procedure to run on the specified CPU in a blocking fashion.

Parameters
Procedure | The address of the procedure to run
CpuIndex | Target CPU Index
ProcArguments | The parameter to pass to the procedure
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | The procedure has been successfully scheduled

Schedule a procedure to run on the specified CPU in blocking mode.

Parameters
[in] | Procedure | The address of the procedure to run
[in] | CpuIndex | Target CPU Index
[in,out] | ProcArguments | The parameter to pass to the procedure
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | The procedure has been successfully scheduled
EFI_STATUS EFIAPI SmmClearMemoryAttributes | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function clears the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to clear for the memory region.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.

This function clears the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to clear for the memory region.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be cleared together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI SmmClearMemoryAttributesEx | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | OUT BOOLEAN *IsSplitted | OPTIONAL
 | ) |  |

This function clears the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to clear for the memory region.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.

This function clears the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to clear for the memory region.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be cleared together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
UINT32 SmmInitPageTable ( VOID )

Create PageTable for SMM use.

Returns
PageTable Address

Create PageTable for SMM use.

Returns
The address of PML4 (to set CR3).
EFI_STATUS EFIAPI SmmReadSaveState | ( | IN CONST EFI_SMM_CPU_PROTOCOL * | This,
 |  | IN UINTN | Width,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | CpuIndex,
 |  | OUT VOID * | Buffer
 | ) |  |

Read information from the CPU save state.

Parameters
This | EFI_SMM_CPU_PROTOCOL instance
Width | The number of bytes to read from the CPU save state.
Register | Specifies the CPU register to read form the save state.
CpuIndex | Specifies the zero-based index of the CPU save state
Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State
EFI_NOT_FOUND | The register is not defined for the Save State of Processor
EFI_INVALID_PARAMTER | This or Buffer is NULL.

Read information from the CPU save state.

Parameters
This | EFI_SMM_CPU_PROTOCOL instance
Width | The number of bytes to read from the CPU save state.
Register | Specifies the CPU register to read form the save state.
CpuIndex | Specifies the zero-based index of the CPU save state.
Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State
EFI_NOT_FOUND | The register is not defined for the Save State of Processor
EFI_INVALID_PARAMTER | This or Buffer is NULL.
VOID EFIAPI SmmRelocateBases ( VOID )

Relocate SmmBases for each processor.

Execute on first boot and all S3 resumes

VOID EFIAPI SmmRelocationSemaphoreComplete ( VOID )

Semaphore operation for all processor relocate SMMBase.

EFI_STATUS EFIAPI SmmSetMemoryAttributes | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function sets the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.

This function sets the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI SmmSetMemoryAttributesEx | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | OUT BOOLEAN *IsSplitted | OPTIONAL
 | ) |  |

This function sets the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI SmmStartupThisAp | ( | IN EFI_AP_PROCEDURE | Procedure,
 |  | IN UINTN | CpuIndex,
 |  | IN OUT VOID *ProcArguments | OPTIONAL
 | ) |  |

Schedule a procedure to run on the specified CPU.

Parameters
Procedure | The address of the procedure to run
CpuIndex | Target CPU number
ProcArguments | The parameter to pass to the procedure
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | - The procedure has been successfully scheduled

Schedule a procedure to run on the specified CPU.

Parameters
Procedure | The address of the procedure to run
CpuIndex | Target CPU Index
ProcArguments | The parameter to pass to the procedure
Return values
EFI_INVALID_PARAMETER | CpuNumber not valid
EFI_INVALID_PARAMETER | CpuNumber specifying BSP
EFI_INVALID_PARAMETER | The AP specified by CpuNumber did not enter SMM
EFI_INVALID_PARAMETER | The AP specified by CpuNumber is busy
EFI_SUCCESS | The procedure has been successfully scheduled
EFI_STATUS EFIAPI SmmWriteSaveState | ( | IN CONST EFI_SMM_CPU_PROTOCOL * | This,
 |  | IN UINTN | Width,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | CpuIndex,
 |  | IN CONST VOID * | Buffer
 | ) |  |

Write data to the CPU save state.

Parameters
This | EFI_SMM_CPU_PROTOCOL instance
Width | The number of bytes to read from the CPU save state.
Register | Specifies the CPU register to write to the save state.
CpuIndex | Specifies the zero-based index of the CPU save state
Buffer | Upon entry, this holds the new CPU register value.
Return values
EFI_SUCCESS | The register was written from Save State
EFI_NOT_FOUND | The register is not defined for the Save State of Processor
EFI_INVALID_PARAMTER | ProcessorIndex or Width is not correct
UINT64 EFIAPI StartSyncTimer ( VOID )

Start Timer for SMM AP Sync.

VOID TransferApToSafeState | ( | IN UINTN | ApHltLoopCode,
 |  | IN UINTN | TopOfStack,
 |  | IN UINTN | NumberToFinishAddress
 | ) |  |

Transfer AP to safe hlt-loop after it finished restore CPU features on S3 patch.

Parameters
[in] | ApHltLoopCode | The address of the safe hlt-loop function.
[in] | TopOfStack | A pointer to the new stack to use for the ApHltLoopCode.
[in] | NumberToFinishAddress | Address of Semaphore of APs finish count.
EFI_STATUS EFIAPI WriteSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | IN CONST VOID * | Buffer
 | ) |  |

Write value to a CPU Save State register on the target processor.

This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map.

This function supports writing a CPU Save State register in SMBase relocation handler.

Parameters
[in] | CpuIndex | Specifies the zero-based index of the CPU save state.
[in] | RegisterIndex | Index into mSmmCpuWidthOffset[] look up table.
[in] | Width | The number of bytes to read from the CPU save state.
[in] | Buffer | Upon entry, this holds the new CPU register value.
Return values
EFI_SUCCESS | The register was written to Save State.
EFI_NOT_FOUND | The register is not defined for the Save State of Processor.
EFI_INVALID_PARAMTER | ProcessorIndex or Width is not correct.

Variable Documentation

EFI_SMM_CPU_PROTOCOL mSmmCpu

SMM CPU Protocol instance

UINT8 mSmmSaveStateRegisterLma

The mode of the CPU at the time an SMI occurs

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.uni File Reference

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PiSmmCpuDxeSmm.uni File Reference

Detailed Description

CPU SMM driver.

This SMM driver performs SMM initialization, deploy SMM Entry Vector, provides CPU specific services in SMM.

Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmmExtra.uni File Reference

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PiSmmCpuDxeSmmExtra.uni File Reference

Detailed Description

PiSmmCpuDxeSmm Localized Strings and Content

Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c File Reference

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Functions | Variables
SmmCpuMemoryManagement.c File Reference

Functions

UINTN | GetPageTableBase (VOID)
UINTN | PageAttributeToLength (IN PAGE_ATTRIBUTE PageAttribute)
UINTN | PageAttributeToMask (IN PAGE_ATTRIBUTE PageAttribute)
VOID * | GetPageTableEntry (IN PHYSICAL_ADDRESS Address, OUT PAGE_ATTRIBUTE *PageAttribute)
UINT64 | GetAttributesFromPageEntry (IN UINT64 *PageEntry)
VOID | ConvertPageEntryAttribute (IN UINT64 *PageEntry, IN UINT64 Attributes, IN BOOLEAN IsSet, OUT BOOLEAN *IsModified)
PAGE_ATTRIBUTE | NeedSplitPage (IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 *PageEntry, IN PAGE_ATTRIBUTE PageAttribute)
RETURN_STATUS | SplitPage (IN UINT64 *PageEntry, IN PAGE_ATTRIBUTE PageAttribute, IN PAGE_ATTRIBUTE SplitAttribute)
RETURN_STATUS EFIAPI | ConvertMemoryPageAttributes (IN PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, IN BOOLEAN IsSet, OUT BOOLEAN *IsSplitted, OPTIONAL OUT BOOLEAN *IsModified OPTIONAL)
VOID EFIAPI | FlushTlbOnCurrentProcessor (IN OUT VOID *Buffer)
VOID FlushTlbForAll (VOID)
EFI_STATUS EFIAPI | SmmSetMemoryAttributesEx (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, OUT BOOLEAN *IsSplitted OPTIONAL)
EFI_STATUS EFIAPI | SmmClearMemoryAttributesEx (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes, OUT BOOLEAN *IsSplitted OPTIONAL)
EFI_STATUS EFIAPI | SmmSetMemoryAttributes (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | SmmClearMemoryAttributes (IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | SmmGetSystemConfigurationTable (IN EFI_GUID *TableGuid, OUT VOID **Table)
VOID PatchSmmSaveStateMap (VOID)
VOID PatchGdtIdtMap (VOID)
VOID SetMemMapAttributes (VOID)
STATIC VOID | SortMemoryMap (IN OUT EFI_MEMORY_DESCRIPTOR *MemoryMap, IN UINTN MemoryMapSize, IN UINTN DescriptorSize)
BOOLEAN | IsUefiPageNotPresent (IN EFI_MEMORY_DESCRIPTOR *MemoryMap)
STATIC VOID | MergeMemoryMapForNotPresentEntry (IN OUT EFI_MEMORY_DESCRIPTOR *MemoryMap, IN OUT UINTN *MemoryMapSize, IN UINTN DescriptorSize)
VOID GetGcdMemoryMap (VOID)
VOID GetUefiMemoryAttributesTable (VOID)
VOID GetUefiMemoryMap (VOID)
VOID SetUefiMemMapAttributes (VOID)
BOOLEAN | IsSmmCommBufferForbiddenAddress (IN UINT64 Address)
EFI_STATUS EFIAPI | EdkiiSmmSetMemoryAttributes (IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | EdkiiSmmClearMemoryAttributes (IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, IN UINT64 Attributes)
EFI_STATUS EFIAPI | EdkiiSmmGetMemoryAttributes (IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL *This, IN EFI_PHYSICAL_ADDRESS BaseAddress, IN UINT64 Length, OUT UINT64 *Attributes)

Variables

EFI_MEMORY_DESCRIPTOR * | mUefiMemoryMap
UINTN | mUefiMemoryMapSize
UINTN | mUefiDescriptorSize
EFI_GCD_MEMORY_SPACE_DESCRIPTOR * | mGcdMemSpace = NULL
UINTN | mGcdMemNumberOfDesc = 0
EFI_MEMORY_ATTRIBUTES_TABLE * | mUefiMemoryAttributesTable = NULL
PAGE_ATTRIBUTE_TABLE | mPageAttributeTable []

Detailed Description

Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

RETURN_STATUS EFIAPI ConvertMemoryPageAttributes | ( | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | IN BOOLEAN | IsSet,
 |  | OUT BOOLEAN * | IsSplitted,
 |  | OPTIONAL OUT BOOLEAN *IsModified | OPTIONAL
 | ) |  |

This function modifies the page attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Caller should make sure BaseAddress and Length is at page boundary.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to modify for the memory region.
[in] | IsSet | TRUE means to set attributes. FALSE means to clear attributes.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
[out] | IsModified | TRUE means page table modified. FALSE means page table not modified.
Return values
RETURN_SUCCESS | The attributes were modified for the memory region.
RETURN_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
RETURN_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
RETURN_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
RETURN_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
VOID ConvertPageEntryAttribute | ( | IN UINT64 * | PageEntry,
 |  | IN UINT64 | Attributes,
 |  | IN BOOLEAN | IsSet,
 |  | OUT BOOLEAN * | IsModified
 | ) |  |

Modify memory attributes of page entry.

Parameters
[in] | PageEntry | The page entry.
[in] | Attributes | The bit mask of attributes to modify for the memory region.
[in] | IsSet | TRUE means to set attributes. FALSE means to clear attributes.
[out] | IsModified | TRUE means page table modified. FALSE means page table not modified.
EFI_STATUS EFIAPI EdkiiSmmClearMemoryAttributes | ( | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function clears given attributes of the memory region specified by BaseAddress and Length.

Parameters
This | The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to clear for the memory region.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be cleared together.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI EdkiiSmmGetMemoryAttributes | ( | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | OUT UINT64 * | Attributes
 | ) |  |

This function retrieves the attributes of the memory region specified by BaseAddress and Length. If different attributes are got from different part of the memory region, EFI_NO_MAPPING will be returned.

Parameters
This | The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | Pointer to attributes returned.
Return values
EFI_SUCCESS | The attributes got for the memory region.
EFI_INVALID_PARAMETER | Length is zero. Attributes is NULL.
EFI_NO_MAPPING | Attributes are not consistent cross the memory region.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI EdkiiSmmSetMemoryAttributes | ( | IN EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL * | This,
 |  | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function set given attributes of the memory region specified by BaseAddress and Length.

Parameters
This | The EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL instance.
BaseAddress | The physical address that is the start address of a memory region.
Length | The size in bytes of the memory region.
Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
VOID FlushTlbForAll ( VOID )

FlushTlb for all processors.

VOID EFIAPI FlushTlbOnCurrentProcessor ( IN OUT VOID * Buffer )

FlushTlb on current processor.

Parameters
[in,out] Buffer Pointer to private data buffer.
UINT64 GetAttributesFromPageEntry ( IN UINT64 * PageEntry )

Return memory attributes of page entry.

Parameters
[in] PageEntry The page entry.
Returns
Memory attributes of page entry.
VOID GetGcdMemoryMap ( VOID )

This function caches the GCD memory map information.

UINTN GetPageTableBase ( VOID )

Return page table base.

Returns
page table base.
VOID* GetPageTableEntry | ( | IN PHYSICAL_ADDRESS | Address,
 |  | OUT PAGE_ATTRIBUTE * | PageAttribute
 | ) |  |

Return page table entry to match the address.

Parameters
[in] | Address | The address to be checked.
[out] | PageAttributes | The page attribute of the page entry.
Returns
The page entry.
VOID GetUefiMemoryAttributesTable ( VOID )

Get UEFI MemoryAttributesTable.

VOID GetUefiMemoryMap ( VOID )

This function caches the UEFI memory map information.

BOOLEAN IsSmmCommBufferForbiddenAddress ( IN UINT64 Address )

Return if the Address is forbidden as SMM communication buffer.

Parameters
[in] Address the address to be checked
Returns
TRUE The address is forbidden as SMM communication buffer.
FALSE The address is allowed as SMM communication buffer.
BOOLEAN IsUefiPageNotPresent ( IN EFI_MEMORY_DESCRIPTOR * MemoryMap )

Return if a UEFI memory page should be marked as not present in SMM page table. If the memory map entries type is EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory, EfiUnusableMemory, EfiACPIReclaimMemory, return TRUE. Or return FALSE.

Parameters
[in] MemoryMap A pointer to the memory descriptor.
Returns
TRUE The memory described will be marked as not present in SMM page table.
FALSE The memory described will not be marked as not present in SMM page table.
STATIC VOID MergeMemoryMapForNotPresentEntry | ( | IN OUT EFI_MEMORY_DESCRIPTOR * | MemoryMap,
 |  | IN OUT UINTN * | MemoryMapSize,
 |  | IN UINTN | DescriptorSize
 | ) |  |

Merge continous memory map entries whose type is EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory, EfiUnusableMemory, EfiACPIReclaimMemory, because the memory described by these entries will be set as NOT present in SMM page table.

Parameters
[in,out] | MemoryMap | A pointer to the buffer in which firmware places the current memory map.
[in,out] | MemoryMapSize | A pointer to the size, in bytes, of the MemoryMap buffer. On input, this is the size of the current memory map. On output, it is the size of new memory map after merge.
[in] | DescriptorSize | Size, in bytes, of an individual EFI_MEMORY_DESCRIPTOR.
PAGE_ATTRIBUTE NeedSplitPage | ( | IN PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 * | PageEntry,
 |  | IN PAGE_ATTRIBUTE | PageAttribute
 | ) |  |

This function returns if there is need to split page entry.

Parameters
[in] | BaseAddress | The base address to be checked.
[in] | Length | The length to be checked.
[in] | PageEntry | The page entry to be checked.
[in] | PageAttribute | The page attribute of the page entry.
Return values
SplitAttributes on if there is need to split page entry.
UINTN PageAttributeToLength ( IN PAGE_ATTRIBUTE PageAttribute )

Return length according to page attributes.

Parameters
[in] PageAttributes The page attribute of the page entry.
Returns
The length of page entry.
UINTN PageAttributeToMask ( IN PAGE_ATTRIBUTE PageAttribute )

Return address mask according to page attributes.

Parameters
[in] PageAttributes The page attribute of the page entry.
Returns
The address mask of page entry.
VOID PatchGdtIdtMap ( VOID )

This function sets GDT/IDT buffer to be RO and XP.

VOID PatchSmmSaveStateMap ( VOID )

This function sets SMM save state buffer to be RW and XP.

VOID SetMemMapAttributes ( VOID )

This function sets memory attribute according to MemoryAttributesTable.

VOID SetUefiMemMapAttributes ( VOID )

This function sets UEFI memory attribute according to UEFI memory map.

The normal memory region is marked as not present, such as EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory, EfiUnusableMemory, EfiACPIReclaimMemory.

EFI_STATUS EFIAPI SmmClearMemoryAttributes | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function clears the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to clear for the memory region.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be cleared together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI SmmClearMemoryAttributesEx | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | OUT BOOLEAN *IsSplitted | OPTIONAL
 | ) |  |

This function clears the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to clear for the memory region.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
Return values
EFI_SUCCESS | The attributes were cleared for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be cleared together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI SmmGetSystemConfigurationTable | ( | IN EFI_GUID * | TableGuid,
 |  | OUT VOID ** | Table
 | ) |  |

Retrieves a pointer to the system configuration table from the SMM System Table based on a specified GUID.

Parameters
[in] | TableGuid | The pointer to table's GUID type.
[out] | Table | The pointer to the table associated with TableGuid in the EFI System Table.
Return values
EFI_SUCCESS | A configuration table matching TableGuid was found.
EFI_NOT_FOUND | A configuration table matching TableGuid could not be found.
EFI_STATUS EFIAPI SmmSetMemoryAttributes | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes
 | ) |  |

This function sets the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not supported for the memory resource range specified by BaseAddress and Length.
EFI_STATUS EFIAPI SmmSetMemoryAttributesEx | ( | IN EFI_PHYSICAL_ADDRESS | BaseAddress,
 |  | IN UINT64 | Length,
 |  | IN UINT64 | Attributes,
 |  | OUT BOOLEAN *IsSplitted | OPTIONAL
 | ) |  |

This function sets the attributes for the memory region specified by BaseAddress and Length from their current attributes to the attributes specified by Attributes.

Parameters
[in] | BaseAddress | The physical address that is the start address of a memory region.
[in] | Length | The size in bytes of the memory region.
[in] | Attributes | The bit mask of attributes to set for the memory region.
[out] | IsSplitted | TRUE means page table splitted. FALSE means page table not splitted.
Return values
EFI_SUCCESS | The attributes were set for the memory region.
EFI_ACCESS_DENIED | The attributes for the memory resource range specified by BaseAddress and Length cannot be modified.
EFI_INVALID_PARAMETER | Length is zero. Attributes specified an illegal combination of attributes that cannot be set together.
EFI_OUT_OF_RESOURCES | There are not enough system resources to modify the attributes of the memory resource range.
EFI_UNSUPPORTED | The processor does not support one or more bytes of the memory resource range specified by BaseAddress and Length. The bit mask of attributes is not support for the memory resource range specified by BaseAddress and Length.
STATIC VOID SortMemoryMap | ( | IN OUT EFI_MEMORY_DESCRIPTOR * | MemoryMap,
 |  | IN UINTN | MemoryMapSize,
 |  | IN UINTN | DescriptorSize
 | ) |  |

Sort memory map entries based upon PhysicalStart, from low to high.

Parameters
MemoryMap | A pointer to the buffer in which firmware places the current memory map.
MemoryMapSize | Size, in bytes, of the MemoryMap buffer.
DescriptorSize | Size, in bytes, of an individual EFI_MEMORY_DESCRIPTOR.
RETURN_STATUS SplitPage | ( | IN UINT64 * | PageEntry,
 |  | IN PAGE_ATTRIBUTE | PageAttribute,
 |  | IN PAGE_ATTRIBUTE | SplitAttribute
 | ) |  |

This function splits one page entry to small page entries.

Parameters
[in] | PageEntry | The page entry to be splitted.
[in] | PageAttribute | The page attribute of the page entry.
[in] | SplitAttribute | How to split the page entry.
Return values
RETURN_SUCCESS | The page entry is splitted.
RETURN_UNSUPPORTED | The page entry does not support to be splitted.
RETURN_OUT_OF_RESOURCES | No resource to split page entry.

Variable Documentation

PAGE_ATTRIBUTE_TABLE mPageAttributeTable[]
Initial value:
= {
{Page4K, SIZE_4KB, PAGING_4K_ADDRESS_MASK_64},
{Page2M, SIZE_2MB, PAGING_2M_ADDRESS_MASK_64},
{Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Functions | Variables
SmmProfile.c File Reference

Functions

VOID DisableBTS (VOID)
VOID EnableBTS (VOID)
UINTN | GetCpuIndex (VOID)
UINT64 | GetSourceFromDestinationOnBts (UINTN CpuIndex, UINT64 DestinationIP)
VOID EFIAPI | DebugExceptionHandler (IN EFI_EXCEPTION_TYPE InterruptType, IN EFI_SYSTEM_CONTEXT SystemContext)
BOOLEAN | IsInSmmRanges (IN EFI_PHYSICAL_ADDRESS Address)
BOOLEAN | IsAddressValid (IN EFI_PHYSICAL_ADDRESS Address, IN BOOLEAN *Nx)
BOOLEAN | IsAddressSplit (IN EFI_PHYSICAL_ADDRESS Address)
VOID InitProtectedMemRange (VOID)
VOID InitPaging (VOID)
VOID GetSmiCommandPort (VOID)
VOID SmmProfileStart (VOID)
EFI_STATUS EFIAPI | InitSmmProfileCallBack (IN CONST EFI_GUID *Protocol, IN VOID *Interface, IN EFI_HANDLE Handle)
VOID InitSmmProfileInternal (VOID)
VOID CheckFeatureSupported (VOID)
VOID ActivateSingleStepDB (VOID)
VOID ActivateLBR (VOID)
VOID | ActivateBTS (IN UINTN CpuIndex)
VOID SmmProfileRecordSmiNum (VOID)
VOID | ActivateSmmProfile (IN UINTN CpuIndex)
VOID | InitSmmProfile (UINT32 Cr3)
VOID | RestorePageTableBelow4G (UINT64 *PageTable, UINT64 PFAddress, UINTN CpuIndex, UINTN ErrorCode)
VOID | GuardPagePFHandler (UINTN ErrorCode)
VOID | SmmProfilePFHandler (UINTN Rip, UINTN ErrorCode)
VOID InitIdtr (VOID)

Variables

UINT32 | mSmmProfileCr3
SMM_PROFILE_HEADER * | mSmmProfileBase
MSR_DS_AREA_STRUCT * | mMsrDsAreaBase
UINTN | mSmmProfileSize
UINTN | mMsrDsAreaSize = SMM_PROFILE_DTS_SIZE
BOOLEAN | mXdSupported = TRUE
BOOLEAN | mXdEnabled = FALSE
BOOLEAN | mBtsSupported = FALSE
BOOLEAN | mSmmProfileStart = FALSE
BOOLEAN | mSetupDebugTrap = FALSE
UINTN * | mPFEntryCount
UINT64(* | mLastPFEntryValue )[MAX_PF_ENTRY_COUNT]
UINT64 *(* | mLastPFEntryPointer )[MAX_PF_ENTRY_COUNT]
MSR_DS_AREA_STRUCT ** | mMsrDsArea
BRANCH_TRACE_RECORD ** | mMsrBTSRecord
UINTN | mBTSRecordNumber
PEBS_RECORD ** | mMsrPEBSRecord
MEMORY_PROTECTION_RANGE * | mProtectionMemRange = NULL
UINTN | mProtectionMemRangeCount = 0
MEMORY_PROTECTION_RANGE | mProtectionMemRangeTemplate []
MEMORY_RANGE * | mSplitMemRange = NULL
UINTN | mSplitMemRangeCount = 0
UINT32 | mSmiCommandPort

Detailed Description

Enable SMM profile.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID ActivateBTS ( IN UINTN CpuIndex )

Enable branch trace store.

Parameters
CpuIndex The index of the processor.
VOID ActivateLBR ( VOID )

Enable last branch.

VOID ActivateSingleStepDB ( VOID )

Enable single step.

VOID ActivateSmmProfile ( IN UINTN CpuIndex )

Initialize processor environment for SMM profile.

Parameters
CpuIndex The index of the processor.
VOID CheckFeatureSupported ( VOID )

Check if XD feature is supported by a processor.

VOID EFIAPI DebugExceptionHandler | ( | IN EFI_EXCEPTION_TYPE | InterruptType,
 |  | IN EFI_SYSTEM_CONTEXT | SystemContext
 | ) |  |

SMM profile specific INT 1 (single-step) exception handler.

Parameters
InterruptType | Defines the type of interrupt or exception that occurred on the processor.This parameter is processor architecture specific.
SystemContext | A pointer to the processor context when the interrupt occurred on the processor.
VOID DisableBTS ( VOID )

Disable branch trace store.

VOID EnableBTS ( VOID )

Enable branch trace store.

UINTN GetCpuIndex ( VOID )

Get CPU Index from APIC ID.

VOID GetSmiCommandPort ( VOID )

To get system port address of the SMI Command Port in FADT table.

UINT64 GetSourceFromDestinationOnBts | ( | UINTN | CpuIndex,
 |  | UINT64 | DestinationIP
 | ) |  |

Get the source of IP after execute-disable exception is triggered.

Parameters
CpuIndex | The index of CPU.
DestinationIP | The destination address.
VOID GuardPagePFHandler ( UINTN ErrorCode )

Handler for Page Fault triggered by Guard page.

Parameters
ErrorCode The Error code of exception.
VOID InitIdtr ( VOID )

Replace INT1 exception handler to restore page table to absent/execute-disable state in order to trigger page fault again to save SMM profile data..

VOID InitPaging ( VOID )

Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.

VOID InitProtectedMemRange ( VOID )

Initialize the protected memory ranges and the 4KB-page mapped memory ranges.

VOID InitSmmProfile ( UINT32 Cr3 )

Initialize SMM profile in SMM CPU entry point.

Parameters
[in] Cr3 The base address of the page tables to use in SMM.
EFI_STATUS EFIAPI InitSmmProfileCallBack | ( | IN CONST EFI_GUID * | Protocol,
 |  | IN VOID * | Interface,
 |  | IN EFI_HANDLE | Handle
 | ) |  |

Initialize SMM profile in SmmReadyToLock protocol callback function.

Parameters
Protocol | Points to the protocol's unique identifier.
Interface | Points to the interface instance.
Handle | The handle on which the interface was installed.
Return values
EFI_SUCCESS SmmReadyToLock protocol callback runs successfully.
VOID InitSmmProfileInternal ( VOID )

Initialize SMM profile data structures.

BOOLEAN IsAddressSplit ( IN EFI_PHYSICAL_ADDRESS Address )

Check if the memory address will be mapped by 4KB-page.

Parameters
Address The address of Memory.
BOOLEAN IsAddressValid | ( | IN EFI_PHYSICAL_ADDRESS | Address,
 |  | IN BOOLEAN * | Nx
 | ) |  |

Check if the memory address will be mapped by 4KB-page.

Parameters
Address | The address of Memory.
Nx | The flag indicates if the memory is execute-disable.
BOOLEAN IsInSmmRanges ( IN EFI_PHYSICAL_ADDRESS Address )

Check if the input address is in SMM ranges.

Parameters
[in] Address The input address.
Return values
TRUE | The input address is in SMM.
FALSE | The input address is not in SMM.
VOID RestorePageTableBelow4G | ( | UINT64 * | PageTable,
 |  | UINT64 | PFAddress,
 |  | UINTN | CpuIndex,
 |  | UINTN | ErrorCode
 | ) |  |

Update page table to map the memory correctly in order to make the instruction which caused page fault execute successfully. And it also save the original page table to be restored in single-step exception.

Parameters
PageTable | PageTable Address.
PFAddress | The memory address which caused page fault exception.
CpuIndex | The index of the processor.
ErrorCode | The Error code of exception.
VOID SmmProfilePFHandler | ( | UINTN | Rip,
 |  | UINTN | ErrorCode
 | ) |  |

The Page fault handler to save SMM profile data.

Parameters
Rip | The RIP when exception happens.
ErrorCode | The Error code of exception.
VOID SmmProfileRecordSmiNum ( VOID )

Increase SMI number in each SMI entry.

VOID SmmProfileStart ( VOID )

Updates page table to make some memory ranges (like system memory) absent and make some memory ranges (like MMIO) present and execute disable. It also update 2MB-page to 4KB-page for some memory ranges.

Variable Documentation

MEMORY_PROTECTION_RANGE mProtectionMemRangeTemplate[]
Initial value:
= {
{{0x00000000, 0x00000000},TRUE,FALSE},
{{0x00000000, 0x00000000},TRUE,TRUE},
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Functions | Variables
SmmProfile.h File Reference

Functions

VOID | ActivateSmmProfile (IN UINTN CpuIndex)
VOID | InitSmmProfile (UINT32 Cr3)
VOID SmmProfileRecordSmiNum (VOID)
VOID | SmmProfilePFHandler (UINTN Rip, UINTN ErrorCode)
VOID SmmProfileStart (VOID)
VOID EFIAPI | PageFaultIdtHandlerSmmProfile (VOID)
VOID CheckFeatureSupported (VOID)
VOID InitPaging (VOID)
UINTN | GetCpuIndex (VOID)
VOID | GuardPagePFHandler (UINTN ErrorCode)

Variables

BOOLEAN | mXdSupported
BOOLEAN | mXdEnabled
BOOLEAN | mSetupDebugTrap

Detailed Description

SMM profile header file.

Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID ActivateSmmProfile ( IN UINTN CpuIndex )

Initialize processor environment for SMM profile.

Parameters
CpuIndex The index of the processor.
VOID CheckFeatureSupported ( VOID )

Check if XD feature is supported by a processor.

UINTN GetCpuIndex ( VOID )

Get CPU Index from APIC ID.

VOID GuardPagePFHandler ( UINTN ErrorCode )

Handler for Page Fault triggered by Guard page.

Parameters
ErrorCode The Error code of exception.
VOID InitPaging ( VOID )

Update page table according to protected memory ranges and the 4KB-page mapped memory ranges.

VOID InitSmmProfile ( UINT32 Cr3 )

Initialize SMM profile in SMM CPU entry point.

Parameters
[in] Cr3 The base address of the page tables to use in SMM.
VOID EFIAPI PageFaultIdtHandlerSmmProfile ( VOID )

Page fault IDT handler for SMM Profile.

VOID SmmProfilePFHandler | ( | UINTN | Rip,
 |  | UINTN | ErrorCode
 | ) |  |

The Page fault handler to save SMM profile data.

Parameters
Rip | The RIP when exception happens.
ErrorCode | The Error code of exception.
VOID SmmProfileRecordSmiNum ( VOID )

Increase SMI number in each SMI entry.

VOID SmmProfileStart ( VOID )

Updates page table to make some memory ranges (like system memory) absent and make some memory ranges (like MMIO) present and execute disable. It also update 2MB-page to 4KB-page for some memory ranges.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Data Structures | Functions | Variables
SmmProfileInternal.h File Reference

Data Structures

struct | MEMORY_RANGE
struct | MEMORY_PROTECTION_RANGE
struct | SMM_PROFILE_HEADER
struct | SMM_PROFILE_ENTRY

Functions

VOID InitIdtr (VOID)
BOOLEAN | IsAddressSplit (IN EFI_PHYSICAL_ADDRESS Address)
BOOLEAN | IsAddressValid (IN EFI_PHYSICAL_ADDRESS Address, IN BOOLEAN *Nx)
VOID SmiDefaultPFHandler (VOID)
VOID | ClearTrapFlag (IN OUT EFI_SYSTEM_CONTEXT SystemContext)

Variables

SMM_S3_RESUME_STATE * | mSmmS3ResumeState
UINTN | gSmiExceptionHandlers []
BOOLEAN | mXdSupported
X86_ASSEMBLY_PATCH_LABEL | gPatchXdSupported
UINTN * | mPFEntryCount
UINT64(* | mLastPFEntryValue )[MAX_PF_ENTRY_COUNT]
UINT64 *(* | mLastPFEntryPointer )[MAX_PF_ENTRY_COUNT]

Detailed Description

SMM profile internal header file.

Copyright (c) 2012 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID ClearTrapFlag ( IN OUT EFI_SYSTEM_CONTEXT SystemContext )

Clear TF in FLAGS.

Parameters
SystemContext A pointer to the processor context when the interrupt occurred on the processor.
VOID InitIdtr ( VOID )

Update IDT table to replace page fault handler and INT 1 handler.

Replace INT1 exception handler to restore page table to absent/execute-disable state in order to trigger page fault again to save SMM profile data..

BOOLEAN IsAddressSplit ( IN EFI_PHYSICAL_ADDRESS Address )

Check if the memory address will be mapped by 4KB-page.

Parameters
Address The address of Memory.
BOOLEAN IsAddressValid | ( | IN EFI_PHYSICAL_ADDRESS | Address,
 |  | IN BOOLEAN * | Nx
 | ) |  |

Check if the memory address will be mapped by 4KB-page.

Parameters
Address | The address of Memory.
Nx | The flag indicates if the memory is execute-disable.
VOID SmiDefaultPFHandler ( VOID )

Page Fault handler for SMM use.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/SmramSaveState.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Data Structures | Functions | Variables
SmramSaveState.c File Reference

Data Structures

struct | PROCESSOR_SMM_DESCRIPTOR
struct | CPU_SMM_SAVE_STATE_REGISTER_RANGE
struct | CPU_SMM_SAVE_STATE_LOOKUP_ENTRY
struct | CPU_SMM_SAVE_STATE_IO_WIDTH

Functions

BOOLEAN | NeedSysCall (VOID)
UINT64 EFIAPI | SysCall (UINTN CallIndex, UINTN Arg1, UINTN Arg2, UINTN Arg3)
UINTN | GetRegisterIndex (IN EFI_SMM_SAVE_STATE_REGISTER Register)
EFI_STATUS | ReadSaveStateRegisterByIndex (IN UINTN CpuIndex, IN UINTN RegisterIndex, IN UINTN Width, OUT VOID *Buffer)
EFI_STATUS EFIAPI | ReadSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, OUT VOID *Buffer)
EFI_STATUS EFIAPI | WriteSaveStateRegister (IN UINTN CpuIndex, IN EFI_SMM_SAVE_STATE_REGISTER Register, IN UINTN Width, IN CONST VOID *Buffer)
UINT64 EFIAPI | HookReturnFromSmm (IN UINTN CpuIndex, SMRAM_SAVE_STATE_MAP *CpuState, UINT64 NewInstructionPointer32, UINT64 NewInstructionPointer)
UINTN EFIAPI | GetSmiHandlerSize (VOID)
VOID EFIAPI | InstallSmiHandler (IN UINTN CpuIndex, IN UINT32 SmBase, IN VOID *SmiStack, IN UINTN StackSize, IN UINTN GdtBase, IN UINTN GdtSize, IN UINTN IdtBase, IN UINTN IdtSize, IN UINT32 Cr3)

Variables

CONST PROCESSOR_SMM_DESCRIPTOR | gcPsd
BOOLEAN | mPcdSmmIsolationSupport
X86_ASSEMBLY_PATCH_LABEL | gPatchSmbase
X86_ASSEMBLY_PATCH_LABEL | gPatchSmiStack
X86_ASSEMBLY_PATCH_LABEL | gPatchSmiCr3
volatile UINT8 | gcSmiHandlerTemplate []
CONST UINT16 | gcSmiHandlerSize
UINT8 | SmiRendezvousEntry
IA32_DESCRIPTOR | gSmiHandlerIdtr
CONST
CPU_SMM_SAVE_STATE_REGISTER_RANGE 		mSmmCpuRegisterRanges []
CONST
CPU_SMM_SAVE_STATE_LOOKUP_ENTRY 		mSmmCpuWidthOffset []
CONST CPU_SMM_SAVE_STATE_IO_WIDTH | mSmmCpuIoWidth []
CONST EFI_SMM_SAVE_STATE_IO_TYPE | mSmmCpuIoType []
UINT8 | mSmmSaveStateRegisterLma

Detailed Description

Provides services to access SMRAM Save State Map

Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

UINTN GetRegisterIndex ( IN EFI_SMM_SAVE_STATE_REGISTER Register )

Read information from the CPU save state.

Parameters
Register Specifies the CPU register to read form the save state.
Return values
0 | Register is not valid
>0 | Index into mSmmCpuWidthOffset[] associated with Register
UINTN EFIAPI GetSmiHandlerSize ( VOID )

Get the size of the SMI Handler in bytes.

Return values
The size, in bytes, of the SMI Handler.
UINT64 EFIAPI HookReturnFromSmm | ( | IN UINTN | CpuIndex,
 |  | SMRAM_SAVE_STATE_MAP * | CpuState,
 |  | UINT64 | NewInstructionPointer32,
 |  | UINT64 | NewInstructionPointer
 | ) |  |

Hook the code executed immediately after an RSM instruction on the currently executing CPU. The mode of code executed immediately after RSM must be detected, and the appropriate hook must be selected. Always clear the auto HALT restart flag if it is set.

Parameters
[in] | CpuIndex | The processor index for the currently executing CPU.
[in] | CpuState | Pointer to SMRAM Save State Map for the currently executing CPU.
[in] | NewInstructionPointer32 | Instruction pointer to use if resuming to 32-bit mode from 64-bit SMM.
[in] | NewInstructionPointer | Instruction pointer to use if resuming to same mode as SMM.
Return values
The value of the original instruction pointer before it was hooked.
VOID EFIAPI InstallSmiHandler | ( | IN UINTN | CpuIndex,
 |  | IN UINT32 | SmBase,
 |  | IN VOID * | SmiStack,
 |  | IN UINTN | StackSize,
 |  | IN UINTN | GdtBase,
 |  | IN UINTN | GdtSize,
 |  | IN UINTN | IdtBase,
 |  | IN UINTN | IdtSize,
 |  | IN UINT32 | Cr3
 | ) |  |

Install the SMI handler for the CPU specified by CpuIndex. This function is called by the CPU that was elected as monarch during System Management Mode initialization.

Parameters
[in] | CpuIndex | The index of the CPU to install the custom SMI handler. The value must be between 0 and the NumberOfCpus field in the System Management System Table (SMST).
[in] | SmBase | The SMBASE address for the CPU specified by CpuIndex.
[in] | SmiStack | The stack to use when an SMI is processed by the the CPU specified by CpuIndex.
[in] | StackSize | The size, in bytes, if the stack used when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtBase | The base address of the GDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | GdtSize | The size, in bytes, of the GDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtBase | The base address of the IDT to use when an SMI is processed by the CPU specified by CpuIndex.
[in] | IdtSize | The size, in bytes, of the IDT used when an SMI is processed by the CPU specified by CpuIndex.
[in] | Cr3 | The base address of the page tables to use when an SMI is processed by the CPU specified by CpuIndex.
EFI_STATUS EFIAPI ReadSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | OUT VOID * | Buffer
 | ) |  |

Read a CPU Save State register on the target processor.

This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map.

This function supports reading a CPU Save State register in SMBase relocation handler.

Parameters
[in] | CpuIndex | Specifies the zero-based index of the CPU save state.
[in] | RegisterIndex | Index into mSmmCpuWidthOffset[] look up table.
[in] | Width | The number of bytes to read from the CPU save state.
[out] | Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State.
EFI_NOT_FOUND | The register is not defined for the Save State of Processor.
EFI_INVALID_PARAMTER | This or Buffer is NULL.
EFI_STATUS ReadSaveStateRegisterByIndex | ( | IN UINTN | CpuIndex,
 |  | IN UINTN | RegisterIndex,
 |  | IN UINTN | Width,
 |  | OUT VOID * | Buffer
 | ) |  |

Read a CPU Save State register on the target processor.

This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map.

This function supports reading a CPU Save State register in SMBase relocation handler.

Parameters
[in] | CpuIndex | Specifies the zero-based index of the CPU save state.
[in] | RegisterIndex | Index into mSmmCpuWidthOffset[] look up table.
[in] | Width | The number of bytes to read from the CPU save state.
[out] | Buffer | Upon return, this holds the CPU register value read from the save state.
Return values
EFI_SUCCESS | The register was read from Save State.
EFI_NOT_FOUND | The register is not defined for the Save State of Processor.
EFI_INVALID_PARAMTER | This or Buffer is NULL.
EFI_STATUS EFIAPI WriteSaveStateRegister | ( | IN UINTN | CpuIndex,
 |  | IN EFI_SMM_SAVE_STATE_REGISTER | Register,
 |  | IN UINTN | Width,
 |  | IN CONST VOID * | Buffer
 | ) |  |

Write value to a CPU Save State register on the target processor.

This function abstracts the differences that whether the CPU Save State register is in the IA32 CPU Save State Map or X64 CPU Save State Map.

This function supports writing a CPU Save State register in SMBase relocation handler.

Parameters
[in] | CpuIndex | Specifies the zero-based index of the CPU save state.
[in] | RegisterIndex | Index into mSmmCpuWidthOffset[] look up table.
[in] | Width | The number of bytes to read from the CPU save state.
[in] | Buffer | Upon entry, this holds the new CPU register value.
Return values
EFI_SUCCESS | The register was written to Save State.
EFI_NOT_FOUND | The register is not defined for the Save State of Processor.
EFI_INVALID_PARAMTER | ProcessorIndex or Width is not correct.

Variable Documentation

X86_ASSEMBLY_PATCH_LABEL gPatchSmbase

Variables from SMI Handler

CONST EFI_SMM_SAVE_STATE_IO_TYPE mSmmCpuIoType[]
Initial value:
= {
EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT,
EFI_SMM_SAVE_STATE_IO_TYPE_INPUT,
EFI_SMM_SAVE_STATE_IO_TYPE_STRING,
EFI_SMM_SAVE_STATE_IO_TYPE_STRING,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX,
EFI_SMM_SAVE_STATE_IO_TYPE_REP_PREFIX,
EFI_SMM_SAVE_STATE_IO_TYPE_OUTPUT,
EFI_SMM_SAVE_STATE_IO_TYPE_INPUT,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
(EFI_SMM_SAVE_STATE_IO_TYPE)0,
(EFI_SMM_SAVE_STATE_IO_TYPE)0
}

Lookup table for the IOMisc type information

CONST CPU_SMM_SAVE_STATE_IO_WIDTH mSmmCpuIoWidth[]
Initial value:
= {
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 },
{ 1, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 },
{ 2, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT16 },
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 },
{ 4, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT32 },
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 },
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 },
{ 0, EFI_SMM_SAVE_STATE_IO_WIDTH_UINT8 }
}

Lookup table for the IOMisc width information

CONST CPU_SMM_SAVE_STATE_REGISTER_RANGE mSmmCpuRegisterRanges[]
Initial value:
= {
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_GDTBASE, EFI_SMM_SAVE_STATE_REGISTER_LDTINFO),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_ES, EFI_SMM_SAVE_STATE_REGISTER_RIP),
SMM_REGISTER_RANGE (EFI_SMM_SAVE_STATE_REGISTER_RFLAGS, EFI_SMM_SAVE_STATE_REGISTER_CR4),
{ (EFI_SMM_SAVE_STATE_REGISTER)0, (EFI_SMM_SAVE_STATE_REGISTER)0, 0 }
}

Table used by GetRegisterIndex() to convert an EFI_SMM_SAVE_STATE_REGISTER value to an index into a table of type CPU_SMM_SAVE_STATE_LOOKUP_ENTRY

CONST CPU_SMM_SAVE_STATE_LOOKUP_ENTRY mSmmCpuWidthOffset[]

Lookup table used to retrieve the widths and offsets associated with each supported EFI_SMM_SAVE_STATE_REGISTER value

UINT8 mSmmSaveStateRegisterLma

The mode of the CPU at the time an SMI occurs

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/PiSmmCpuDxeSmm/SyncTimer.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • PiSmmCpuDxeSmm
Functions | Variables
SyncTimer.c File Reference

Functions

VOID InitializeSmmTimer (VOID)
UINT64 EFIAPI | StartSyncTimer (VOID)
BOOLEAN EFIAPI | IsSyncTimerTimeout (IN UINT64 Timer)

Variables

UINT64 | mTimeoutTicker = 0
UINT64 | mCycle = 0
BOOLEAN | mCountDown

Detailed Description

SMM Timer feature support

Copyright (c) 2009 - 2015, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID InitializeSmmTimer ( VOID )

Initialize Timer for SMM AP Sync.

BOOLEAN EFIAPI IsSyncTimerTimeout ( IN UINT64 Timer )

Check if the SMM AP Sync timer is timeout.

Parameters
Timer The start timer from the begin.
UINT64 EFIAPI StartSyncTimer ( VOID )

Start Timer for SMM AP Sync.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector Directory Reference

  • UefiCpuPkg
  • ResetVector
ResetVector Directory Reference

Directories

directory | FixupVtf
directory | Vtf0
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/FixupVtf Directory Reference

  • UefiCpuPkg
  • ResetVector
  • FixupVtf
FixupVtf Directory Reference

Files

file | ResetVector.uni
file | ResetVectorExtra.uni
file | Vtf.inf
file | Vtf.nasmb
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/FixupVtf/ResetVector.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • FixupVtf
ResetVector.uni File Reference

Detailed Description

Reset Vector

This VTF requires build time fixups in order to find the SEC entry point.

Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/FixupVtf/ResetVectorExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • FixupVtf
ResetVectorExtra.uni File Reference

Detailed Description

ResetVector Localized Strings and Content

Copyright (c) 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0 Directory Reference

  • UefiCpuPkg
  • ResetVector
  • Vtf0
Vtf0 Directory Reference

Directories

directory | Bin
directory | Ia16
directory | Ia32
directory | Tools
directory | X64

Files

file | Build.py
Automate the process of building the various reset vector types.
file | CommonMacros.inc
file | DebugDisabled.asm
file | Main.asm
file | Port80Debug.asm
file | PostCodes.inc
file | ResetVector.uni
file | ResetVectorExtra.uni
file | SerialDebug.asm
file | Vtf0.inf
file | Vtf0.nasmb
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Bin Directory Reference

  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Bin
Bin Directory Reference

Files

file | ResetVector.ia32.port80.raw
file | ResetVector.ia32.raw
file | ResetVector.ia32.serial.raw
file | ResetVector.inf
file | ResetVector.uni
file | ResetVector.x64.port80.raw
file | ResetVector.x64.raw
file | ResetVector.x64.serial.raw
file | ResetVectorExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Bin
ResetVector.uni File Reference

Detailed Description

Reset Vector binary

Reset Vector binary

Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVectorExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Bin
ResetVectorExtra.uni File Reference

Detailed Description

ResetVector Localized Strings and Content

Copyright (c) 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Tools Directory Reference

  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Tools
Tools Directory Reference

Files

file FixupForRawSection.py
Apply fixup to VTF binary image for FFS Raw section.
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Tools
Variables
FixupForRawSection.py File Reference

Apply fixup to VTF binary image for FFS Raw section. More...

Variables

list | FixupForRawSection.filename = sys.argv[1]
tuple | FixupForRawSection.d = open(sys.argv[1], 'rb')
tuple | FixupForRawSection.c = ((len(d) + 4 + 7) & ~7)
tuple | FixupForRawSection.f = open(sys.argv[1], 'wb')

Detailed Description

Apply fixup to VTF binary image for FFS Raw section.

Copyright (c) 2008, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Build.py File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • Vtf0
Functions | Variables
Build.py File Reference

Automate the process of building the various reset vector types. More...

Functions

def Build.RunCommand

Variables

tuple | Build.output = os.path.join('Bin', 'ResetVector')
tuple | Build.commandLine
tuple | Build.ret = RunCommand(commandLine)

Detailed Description

Automate the process of building the various reset vector types.

Copyright (c) 2009, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/ResetVector.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • Vtf0
ResetVector.uni File Reference

Detailed Description

Reset Vector

Reset Vector

Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/ResetVectorExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • ResetVector
  • Vtf0
ResetVectorExtra.uni File Reference

Detailed Description

ResetVector Localized Strings and Content

Copyright (c) 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore Directory Reference

  • UefiCpuPkg
  • SecCore
SecCore Directory Reference

Directories

directory Ia32

Files

file | FindPeiCore.c
file | SecBist.c
file | SecCore.inf
file | SecCore.uni
file | SecCoreExtra.uni
file | SecMain.c
file | SecMain.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore/FindPeiCore.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • SecCore
Functions
FindPeiCore.c File Reference

Functions

EFI_STATUS EFIAPI | FindImageBase (IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr, OUT EFI_PHYSICAL_ADDRESS *SecCoreImageBase, OUT EFI_PHYSICAL_ADDRESS *PeiCoreImageBase)
VOID EFIAPI | FindAndReportEntryPoints (IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr, OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint)

Detailed Description

Locate the entry point for the PEI Core

Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI FindAndReportEntryPoints | ( | IN EFI_FIRMWARE_VOLUME_HEADER * | BootFirmwareVolumePtr,
 |  | OUT EFI_PEI_CORE_ENTRY_POINT * | PeiCoreEntryPoint
 | ) |  |

Find and return Pei Core entry point.

It also find SEC and PEI Core file debug information. It will report them if remote debug is enabled.

Parameters
BootFirmwareVolumePtr | Point to the boot firmware volume.
PeiCoreEntryPoint | The entry point of the PEI core.
EFI_STATUS EFIAPI FindImageBase | ( | IN EFI_FIRMWARE_VOLUME_HEADER * | BootFirmwareVolumePtr,
 |  | OUT EFI_PHYSICAL_ADDRESS * | SecCoreImageBase,
 |  | OUT EFI_PHYSICAL_ADDRESS * | PeiCoreImageBase
 | ) |  |

Find core image base.

Parameters
BootFirmwareVolumePtr | Point to the boot firmware volume.
SecCoreImageBase | The base address of the SEC core image.
PeiCoreImageBase | The base address of the PEI core image.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore/SecBist.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • SecCore
Functions | Variables
SecBist.c File Reference

Functions

EFI_STATUS | GetBistFromHob (IN OUT UINT64 *StructureSize, IN OUT VOID *StructureBuffer)
EFI_STATUS EFIAPI | SecPlatformInformationBist (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
EFI_STATUS EFIAPI | SecPlatformInformation2Bist (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2)
EFI_STATUS | GetBistInfoFromPpi (IN CONST EFI_PEI_SERVICES **PeiServices, IN CONST EFI_GUID *Guid, OUT EFI_PEI_PPI_DESCRIPTOR **PpiDescriptor, OUT VOID **BistInformationData, OUT UINT64 *BistInformationSize OPTIONAL)
VOID RepublishSecPlatformInformationPpi (VOID)

Variables

EFI_SEC_PLATFORM_INFORMATION_PPI | mSecPlatformInformation
EFI_PEI_PPI_DESCRIPTOR | mPeiSecPlatformInformation
EFI_SEC_PLATFORM_INFORMATION2_PPI | mSecPlatformInformation2
EFI_PEI_PPI_DESCRIPTOR | mPeiSecPlatformInformation2

Detailed Description

Get SEC platform information(2) PPI and reinstall it.

Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS GetBistFromHob | ( | IN OUT UINT64 * | StructureSize,
 |  | IN OUT VOID * | StructureBuffer
 | ) |  |

Worker function to parse CPU BIST information from Guided HOB.

Parameters
[in,out] | StructureSize | Pointer to the variable describing size of the input buffer.
[in,out] | StructureBuffer | Pointer to the buffer save CPU BIST information.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.
EFI_STATUS GetBistInfoFromPpi | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN CONST EFI_GUID * | Guid,
 |  | OUT EFI_PEI_PPI_DESCRIPTOR ** | PpiDescriptor,
 |  | OUT VOID ** | BistInformationData,
 |  | OUT UINT64 *BistInformationSize | OPTIONAL
 | ) |  |

Worker function to get CPUs' BIST by calling SecPlatformInformationPpi or SecPlatformInformation2Ppi.

Parameters
[in] | PeiServices | Pointer to PEI Services Table
[in] | Guid | PPI Guid
[out] | PpiDescriptor | Return a pointer to instance of the EFI_PEI_PPI_DESCRIPTOR
[out] | BistInformationData | Pointer to BIST information data
[out] | BistInformationSize | Return the size in bytes of BIST information
Return values
EFI_SUCCESS | Retrieve of the BIST data successfully
EFI_NOT_FOUND | No sec platform information(2) ppi export
EFI_DEVICE_ERROR | Failed to get CPU Information
VOID RepublishSecPlatformInformationPpi ( VOID )

Get CPUs' BIST by calling SecPlatformInformationPpi/SecPlatformInformation2Ppi.

EFI_STATUS EFIAPI SecPlatformInformation2Bist | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 * | PlatformInformationRecord2
 | ) |  |

Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.

Parameters
[in] | PeiServices | The pointer to the PEI Services Table.
[in,out] | StructureSize | The pointer to the variable describing size of the input buffer.
[out] | PlatformInformationRecord2 | The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small. The current buffer size needed to hold the record is returned in StructureSize.
EFI_STATUS EFIAPI SecPlatformInformationBist | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD * | PlatformInformationRecord
 | ) |  |

Implementation of the PlatformInformation service in EFI_SEC_PLATFORM_INFORMATION_PPI.

Parameters
[in] | PeiServices | Pointer to the PEI Services Table.
[in,out] | StructureSize | Pointer to the variable describing size of the input buffer.
[out] | PlatformInformationRecord | Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.

Variable Documentation

EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiSecPlatformInformationPpiGuid,
&mSecPlatformInformation
}
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformation2
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiSecPlatformInformation2PpiGuid,
&mSecPlatformInformation2
}
EFI_SEC_PLATFORM_INFORMATION_PPI mSecPlatformInformation
Initial value:
= {
SecPlatformInformationBist
}
SecPlatformInformationBist
EFI_STATUS EFIAPI SecPlatformInformationBist(IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
Definition: SecBist.c:92
EFI_SEC_PLATFORM_INFORMATION2_PPI mSecPlatformInformation2
Initial value:
= {
SecPlatformInformation2Bist
}
SecPlatformInformation2Bist
EFI_STATUS EFIAPI SecPlatformInformation2Bist(IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2)
Definition: SecBist.c:115
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore/SecCore.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • SecCore
SecCore.uni File Reference

Detailed Description

SecCore module that implements the SEC phase.

This is the first module taking control of the platform upon power-on/reset. It implements the first phase of the security phase. The entry point function is _ModuleEntryPoint in PlatformSecLib. The entry point function will switch to protected mode, setup flat memory model, enable temporary memory and call into SecStartup().

Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore/SecCoreExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • SecCore
SecCoreExtra.uni File Reference

Detailed Description

SecCore Localized Strings and Content

Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore/SecMain.c File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • SecCore
Functions | Variables
SecMain.c File Reference

Functions

VOID NORETURN EFIAPI | SecStartupPhase2 (IN VOID *Context)
EFI_STATUS EFIAPI | SecPerformancePpiCallBack (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
VOID NORETURN EFIAPI | SecStartup (IN UINT32 SizeOfRam, IN UINT32 TempRamBase, IN VOID *BootFirmwareVolume)
EFI_STATUS EFIAPI | SecTemporaryRamDone (VOID)

Variables

EFI_PEI_TEMPORARY_RAM_DONE_PPI | gSecTemporaryRamDonePpi
EFI_SEC_PLATFORM_INFORMATION_PPI | mSecPlatformInformationPpi = { SecPlatformInformation }
EFI_PEI_PPI_DESCRIPTOR | mPeiSecPlatformInformationPpi []
UINT64 | mIdtEntryTemplate = 0xffff8e000010ffe4ULL

Detailed Description

C functions in SEC

Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

EFI_STATUS EFIAPI SecPerformancePpiCallBack | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Entry point of the notification callback function itself within the PEIM. It is to get SEC performance data and build HOB to convey the SEC performance data to DXE phase.

Parameters
PeiServices | Indirect reference to the PEI Services Table.
NotifyDescriptor | Address of the notification descriptor data structure.
Ppi | Address of the PPI that was installed.
Returns
Status of the notification. The status code returned from this function is ignored.
VOID NORETURN EFIAPI SecStartup | ( | IN UINT32 | SizeOfRam,
 |  | IN UINT32 | TempRamBase,
 |  | IN VOID * | BootFirmwareVolume
 | ) |  |

Entry point to the C language phase of SEC. After the SEC assembly code has initialized some temporary memory and set up the stack, the control is transferred to this function.

Parameters
SizeOfRam | Size of the temporary memory available for use.
TempRamBase | Base address of temporary ram
BootFirmwareVolume | Base address of the Boot Firmware Volume.
VOID NORETURN EFIAPI SecStartupPhase2 ( IN VOID * Context )

Caller provided function to be invoked at the end of InitializeDebugAgent().

Entry point to the C language phase of SEC. After the SEC assembly code has initialized some temporary memory and set up the stack, the control is transferred to this function.

Parameters
[in] Context The first input parameter of InitializeDebugAgent().
EFI_STATUS EFIAPI SecTemporaryRamDone ( VOID )

TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.

Return values
EFI_SUCCESS | Use of Temporary RAM was disabled.
EFI_INVALID_PARAMETER | Temporary RAM could not be disabled.

Variable Documentation

EFI_PEI_TEMPORARY_RAM_DONE_PPI gSecTemporaryRamDonePpi
Initial value:
= {
SecTemporaryRamDone
}
SecTemporaryRamDone
EFI_STATUS EFIAPI SecTemporaryRamDone(VOID)
Definition: SecMain.c:336
EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[]
Initial value:
= {
{
EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
&gPeiSecPerformancePpiGuid,
(VOID *) (UINTN) SecPerformancePpiCallBack
},
{
EFI_PEI_PPI_DESCRIPTOR_PPI,
&gEfiTemporaryRamDonePpiGuid,
&gSecTemporaryRamDonePpi
},
{
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiSecPlatformInformationPpiGuid,
&mSecPlatformInformationPpi
}
}
VOID
typedef VOID(EFIAPI *ASM_RELOCATE_AP_LOOP)(IN BOOLEAN MwaitSupport
SecPerformancePpiCallBack
EFI_STATUS EFIAPI SecPerformancePpiCallBack(IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)
Definition: SecMain.c:80
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/SecCore/SecMain.h File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • SecCore
Data Structures | Typedefs | Functions
SecMain.h File Reference

Data Structures

struct _SEC_IDT_TABLE

Typedefs

typedef struct _SEC_IDT_TABLE SEC_IDT_TABLE

Functions

EFI_STATUS EFIAPI | SecTemporaryRamDone (VOID)
VOID NORETURN EFIAPI | SecStartup (IN UINT32 SizeOfRam, IN UINT32 TempRamBase, IN VOID *BootFirmwareVolume)
VOID EFIAPI | FindAndReportEntryPoints (IN EFI_FIRMWARE_VOLUME_HEADER *BootFirmwareVolumePtr, OUT EFI_PEI_CORE_ENTRY_POINT *PeiCoreEntryPoint)
VOID EFIAPI | ProcessLibraryConstructorList (VOID)
EFI_STATUS EFIAPI | SecPlatformInformationBist (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord)
EFI_STATUS EFIAPI | SecPlatformInformation2Bist (IN CONST EFI_PEI_SERVICES **PeiServices, IN OUT UINT64 *StructureSize, OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2)
VOID RepublishSecPlatformInformationPpi (VOID)
EFI_STATUS EFIAPI | SecPerformancePpiCallBack (IN EFI_PEI_SERVICES **PeiServices, IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, IN VOID *Ppi)

Detailed Description

Master header file for SecCore.

Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI FindAndReportEntryPoints | ( | IN EFI_FIRMWARE_VOLUME_HEADER * | BootFirmwareVolumePtr,
 |  | OUT EFI_PEI_CORE_ENTRY_POINT * | PeiCoreEntryPoint
 | ) |  |

Find and return Pei Core entry point.

It also find SEC and PEI Core file debug information. It will report them if remote debug is enabled.

Parameters
BootFirmwareVolumePtr | Point to the boot firmware volume.
PeiCoreEntryPoint | Point to the PEI core entry point.

Find and return Pei Core entry point.

It also find SEC and PEI Core file debug information. It will report them if remote debug is enabled.

Parameters
BootFirmwareVolumePtr | Point to the boot firmware volume.
PeiCoreEntryPoint | The entry point of the PEI core.
VOID EFIAPI ProcessLibraryConstructorList ( VOID )

Auto-generated function that calls the library constructors for all of the module's dependent libraries. This function must be called by the SEC Core once a stack has been established.

VOID RepublishSecPlatformInformationPpi ( VOID )

Republish SecPlatformInformationPpi/SecPlatformInformation2Ppi.

Get CPUs' BIST by calling SecPlatformInformationPpi/SecPlatformInformation2Ppi.

EFI_STATUS EFIAPI SecPerformancePpiCallBack | ( | IN EFI_PEI_SERVICES ** | PeiServices,
 |  | IN EFI_PEI_NOTIFY_DESCRIPTOR * | NotifyDescriptor,
 |  | IN VOID * | Ppi
 | ) |  |

Entry point of the notification callback function itself within the PEIM. It is to get SEC performance data and build HOB to convey the SEC performance data to DXE phase.

Parameters
PeiServices | Indirect reference to the PEI Services Table.
NotifyDescriptor | Address of the notification descriptor data structure.
Ppi | Address of the PPI that was installed.
Returns
Status of the notification. The status code returned from this function is ignored.
EFI_STATUS EFIAPI SecPlatformInformation2Bist | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 * | PlatformInformationRecord2
 | ) |  |

Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.

Parameters
PeiServices | The pointer to the PEI Services Table.
StructureSize | The pointer to the variable describing size of the input buffer.
PlatformInformationRecord2 | The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small. The current buffer size needed to hold the record is returned in StructureSize.

Implementation of the PlatformInformation2 service in EFI_SEC_PLATFORM_INFORMATION2_PPI.

Parameters
[in] | PeiServices | The pointer to the PEI Services Table.
[in,out] | StructureSize | The pointer to the variable describing size of the input buffer.
[out] | PlatformInformationRecord2 | The pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD2.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small. The current buffer size needed to hold the record is returned in StructureSize.
EFI_STATUS EFIAPI SecPlatformInformationBist | ( | IN CONST EFI_PEI_SERVICES ** | PeiServices,
 |  | IN OUT UINT64 * | StructureSize,
 |  | OUT EFI_SEC_PLATFORM_INFORMATION_RECORD * | PlatformInformationRecord
 | ) |  |

Implementation of the PlatformInformation service in EFI_SEC_PLATFORM_INFORMATION_PPI.

Parameters
PeiServices | Pointer to the PEI Services Table.
StructureSize | Pointer to the variable describing size of the input buffer.
PlatformInformationRecord | Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.

Implementation of the PlatformInformation service in EFI_SEC_PLATFORM_INFORMATION_PPI.

Parameters
[in] | PeiServices | Pointer to the PEI Services Table.
[in,out] | StructureSize | Pointer to the variable describing size of the input buffer.
[out] | PlatformInformationRecord | Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
Return values
EFI_SUCCESS | The data was successfully returned.
EFI_BUFFER_TOO_SMALL | The buffer was too small.
VOID NORETURN EFIAPI SecStartup | ( | IN UINT32 | SizeOfRam,
 |  | IN UINT32 | TempRamBase,
 |  | IN VOID * | BootFirmwareVolume
 | ) |  |

Entry point to the C language phase of SEC. After the SEC assembly code has initialized some temporary memory and set up the stack, the control is transferred to this function.

Parameters
SizeOfRam | Size of the temporary memory available for use.
TempRamBase | Base address of temporary ram
BootFirmwareVolume | Base address of the Boot Firmware Volume.
EFI_STATUS EFIAPI SecTemporaryRamDone ( VOID )

TemporaryRamDone() disables the use of Temporary RAM. If present, this service is invoked by the PEI Foundation after the EFI_PEI_PERMANANT_MEMORY_INSTALLED_PPI is installed.

Return values
EFI_SUCCESS | Use of Temporary RAM was disabled.
EFI_INVALID_PARAMETER | Temporary RAM could not be disabled.
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal Directory Reference

  • UefiCpuPkg
  • Universal
Universal Directory Reference

Directories

directory Acpi
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi Directory Reference

  • UefiCpuPkg
  • Universal
  • Acpi
Acpi Directory Reference

Directories

directory S3Resume2Pei
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi/S3Resume2Pei Directory Reference

  • UefiCpuPkg
  • Universal
  • Acpi
  • S3Resume2Pei
S3Resume2Pei Directory Reference

Directories

directory | Ia32
directory | X64

Files

file | S3Resume.c
file | S3Resume.sdl
file | S3Resume2Pei.inf
file | S3Resume2Pei.uni
file | S3Resume2PeiExtra.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c File Reference

  • File List
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  • UefiCpuPkg
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  • S3Resume2Pei
Data Structures | Typedefs | Functions | Variables
S3Resume.c File Reference

Data Structures

struct | _ACPI_RESET_STRUCTURE
union | IA32_GDT
union | PAGE_MAP_AND_DIRECTORY_POINTER
union | PAGE_TABLE_ENTRY
union | PAGE_TABLE_1G_ENTRY
struct | SMM_COMMUNICATE_HEADER_32
struct | SMM_COMMUNICATE_HEADER_64

Typedefs

typedef struct
_ACPI_RESET_STRUCTURE 		ACPI_RESET_STRUCTURE
typedef IN UINT32 AcpiLowMemoryBase

Functions

typedef | VOID (EFIAPI *ASM_TRANSFER_CONTROL)(IN UINT32 S3WakingVector
EFI_STATUS EFIAPI | S3RestoreConfig2 (IN EFI_PEI_S3_RESUME2_PPI *This)
VOID EFIAPI | AsmSetDataSelectors (IN UINT16 SelectorValue)
BOOLEAN | IsLongModeWakingVector (IN ACPI_S3_CONTEXT *AcpiS3Context)
VOID | SignalToSmmByCommunication (IN EFI_GUID *HandlerType)
VOID EFIAPI | S3ResumeBootOs (IN ACPI_S3_CONTEXT *AcpiS3Context, IN PEI_S3_RESUME_STATE *PeiS3ResumeState)
VOID | RestoreS3PageTables (IN UINTN S3NvsPageTableAddress, IN BOOLEAN Build4GPageTableOnly)
VOID EFIAPI | S3ResumeExecuteBootScript (IN ACPI_S3_CONTEXT *AcpiS3Context, IN BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable)
EFI_STATUS EFIAPI | PeimS3ResumeEntryPoint (IN EFI_PEI_FILE_HANDLE FileHandle, IN CONST EFI_PEI_SERVICES **PeiServices)

Variables

EFI_PEI_S3_RESUME2_PPI | mS3ResumePpi = { S3RestoreConfig2 }
EFI_PEI_PPI_DESCRIPTOR | mPpiList
EFI_PEI_PPI_DESCRIPTOR | mPpiListPostScriptTable
EFI_PEI_PPI_DESCRIPTOR | mPpiListEndOfPeiTable
EFI_PEI_PPI_DESCRIPTOR | mPpiListS3SmmInitDoneTable
GLOBAL_REMOVE_IF_UNREFERENCED
IA32_GDT 		mGdtEntries []
GLOBAL_REMOVE_IF_UNREFERENCED
CONST IA32_DESCRIPTOR 		mGdt

Detailed Description

This module produces the EFI_PEI_S3_RESUME2_PPI. This module works with StandAloneBootScriptExecutor to S3 resume to OS. This module will execute the boot script saved during last boot and after that, control is passed to OS waking up handler.

Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
Copyright (c) 2017, AMD Incorporated. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Function Documentation

VOID EFIAPI AsmSetDataSelectors ( IN UINT16 SelectorValue )

Set data segment selectors value including DS/ES/FS/GS/SS.

Parameters
[in] SelectorValue Segment selector value to be set.
BOOLEAN IsLongModeWakingVector ( IN ACPI_S3_CONTEXT * AcpiS3Context )

The function will check if current waking vector is long mode.

Parameters
AcpiS3Context a pointer to a structure of ACPI_S3_CONTEXT
Return values
TRUE | Current context need long mode waking vector.
FALSE | Current context need not long mode waking vector.
EFI_STATUS EFIAPI PeimS3ResumeEntryPoint | ( | IN EFI_PEI_FILE_HANDLE | FileHandle,
 |  | IN CONST EFI_PEI_SERVICES ** | PeiServices
 | ) |  |

Main entry for S3 Resume PEIM.

This routine is to install EFI_PEI_S3_RESUME2_PPI.

Parameters
FileHandle | Handle of the file being invoked.
PeiServices | Pointer to PEI Services table.
Return values
EFI_SUCCESS S3Resume Ppi is installed successfully.
VOID RestoreS3PageTables | ( | IN UINTN | S3NvsPageTableAddress,
 |  | IN BOOLEAN | Build4GPageTableOnly
 | ) |  |

Restore S3 page table because we do not trust ACPINvs content. If BootScriptExector driver will not run in 64-bit mode, this function will do nothing.

Parameters
S3NvsPageTableAddress | PageTableAddress in ACPINvs
Build4GPageTableOnly | If BIOS just build 4G page table only
EFI_STATUS EFIAPI S3RestoreConfig2 ( IN EFI_PEI_S3_RESUME2_PPI * This )

Restores the platform to its preboot configuration for an S3 resume and jumps to the OS waking vector.

This function will restore the platform to its pre-boot configuration that was pre-stored in the boot script table and transfer control to OS waking vector. Upon invocation, this function is responsible for locating the following information before jumping to OS waking vector:

  • ACPI tables
  • boot script table
  • any other information that it needs

The S3RestoreConfig() function then executes the pre-stored boot script table and transitions the platform to the pre-boot state. The boot script is recorded during regular boot using the EFI_S3_SAVE_STATE_PROTOCOL.Write() and EFI_S3_SMM_SAVE_STATE_PROTOCOL.Write() functions. Finally, this function transfers control to the OS waking vector. If the OS supports only a real-mode waking vector, this function will switch from flat mode to real mode before jumping to the waking vector. If all platform pre-boot configurations are successfully restored and all other necessary information is ready, this function will never return and instead will directly jump to the OS waking vector. If this function returns, it indicates that the attempt to resume from the ACPI S3 sleep state failed.

Parameters
[in] This Pointer to this instance of the PEI_S3_RESUME_PPI
Return values
EFI_ABORTED | Execution of the S3 resume boot script table failed.
EFI_NOT_FOUND | Some necessary information that is used for the S3 resume boot path could not be located.
VOID EFIAPI S3ResumeBootOs | ( | IN ACPI_S3_CONTEXT * | AcpiS3Context,
 |  | IN PEI_S3_RESUME_STATE * | PeiS3ResumeState
 | ) |  |

Jump to OS waking vector. The function will install boot script done PPI, report S3 resume status code, and then jump to OS waking vector.

Parameters
AcpiS3Context | a pointer to a structure of ACPI_S3_CONTEXT
PeiS3ResumeState | a pointer to a structure of PEI_S3_RESUME_STATE
VOID EFIAPI S3ResumeExecuteBootScript | ( | IN ACPI_S3_CONTEXT * | AcpiS3Context,
 |  | IN BOOT_SCRIPT_EXECUTOR_VARIABLE * | EfiBootScriptExecutorVariable
 | ) |  |

Jump to boot script executor driver.

The function will close and lock SMRAM and then jump to boot script execute driver to executing S3 boot script table.

Parameters
AcpiS3Context | a pointer to a structure of ACPI_S3_CONTEXT
EfiBootScriptExecutorVariable | The function entry to executing S3 boot Script table. This function is build in boot script execute driver
VOID SignalToSmmByCommunication ( IN EFI_GUID * HandlerType )

Signal to SMM through communication buffer way.

Parameters
[in] HandlerType SMI handler type to be signaled.
typedef VOID ( EFIAPI * ASM_TRANSFER_CONTROL )

a ASM function to transfer control to OS.

Parameters
S3WakingVector | The S3 waking up vector saved in ACPI Facs table
AcpiLowMemoryBase | a buffer under 1M which could be used during the transfer

Variable Documentation

GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt
Initial value:
= {
sizeof (mGdtEntries) - 1,
(UINTN) mGdtEntries
}
GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[]
Initial value:
= {
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
{{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
{{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}},
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
{{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
{{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}},
{{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}},
{{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}},
}
EFI_PEI_PPI_DESCRIPTOR mPpiList
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiPeiS3Resume2PpiGuid,
&mS3ResumePpi
}
EFI_PEI_PPI_DESCRIPTOR mPpiListEndOfPeiTable
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEfiEndOfPeiSignalPpiGuid,
0
}
EFI_PEI_PPI_DESCRIPTOR mPpiListPostScriptTable
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gPeiPostScriptTablePpiGuid,
0
}
EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable
Initial value:
= {
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
&gEdkiiS3SmmInitDoneGuid,
0
}
Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.uni File Reference

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Variables
S3Resume2Pei.uni File Reference

Variables

This module will execute the
boot script saved during last
boot and after 		that

Detailed Description

S3 Resume Module installs EFI_PEI_S3_RESUME2_PPI.

This module works with StandAloneBootScriptExecutor to S3 resume to OS. This module will excute the boot script saved during last boot and after that, control is passed to OS waking up handler.

Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2PeiExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
  • Universal
  • Acpi
  • S3Resume2Pei
S3Resume2PeiExtra.uni File Reference

Detailed Description

S3Resume2Pei Localized Strings and Content

Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/UefiCpuPkg.uni File Reference

  • File List
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  • UefiCpuPkg
Variables
UefiCpuPkg.uni File Reference

Variables

aligns the address on a KByte
boundary If 		enabled

Detailed Description

This Package provides UEFI compatible CPU modules and libraries.

This Package provides UEFI compatible CPU modules and libraries.

Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Generated on Tue Sep 1 2020 14:37:09 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/UefiCpuPkgExtra.uni File Reference

  • File List
  • Globals
  • UefiCpuPkg
UefiCpuPkgExtra.uni File Reference

Detailed Description

UefiCpu Package Localized Strings and Content.

Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.

This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

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AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • _
  • a
  • b
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  • d
  • e
  • f
  • g
  • h
  • i
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  • m
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  • t
  • u
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  • w
  • x
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- _ -

  • _ModuleEntryPoint() : PlatformSecLibNull.c
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AmdUefiCpuPkg: Globals

  • File List
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • a
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  • x
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- a -

  • AcquirePage() : SmmProfileArch.c
  • ActivateBTS() : SmmProfile.c
  • ActivateLBR() : SmmProfile.c
  • ActivateSingleStepDB() : SmmProfile.c
  • ActivateSmmProfile() : SmmProfile.c , SmmProfile.h
  • AddLocalApicMemorySpace() : CpuDxe.c
  • AddMemoryMappedIoSpace() : CpuDxe.c
  • AddPiResource() : SmmStm.c , SmmStm.h
  • AddResource() : SmmStm.c
  • AddSingleResource() : SmmStm.c
  • AdjustEntry() : RegisterCpuFeaturesLib.c
  • AdjustFeaturesDependence() : RegisterCpuFeaturesLib.c
  • AesniGetConfigData() : CpuCommonFeatures.h , Aesni.c
  • AesniInitialize() : Aesni.c , CpuCommonFeatures.h
  • AesniSupport() : Aesni.c , CpuCommonFeatures.h
  • AllCpusInSmmWithExceptions() : MpService.c
  • AllocateAcpiNvsMemory() : CpuS3Data.c
  • AllocateAcpiNvsMemoryBelow4G() : PiSmmCommunicationSmm.c
  • AllocateAlignedCodePages() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • AllocateCodePages() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • AllocatePageTableMemory() : PiSmmCpuDxeSmm.h , CpuPageTable.c , CpuPageTable.h , CpuPaging.c , PiSmmCpuDxeSmm.c
  • AllocateResetVector() : MpLib.c
  • AllocateZeroPages() : CpuS3Data.c
  • AllocPage() : PageTbl.c
  • AmiCpuPeiPreMemEntry() : AmiCpuPeiPreMem.c
  • AnalysisProcessorFeatures() : CpuFeaturesInitialize.c
  • ApFuncEnableX2Apic() : MpLib.c
  • APHandler() : MpService.c
  • ApInitializeSync() : MpLib.c
  • ApWakeupFunction() : MpLib.c
  • ArchGetIdtHandler() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchRestoreExceptionContext() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchSaveExceptionContext() : ArchExceptionHandler.c , CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchSetupExcpetionStack() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchUpdateIdtEntry() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • AsmExchangeRole() : MpLib.h
  • AsmGetAddressMap() : CpuS3.c , MpLib.h
  • AsmGetTemplateAddressMap() : CpuExceptionCommon.h
  • AsmGetTssTemplateMap() : CpuExceptionCommon.h
  • AsmSetDataSelectors() : S3Resume.c
  • AsmVectorNumFixup() : CpuExceptionCommon.h
  • AssignMemoryPageAttributes() : CpuPageTable.c , CpuPageTable.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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  • Globals
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  • x
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- b -

  • BackupAndPrepareWakeupBuffer() : MpLib.c
  • BiggestDep() : CpuFeaturesInitialize.c
  • BSPHandler() : MpService.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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  • Globals
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  • x
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- c -

  • C1eInitialize() : C1e.c , CpuCommonFeatures.h
  • C1eSupport() : CpuCommonFeatures.h , C1e.c
  • CalculateMaximumSupportAddress() : PageTbl.c
  • CalculateTimeout() : MpLib.c
  • CheckAllAPs() : MpLib.h , MpLib.c
  • CheckAndUpdateApsStatus() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • CheckApsStatus() : DxeMpLib.c
  • CheckCpuFeaturesDependency() : RegisterCpuFeaturesLib.c
  • CheckFeatureSupported() : SmmProfile.c , SmmProfile.h
  • CheckOverlapWithAllocatedBuffer() : PeiMpLib.c
  • CheckThisAP() : MpLib.c , MpLib.h
  • CheckTimeout() : MpLib.c
  • ClearTopLevelSmiStatus() : SmmCpuPlatformHookLib.h , SmmCpuPlatformHookLibNull.c
  • ClearTrapFlag() : SmmProfileArch.c , SmmProfileInternal.h , SmmProfileArch.c
  • ClockModulationInitialize() : ClockModulation.c , CpuCommonFeatures.h
  • ClockModulationSupport() : ClockModulation.c , CpuCommonFeatures.h
  • CollectBistDataFromHob() : CpuMp.c
  • CollectBistDataFromPpi() : CpuBist.c , CpuMpPei.h
  • CollectProcessorCount() : MpLib.c
  • CollectProcessorData() : CpuFeaturesInitialize.c
  • CommonExceptionHandler() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • CommonExceptionHandlerWorker() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
  • Communicate() : PiSmmCommunicationPei.c
  • ConfigSmmCodeAccessCheck() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • ConfigSmmCodeAccessCheckOnCurrentProcessor() : PiSmmCpuDxeSmm.c
  • ConvertMemoryPageAttributes() : CpuPageTable.c , CpuPaging.c , SmmCpuMemoryManagement.c
  • ConvertPageEntryAttribute() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • CopyRegisterTable() : CpuS3.c
  • CPU_FEATURE_GET_CONFIG_DATA : RegisterCpuFeaturesLib.h
  • CPU_FEATURE_INITIALIZE : RegisterCpuFeaturesLib.h
  • CPU_FEATURE_SUPPORT : RegisterCpuFeaturesLib.h
  • CpuCommonFeaturesLibConstructor() : CpuCommonFeaturesLib.c
  • CpuDisableInterrupt() : CpuDxe.c , CpuDxe.h
  • CpuEnableInterrupt() : CpuDxe.c , CpuDxe.h
  • CpuFeaturesDetect() : RegisterCpuFeaturesLib.h , CpuFeaturesInitialize.c
  • CpuFeaturesDxeInitialize() : CpuFeaturesDxe.c
  • CpuFeaturesInitialize() : RegisterCpuFeaturesLib.h , DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c
  • CpuFeaturesInitializeWorker() : CpuFeaturesDxe.c
  • CpuFeaturesPeimInitialize() : CpuFeaturesPei.c
  • CpuFlushCpuDataCache() : CpuDxe.c , CpuDxe.h
  • CpuGetInterruptState() : CpuDxe.c , CpuDxe.h
  • CpuGetTimerValue() : CpuDxe.c , CpuDxe.h
  • CpuInit() : CpuDxe.c , CpuDxe.h
  • CpuInitDataInitialize() : CpuFeaturesInitialize.c
  • CpuIo2Initialize() : CpuIo2Dxe.c
  • CpuIoCheckParameter() : CpuIo2Dxe.c , CpuIo2Smm.c , CpuIoPei.c
  • CpuIoInitialize() : CpuIoPei.c
  • CpuIoRead16() : CpuIoPei.c , CpuIoPei.h
  • CpuIoRead32() : CpuIoPei.c , CpuIoPei.h
  • CpuIoRead64() : CpuIoPei.c , CpuIoPei.h
  • CpuIoRead8() : CpuIoPei.c , CpuIoPei.h
  • CpuIoServiceRead() : CpuIo2Dxe.c , CpuIo2Dxe.h , CpuIo2Smm.c , CpuIoPei.c , CpuIoPei.h , CpuIo2Smm.h
  • CpuIoServiceWrite() : CpuIo2Dxe.c , CpuIo2Smm.c , CpuIo2Smm.h , CpuIoPei.c , CpuIoPei.h , CpuIo2Dxe.h
  • CpuIoWrite16() : CpuIoPei.c , CpuIoPei.h
  • CpuIoWrite32() : CpuIoPei.h , CpuIoPei.c
  • CpuIoWrite64() : CpuIoPei.h , CpuIoPei.c
  • CpuIoWrite8() : CpuIoPei.c , CpuIoPei.h
  • CpuMemoryServiceRead() : CpuIoPei.h , CpuIo2Smm.h , CpuIo2Smm.c , CpuIo2Dxe.h , CpuIo2Dxe.c , CpuIoPei.c
  • CpuMemoryServiceWrite() : CpuIo2Smm.h , CpuIoPei.c , CpuIo2Dxe.h , CpuIo2Dxe.c , CpuIoPei.h , CpuIo2Smm.c
  • CpuMemRead16() : CpuIoPei.c , CpuIoPei.h
  • CpuMemRead32() : CpuIoPei.h , CpuIoPei.c
  • CpuMemRead64() : CpuIoPei.h , CpuIoPei.c
  • CpuMemRead8() : CpuIoPei.h , CpuIoPei.c
  • CpuMemWrite16() : CpuIoPei.c , CpuIoPei.h
  • CpuMemWrite32() : CpuIoPei.h , CpuIoPei.c
  • CpuMemWrite64() : CpuIoPei.c , CpuIoPei.h
  • CpuMemWrite8() : CpuIoPei.c , CpuIoPei.h
  • CpuMpPeimInit() : CpuMpPei.c
  • CpuRegisterInterruptHandler() : CpuDxe.c , CpuDxe.h
  • CpuRegisterTableWrite() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • CpuRegisterTableWriteWorker() : RegisterCpuFeaturesLib.c
  • CpuS3DataInitialize() : CpuS3Data.c
  • CpuS3DataOnEndOfDxe() : CpuS3Data.c
  • CpuSetMemoryAttributes() : CpuDxe.c , CpuDxe.h
  • CpuSmmDebugEntry() : MpService.c
  • CpuSmmDebugExit() : MpService.c
  • CreatePageTable() : CpuPaging.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- d -

  • DebugExceptionHandler() : CpuDxe.h , CpuPageTable.c , SmmProfile.c
  • DeletePiResource() : SmmStm.c , SmmStm.h
  • DetectFeatureScope() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DetectNoneNeighborhoodFeatureScope() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DisableApicTimerInterrupt() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • DisableBTS() : SmmProfile.c
  • DisableLvtInterrupts() : BaseXApicX2ApicLib.c , LocalApicLib.h , BaseXApicLib.c
  • DisableReadOnlyPageWriteProtect() : CpuPageTable.c
  • DumpCpuContext() : ArchExceptionHandler.c
  • DumpCpuFeature() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DumpCpuFeatureMask() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DumpImageAndCpuContent() : ArchExceptionHandler.c , CpuExceptionCommon.h
  • DumpModuleImageInfo() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • DumpModuleInfoByIp() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • DumpRegisterTableOnProcessor() : CpuFeaturesInitialize.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- e -

  • EdkiiSmmClearMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • EdkiiSmmGetMemoryAttributes() : SmmCpuMemoryManagement.c , PiSmmCpuDxeSmm.h
  • EdkiiSmmSetMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • EFI_SM_MONITOR_STATE() : SmMonitorInit.h
  • EFI_STATUS() : SmmCpuService.h , SmMonitorInit.h
  • EistInitialize() : CpuCommonFeatures.h , Eist.c
  • EistSupport() : CpuCommonFeatures.h , Eist.c
  • EnableApicTimerInterrupt() : BaseXApicX2ApicLib.c , LocalApicLib.h , BaseXApicLib.c
  • EnableBTS() : SmmProfile.c
  • EnableDebugAgent() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • EnableDisableAP() : CpuMp.c , CpuMp.h
  • EnableDisableApWorker() : MpLib.h , MpLib.c
  • EnableMsegMsr() : SmmStm.c
  • EnablePaging() : CpuPaging.c
  • EnableReadOnlyPageWriteProtect() : CpuPageTable.c
  • EnlargeRegisterTable() : RegisterCpuFeaturesLib.c
  • EVENT_TYPE : StmApi.h
  • EvtBiosAccessToUnclaimedResource : StmApi.h
  • EvtInvalid : StmApi.h
  • EvtMleMax : StmApi.h
  • ExecuteDisableInitialize() : ExecuteDisable.c , CpuCommonFeatures.h
  • ExecuteDisableSupport() : ExecuteDisable.c , CpuCommonFeatures.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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  • i
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  • r
  • s
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  • w
  • x
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- f -

  • FastStringsInitialize() : CpuCommonFeatures.h , FastStrings.c
  • FeatureControlGetConfigData() : FeatureControl.c , CpuCommonFeatures.h
  • FillExchangeInfoData() : MpLib.c
  • FillProcessorInfo() : CpuFeaturesInitialize.c
  • FindAndReportEntryPoints() : SecMain.h , FindPeiCore.c
  • FindImageBase() : FindPeiCore.c
  • FindMicrocode() : AmiCpuPeiPreMem.c
  • FindMicrocodeInFv() : AmiCpuPeiPreMem.c
  • FindSmramInfo() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • FindSpecifyFeature() : RegisterCpuFeaturesLib.c
  • FinishSmmCpuFeaturesInitializeProcessor() : SmmCpuFeaturesLibNoStm.c , SmmCpuFeaturesLib.c , SmmStm.c
  • FlushTlbForAll() : SmmCpuMemoryManagement.c
  • FlushTlbOnCurrentProcessor() : SmmCpuMemoryManagement.c
  • FreeResetVector() : MpLib.c
  • FutureBSPProc() : MpLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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  • t
  • u
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  • w
  • x
Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- g -

  • Gen4GPageTable() : MpService.c , PiSmmCpuDxeSmm.h
  • GetAccNum() : PageTbl.c
  • GetAcpiCpuData() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c , CpuS3.c , PiSmmCpuDxeSmm.h
  • GetAcpiS3EnableFlag() : CpuS3.c , PiSmmCpuDxeSmm.h
  • GetAndUpdateAccNum() : PageTbl.c
  • GetApicId() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicMode() : BaseXApicX2ApicLib.c , LocalApicLib.h , BaseXApicLib.c
  • GetApicMsiAddress() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicMsiValue() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerCurrentCount() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerInitCount() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerInterruptState() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerState() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicVersion() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApLoopMode() : MpLib.c
  • GetApState() : MpLib.c
  • GetAttributesFromPageEntry() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • GetBistFromHob() : SecBist.c
  • GetBistInfoFromPpi() : CpuBist.c , SecBist.c
  • GetCommunicationContext() : PiSmmCommunicationPei.c
  • GetConfigurationPcd() : CpuFeaturesInitialize.c
  • GetCpuFeaturesData() : DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h
  • GetCpuIndex() : SmmProfile.c , SmmProfile.h
  • GetCpuMpData() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • GetCpuMpDataFromGuidedHob() : MpLib.c , MpLib.h
  • GetCurrentMicrocodeSignature() : Microcode.c
  • GetCurrentPagingContext() : CpuPageTable.c
  • GetExceptionHandlerData() : PeiCpuException.c
  • GetExceptionNameStr() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • GetFirmwareVariableMtrrCount() : MtrrLib.h , MtrrLib.c
  • GetFirmwareVariableMtrrCountWorker() : MtrrLib.c
  • GetGcdMemoryMap() : SmmCpuMemoryManagement.c
  • GetGdtr() : CpuMp.c , CpuMpPei.c
  • GetInitialApicId() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetLocalApicBaseAddress() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetMaxMemoryPage() : CpuPaging.c
  • GetMemorySpaceAttributeFromMtrrType() : CpuDxe.c
  • GetModeTransitionBuffer() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • GetMonitorState() : SmmStm.c , SmmStm.h
  • GetMpPpi() : PeiRegisterCpuFeaturesLib.c
  • GetMpProtocol() : DxeRegisterCpuFeaturesLib.c
  • GetNextWaitingProcessorNumber() : MpLib.c
  • GetNumberOfProcessor() : DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h
  • GetNumberOfProcessors() : CpuMp.h , CpuMp.c
  • GetPageTableBase() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • GetPageTableEntry() : CpuPaging.c , SmmCpuMemoryManagement.c , CpuPageTable.c
  • GetPageTableTopLevelType() : CpuPaging.c
  • GetPerformanceCounter() : X86TimerLib.c
  • GetPerformanceCounterProperties() : X86TimerLib.c
  • GetPhysicalAddressWidth() : CpuPaging.c
  • GetPiResource() : SmmStm.h , SmmStm.c
  • GetPlatformPageTableAttribute() : SmmCpuPlatformHookLib.h , SmmCpuPlatformHookLibNull.c
  • GetProcessorIndex() : PeiRegisterCpuFeaturesLib.c , DxeRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h
  • GetProcessorInfo() : CpuMp.h , CpuMp.c
  • GetProcessorInformation() : RegisterCpuFeatures.h , DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c
  • GetProcessorLocationByApicId() : BaseXApicLib.c , LocalApicLib.h , BaseXApicX2ApicLib.c
  • GetProcessorNumber() : MpLib.c
  • GetProtectedModeCS() : DxeMpLib.c , SmmFuncsArch.c
  • GetRegisterIndex() : SmramSaveState.c
  • GetResourceSize() : SmmStm.c
  • GetSmiCommandPort() : SmmProfile.c
  • GetSmiHandlerSize() : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • GetSmramInfoByHob() : PiSmmCommunicationSmm.c
  • GetSmramInfoByProtocol() : PiSmmCommunicationSmm.c
  • GetSourceFromDestinationOnBts() : SmmProfile.c
  • GetStackBase() : CpuPaging.c
  • GetStmResource() : SmmStm.h , SmmStm.c
  • GetSubEntriesNum() : PageTbl.c
  • GetSupportPcd() : CpuFeaturesInitialize.c
  • GetTimeInNanoSecond() : X86TimerLib.c
  • GetUefiMemoryAttributesTable() : SmmCpuMemoryManagement.c
  • GetUefiMemoryMap() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • GetVariableMtrrCount() : MtrrLib.c , MtrrLib.h
  • GetVariableMtrrCountWorker() : MtrrLib.c
  • GetVmcsSize() : SmmStm.c
  • GetWakeupBuffer() : MpLib.h , DxeMpLib.c , PeiMpLib.c
  • gPatchSmbase : SmramSaveState.c
  • GuardPagePFHandler() : SmmProfile.h , SmmProfile.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- h -

  • HandleSingleResource() : SmmStm.c
  • HookReturnFromSmm() : SmramSaveState.c , PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- i -

  • IdleLoopEventCallback() : CpuDxe.c
  • InitCommunicationContext() : PiSmmCommunicationPei.c
  • InitGdt() : PiSmmCpuDxeSmm.h , SmmFuncsArch.c
  • InitGlobalDescriptorTable() : CpuDxe.h , CpuGdt.c
  • InitializeAp() : CpuS3.c
  • InitializeApData() : MpLib.c
  • InitializeApicTimer() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • InitializeCpu() : CpuDxe.c
  • InitializeCpuAfterRebase() : CpuS3.c
  • InitializeCpuBeforeRebase() : CpuS3.c
  • InitializeCpuExceptionHandlers() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • InitializeCpuExceptionHandlersEx() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • InitializeCpuExceptionHandlersWorker() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
  • InitializeCpuInterruptHandlers() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • InitializeCpuMpWorker() : CpuMpPei.c , CpuMpPei.h
  • InitializeExceptionStackSwitchHandlers() : CpuMp.c , CpuMpPei.c
  • InitializeFloatingPointUnits() : UefiCpuLib.h
  • InitializeIDTSmmStackGuard() : SmmFuncsArch.c , PiSmmCpuDxeSmm.h , SmmFuncsArch.c
  • InitializeLocalApicSoftwareEnable() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • InitializeMpExceptionHandlers() : CpuMp.c
  • InitializeMpExceptionStackSwitchHandlers() : CpuMp.c , CpuMpPei.c
  • InitializeMpServiceData() : MpService.c , PiSmmCpuDxeSmm.h
  • InitializeMpSupport() : CpuMp.c , CpuMp.h
  • InitializeMpSyncData() : MpService.c , PiSmmCpuDxeSmm.h
  • InitializeMtrrMask() : CpuDxe.c
  • InitializePageTableLib() : CpuPageTable.h
  • InitializePageTablePool() : CpuPageTable.c
  • InitializeSmmCpuSemaphores() : MpService.c
  • InitializeSmmCpuServices() : CpuService.c , CpuService.h
  • InitializeSmmIdt() : PiSmmCpuDxeSmm.c
  • InitializeSmmTimer() : PiSmmCpuDxeSmm.h , SyncTimer.c
  • InitIdtr() : SmmProfile.c , SmmProfileInternal.h
  • InitInterruptDescriptorTable() : CpuDxe.c
  • InitMpGlobalData() : PeiMpLib.c , DxeMpLib.c , MpLib.h
  • InitMsrSpinLockByIndex() : PiSmmCpuDxeSmm.h
  • InitPagesForPFHandler() : SmmProfileArch.c , SmmProfileArch.h , SmmProfileArch.c , SmmProfileArch.h
  • InitPaging() : SmmProfile.c , SmmProfile.h
  • InitProtectedMemRange() : SmmProfile.c
  • InitSmmProfile() : SmmProfile.c , SmmProfile.h
  • InitSmmProfileCallBack() : SmmProfile.c
  • InitSmmProfileInternal() : SmmProfile.c
  • InitSmmS3Cr3() : SmmProfileArch.c , SmmProfileArch.h , SmmProfileArch.c
  • InitSmmS3ResumeState() : PiSmmCommunicationSmm.c , CpuS3.c , PiSmmCpuDxeSmm.h
  • InsertToAfterEntry() : RegisterCpuFeaturesLib.c
  • InsertToBeforeEntry() : RegisterCpuFeaturesLib.c
  • InstallSmiHandler() : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • InternalPrintMessage() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • InternalSmmStartupThisAp() : MpService.c
  • InternalSmstGetVendorTableByGuid() : PiSmmCommunicationPei.c
  • InternalX86Delay() : X86TimerLib.c
  • InternalX86GetTimerFrequency() : X86TimerLib.c
  • IntersectMemoryDescriptor() : CpuDxe.c
  • Is1GPageSupport() : PageTbl.c
  • IsAddressSplit() : SmmProfile.c , SmmProfileInternal.h
  • IsAddressValid() : SmmProfileInternal.h , SmmProfile.c
  • IsBitMaskMatch() : CpuFeaturesInitialize.c
  • IsBitMaskMatchCheck() : RegisterCpuFeaturesLib.c
  • IsBspExecuteDisableEnabled() : MpLib.c
  • IsCpuFeatureCapability() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • IsCpuFeatureInSetting() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • IsCpuFeatureMatch() : RegisterCpuFeaturesLib.c
  • IsCpuFeatureSetInCpuPcd() : RegisterCpuFeaturesLib.c
  • IsCpuFeatureSupported() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • IsCpuFeatureUserConfiguration() : RegisterCpuFeaturesLib.h , RegisterCpuFeaturesLib.c
  • IsExecuteDisableEnabled() : CpuPageTable.c
  • IsIa32PaeSupported() : CpuPaging.c
  • IsInSmm() : CpuPageTable.c
  • IsInSmmRanges() : SmmProfile.c
  • IsLmceOsEnabled() : MpService.c
  • IsLmceSignaled() : MpService.c
  • IsLongModeWakingVector() : S3Resume.c
  • IsMtrrSupported() : MtrrLib.h , MtrrLib.c
  • IsMwaitSupport() : MpLib.h , MpLib.c
  • IsPagingAndPageAddressExtensionsEnabled() : CpuDxe.c
  • IsReadOnlyPageWriteProtected() : CpuPageTable.c
  • IsSmmCommBufferForbiddenAddress() : SmmCpuMemoryManagement.c , PiSmmCpuDxeSmm.h
  • IsSyncTimerTimeout() : PiSmmCpuDxeSmm.h , SyncTimer.c
  • IsUefiPageNotPresent() : SmmCpuMemoryManagement.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- l -

  • LibReleaseSemaphore() : CpuFeaturesInitialize.c
  • LibWaitForSemaphore() : CpuFeaturesInitialize.c
  • LimitCpuidMaxvalInitialize() : LimitCpuIdMaxval.c , CpuCommonFeatures.h
  • LimitCpuidMaxvalSupport() : CpuCommonFeatures.h , LimitCpuIdMaxval.c
  • LmceInitialize() : MachineCheck.c , CpuCommonFeatures.h
  • LmceSupport() : CpuCommonFeatures.h , MachineCheck.c
  • LoadMonitor() : SmmStm.c , SmmStm.h
  • LoadMtrrData() : CpuS3.c
  • LocalApicBaseAddressMsrSupported() : BaseXApicX2ApicLib.c , BaseXApicLib.c
  • LockdownSemaphore() : MpService.c
  • LockFeatureControlRegisterInitialize() : FeatureControl.c , CpuCommonFeatures.h
  • LockFeatureControlRegisterSupport() : FeatureControl.c , CpuCommonFeatures.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- m -

  • McaInitialize() : CpuCommonFeatures.h , MachineCheck.c
  • McaSupport() : MachineCheck.c , CpuCommonFeatures.h
  • MceInitialize() : CpuCommonFeatures.h , MachineCheck.c
  • MceSupport() : MachineCheck.c , CpuCommonFeatures.h
  • McgCtlInitialize() : CpuCommonFeatures.h , MachineCheck.c
  • McgCtlSupport() : CpuCommonFeatures.h , MachineCheck.c
  • MemoryDiscoveredPpiNotifyCallback() : CpuMpPei.h , CpuPaging.c
  • MergeMemoryMapForNotPresentEntry() : SmmCpuMemoryManagement.c
  • MicrocodeDetect() : Microcode.c , MpLib.h
  • MicroSecondDelay() : X86TimerLib.c
  • MonitorMwaitInitialize() : CpuCommonFeatures.h , MonitorMwait.c
  • MonitorMwaitSupport() : CpuCommonFeatures.h , MonitorMwait.c
  • MpInitChangeApLoopCallback() : DxeMpLib.c
  • MpInitLibEnableDisableAP() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibGetNumberOfProcessors() : MpInitLib.h , MpLib.c
  • MpInitLibGetProcessorInfo() : MpInitLib.h , MpLib.c
  • MpInitLibInitialize() : MpLib.c , MpInitLib.h
  • MpInitLibStartupAllAPs() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibStartupThisAP() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibSwitchBSP() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibWhoAmI() : MpInitLib.h , MpLib.c
  • mSmmCpu : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • mSmmCpuHandle : PiSmmCpuDxeSmm.c
  • mSmmCpuIoType : SmramSaveState.c
  • mSmmCpuIoWidth : SmramSaveState.c
  • mSmmCpuRegisterRanges : SmramSaveState.c
  • mSmmCpuWidthOffset : SmramSaveState.c
  • mSmmMemoryAttribute : PiSmmCpuDxeSmm.c
  • mSmmSaveStateRegisterLma : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • MtrrDebugPrintAllMtrrs() : MtrrLib.h , MtrrLib.c
  • MtrrDebugPrintAllMtrrsWorker() : MtrrLib.c
  • MtrrGetAllMtrrs() : MtrrLib.h , MtrrLib.c
  • MtrrGetDefaultMemoryType() : MtrrLib.h , MtrrLib.c
  • MtrrGetDefaultMemoryTypeWorker() : MtrrLib.c
  • MtrrGetFixedMtrr() : MtrrLib.c , MtrrLib.h
  • MtrrGetFixedMtrrWorker() : MtrrLib.c
  • MtrrGetMemoryAttribute() : MtrrLib.h , MtrrLib.c
  • MtrrGetMemoryAttributeByAddressWorker() : MtrrLib.c
  • MtrrGetMemoryAttributeInVariableMtrr() : MtrrLib.h , MtrrLib.c
  • MtrrGetMemoryAttributeInVariableMtrrWorker() : MtrrLib.c
  • MtrrGetVariableMtrr() : MtrrLib.c , MtrrLib.h
  • MtrrGetVariableMtrrWorker() : MtrrLib.c
  • MtrrLibAppendVariableMtrr() : MtrrLib.c
  • MtrrLibApplyFixedMtrrs() : MtrrLib.c
  • MtrrLibApplyVariableMtrrs() : MtrrLib.c
  • MtrrLibBiggestAlignment() : MtrrLib.c
  • MtrrLibCalculateLeastMtrrs() : MtrrLib.c
  • MtrrLibCalculateMtrrs() : MtrrLib.c
  • MtrrLibCalculateSubtractivePath() : MtrrLib.c
  • MtrrLibGetCompatibleTypes() : MtrrLib.c
  • MtrrLibGetNumberOfTypes() : MtrrLib.c
  • MtrrLibGetRawVariableRanges() : MtrrLib.c
  • MtrrLibInitializeMtrrMask() : MtrrLib.c
  • MtrrLibIsPowerOfTwo() : MtrrLib.c
  • MtrrLibLowestType() : MtrrLib.c
  • MtrrLibMergeVariableMtrr() : MtrrLib.c
  • MtrrLibPostMtrrChange() : MtrrLib.c
  • MtrrLibPostMtrrChangeEnableCache() : MtrrLib.c
  • MtrrLibPrecedence() : MtrrLib.c
  • MtrrLibPreMtrrChange() : MtrrLib.c
  • MtrrLibProgramFixedMtrr() : MtrrLib.c
  • MtrrLibSetBelow1MBMemoryAttribute() : MtrrLib.c
  • MtrrLibSetMemoryRanges() : MtrrLib.c
  • MtrrLibSetMemoryType() : MtrrLib.c
  • MtrrLibTypeLeftPrecedeRight() : MtrrLib.c
  • MtrrSetAllMtrrs() : MtrrLib.h , MtrrLib.c
  • MtrrSetFixedMtrr() : MtrrLib.h , MtrrLib.c
  • MtrrSetFixedMtrrWorker() : MtrrLib.c
  • MtrrSetMemoryAttribute() : MtrrLib.h , MtrrLib.c
  • MtrrSetMemoryAttributeInMtrrSettings() : MtrrLib.c , MtrrLib.h
  • MtrrSetMemoryAttributesInMtrrSettings() : MtrrLib.c , MtrrLib.h
  • MtrrSetVariableMtrr() : MtrrLib.c , MtrrLib.h
  • MtrrSetVariableMtrrWorker() : MtrrLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- n -

  • NanoSecondDelay() : X86TimerLib.c
  • NeedSplitPage() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • NotifyOnS3SmmInitDonePpi() : PeiMpLib.c
  • NotifyStmResourceChange() : SmmStm.c , SmmStm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- p -

  • PAGE_TABLE_LIB_ALLOCATE_PAGES : CpuPageTable.h
  • PageAttributeToLength() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • PageAttributeToMask() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • PageFaultExceptionHandler() : CpuDxe.h , CpuPageTable.c
  • PageFaultIdtHandlerSmmProfile() : SmmProfile.h
  • PatchGdtIdtMap() : SmmCpuMemoryManagement.c
  • PatchSmmSaveStateMap() : SmmCpuMemoryManagement.c
  • PeiEnableDisableAP() : CpuMpPei.c , CpuMpPei.h
  • PeiGetNumberOfProcessors() : CpuMpPei.c , CpuMpPei.h
  • PeiGetProcessorInfo() : CpuMpPei.h , CpuMpPei.c
  • PeimS3ResumeEntryPoint() : S3Resume.c
  • PeiStartupAllAPs() : CpuMpPei.c , CpuMpPei.h
  • PeiStartupThisAP() : CpuMpPei.c , CpuMpPei.h
  • PeiSwitchBSP() : CpuMpPei.c , CpuMpPei.h
  • PeiWhoAmI() : CpuMpPei.c , CpuMpPei.h
  • PendingBreakInitialize() : CpuCommonFeatures.h , PendingBreak.c
  • PendingBreakSupport() : CpuCommonFeatures.h , PendingBreak.c
  • PerformPreTasks() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • PerformRemainingTasks() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • PiCpuSmmEntry() : PiSmmCpuDxeSmm.c
  • PiSmmCommunicationHandler() : PiSmmCommunicationSmm.c
  • PiSmmCommunicationPeiEntryPoint() : PiSmmCommunicationPei.c
  • PiSmmCommunicationSmmEntryPoint() : PiSmmCommunicationSmm.c
  • PiSmmCpuSmiEntryFixupAddress() : PiSmmCpuDxeSmm.h
  • PiSmmCpuSmmInitFixupAddress() : PiSmmCpuDxeSmm.h
  • PlatformSmmBspElection() : SmmCpuPlatformHookLib.h , SmmCpuPlatformHookLibNull.c
  • PlatformValidSmi() : SmmCpuPlatformHookLib.h , SmmCpuPlatformHookLibNull.c
  • PpinInitialize() : Ppin.c , CpuCommonFeatures.h
  • PpinSupport() : CpuCommonFeatures.h , Ppin.c
  • PrepareApStartupVector() : CpuS3.c
  • PreSmmCpuRegisterTableWrite() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • ProcessLibraryConstructorList() : SecMain.h
  • ProcTraceGetConfigData() : CpuCommonFeatures.h , ProcTrace.c
  • ProcTraceInitialize() : CpuCommonFeatures.h , ProcTrace.c
  • ProcTraceSupport() : ProcTrace.c , CpuCommonFeatures.h
  • ProgramProcessorRegister() : CpuS3.c , CpuFeaturesInitialize.c
  • ProgramVirtualWireMode() : BaseXApicX2ApicLib.c , BaseXApicLib.c , LocalApicLib.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- r -

  • ReadAndVerifyVectorInfo() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • ReadLocalApicReg() : BaseXApicX2ApicLib.c , DxeMpLib.c , BaseXApicLib.c
  • ReadSaveStateRegister() : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • ReadSaveStateRegisterByIndex() : SmramSaveState.c
  • ReclaimPages() : PageTbl.c
  • RefreshGcdMemoryAttributes() : CpuDxe.c
  • RefreshGcdMemoryAttributesFromPaging() : CpuDxe.h , CpuPageTable.c
  • RefreshMemoryAttributesFromMtrr() : CpuDxe.c
  • RegisterCpuFeature() : RegisterCpuFeaturesLib.h , RegisterCpuFeaturesLib.c
  • RegisterCpuFeatureWorker() : RegisterCpuFeaturesLib.c
  • RegisterCpuInterruptHandler() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • RegisterCpuInterruptHandlerWorker() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
  • RegisterSmmEntry() : MpService.c , PiSmmCpuDxeSmm.h
  • ReleaseAllAPs() : MpService.c
  • ReleaseSemaphore() : MpService.c
  • RelocateApLoop() : DxeMpLib.c
  • ReplaceOSMtrrs() : MpService.c
  • RepublishSecPlatformInformationPpi() : SecBist.c , SecMain.h
  • ResetProcessorToIdleState() : MpLib.c
  • RestorePageTableAbove4G() : SmmProfileArch.c , SmmProfileArch.h , SmmProfileArch.c
  • RestorePageTableBelow4G() : SmmProfile.c
  • RestoreS3PageTables() : S3Resume.c
  • RestoreSmmConfigurationInS3() : CpuS3.c , PiSmmCpuDxeSmm.h
  • RestoreVolatileRegisters() : MpLib.c
  • RestoreWakeupBuffer() : MpLib.c
  • RTIT_OUTPUT_SCHEME : ProcTrace.c
  • RTIT_TOPA_MEMORY_SIZE : ArchitecturalMsr.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- s -

  • S3ReleaseSemaphore() : CpuS3.c
  • S3RestoreConfig2() : S3Resume.c
  • S3ResumeBootOs() : S3Resume.c
  • S3ResumeExecuteBootScript() : S3Resume.c
  • S3WaitForSemaphore() : CpuS3.c
  • SaveCpuMpData() : PeiMpLib.c , DxeMpLib.c , MpLib.h
  • SaveLocalApicTimerSetting() : MpLib.c
  • SaveVolatileRegisters() : MpLib.c
  • SearchGcdMemorySpaces() : CpuDxe.c
  • SecPerformancePpiCallBack() : SecMain.c , SecMain.h
  • SecPlatformDisableTemporaryMemory() : PlatformSecLib.h , PlatformSecLibNull.c
  • SecPlatformInformation() : PlatformSecLib.h , PlatformSecLibNull.c
  • SecPlatformInformation2() : CpuBist.c , CpuMpPei.h
  • SecPlatformInformation2Bist() : SecBist.c , SecMain.h
  • SecPlatformInformationBist() : SecBist.c , SecMain.h
  • SecPlatformMain() : PlatformSecLib.h , PlatformSecLibNull.c
  • SecStartup() : SecMain.c , SecMain.h
  • SecStartupPhase2() : SecMain.c
  • SecTemporaryRamDone() : SecMain.c , SecMain.h
  • SemaphoreHook() : PiSmmCpuDxeSmm.h , Semaphore.c
  • SendApicEoi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendFixedIpi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendFixedIpiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitIpi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitIpiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitSipiSipi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitSipiSipiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendIpi() : BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendSmiIpi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendSmiIpiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SetAccNum() : PageTbl.c
  • SetApicMode() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SetApState() : MpLib.c
  • SetCapabilityPcd() : CpuFeaturesInitialize.c
  • SetCodeSelector() : CpuDxe.h
  • SetCommunicationContext() : PiSmmCommunicationPei.c , PiSmmCommunicationSmm.c
  • SetCpuFeaturesBitMask() : RegisterCpuFeaturesLib.c
  • SetDataSelectors() : CpuDxe.h
  • SetExceptionHandlerData() : PeiCpuException.c
  • SetGcdMemorySpaceAttributes() : CpuDxe.c
  • SetLocalApicBaseAddress() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SetMemMapAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SetMtrrsFromBuffer() : CpuDxe.c
  • SetPageTableAttributes() : PageTbl.c , PiSmmCpuDxeSmm.h , PageTbl.c
  • SetProcessorRegister() : CpuFeaturesInitialize.c , RegisterCpuFeatures.h
  • SetRegister() : CpuS3.c
  • SetSettingPcd() : CpuFeaturesInitialize.c
  • SetStaticPageTable() : PageTbl.c
  • SetSubEntriesNum() : PageTbl.c
  • SetUefiMemMapAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SetupStackGuardPage() : CpuPaging.c
  • SignalToSmmByCommunication() : S3Resume.c
  • SmiDefaultPFHandler() : PageTbl.c , SmmProfileInternal.h , PageTbl.c
  • SmiPFHandler() : PageTbl.c , PiSmmCpuDxeSmm.h , PageTbl.c
  • SmiRendezvous() : MpService.c
  • SMM_PAGE_SIZE_TYPE : SmmCpuPlatformHookLib.h
  • SMM_REG_NAME : SmmCpuFeaturesLib.h
  • SmmAddProcessor() : CpuService.c , CpuService.h
  • SmmBlockingStartupThisAp() : MpService.c , PiSmmCpuDxeSmm.h
  • SmmClearMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmClearMemoryAttributesEx() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmConfigurationEventNotify() : CpuFeaturesDxe.c
  • SmmCpuFeaturesAllocatePageTableMemory() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesCompleteSmmReadyToLock() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesDisableSmrr() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesGetSmiHandlerSize() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLibNoStm.c , SmmStm.c
  • SmmCpuFeaturesGetSmmRegister() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesHookReturnFromSmm() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesInitializeProcessor() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesInstallSmiHandler() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLibNoStm.c , SmmStm.c
  • SmmCpuFeaturesIsSmmRegisterSupported() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesLibConstructor() : SmmCpuFeaturesLib.c , SmmStm.c
  • SmmCpuFeaturesLibStmConstructor() : SmmStm.c
  • SmmCpuFeaturesLibStmSmiEntryFixupAddress() : SmmStm.h
  • SmmCpuFeaturesNeedConfigureMtrrs() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesReadSaveStateRegister() : SmmCpuFeaturesLib.c , SmmCpuFeaturesLib.h
  • SmmCpuFeaturesReenableSmrr() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesRendezvousEntry() : SmmCpuFeaturesLib.c , SmmCpuFeaturesLib.h
  • SmmCpuFeaturesRendezvousExit() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesSetSmmRegister() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesSmmRelocationComplete() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesWriteSaveStateRegister() : SmmCpuFeaturesLib.c , SmmCpuFeaturesLib.h
  • SmmCpuIo2Initialize() : CpuIo2Smm.c
  • SmmCpuUpdate() : CpuService.c , CpuService.h
  • SmmEndOfDxeEventNotify() : SmmStm.c
  • SmmGetProcessorInfo() : CpuService.c , CpuService.h
  • SmmGetSystemConfigurationTable() : SmmCpuMemoryManagement.c
  • SmmInitHandler() : PiSmmCpuDxeSmm.c
  • SmmInitPageTable() : PageTbl.c , PiSmmCpuDxeSmm.h , PageTbl.c
  • SmmProfilePFHandler() : SmmProfile.c , SmmProfile.h
  • SmmProfileRecordSmiNum() : SmmProfile.c , SmmProfile.h
  • SmmProfileStart() : SmmProfile.c , SmmProfile.h
  • SmmReadSaveState() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • SmmReadyToLockEventNotify() : PiSmmCpuDxeSmm.c
  • SmmRegFeatureControl : SmmCpuFeaturesLib.h
  • SmmRegisterExceptionHandler() : CpuService.h , CpuService.c
  • SmmRegSmmBlocked : SmmCpuFeaturesLib.h
  • SmmRegSmmDelayed : SmmCpuFeaturesLib.h
  • SmmRegSmmEnable : SmmCpuFeaturesLib.h
  • SmmRelocateBases() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • SmmRelocationSemaphoreComplete() : PiSmmCpuDxeSmm.h
  • SmmRelocationSemaphoreComplete32() : Semaphore.c
  • SmmRemoveProcessor() : CpuService.c , CpuService.h
  • SmmRestoreCpu() : CpuS3.c
  • SmmSetMemoryAttributes() : SmmCpuMemoryManagement.c , PiSmmCpuDxeSmm.h
  • SmmSetMemoryAttributesEx() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmStartupThisAp() : MpService.c , PiSmmCpuDxeSmm.h
  • SmmStmExceptionHandler() : SmmStmSupport.c , SmmStm.h
  • SmmStmSetup() : SmmStm.c
  • SmmStmTeardown() : SmmStm.c
  • SmmSwitchBsp() : CpuService.h , CpuService.c
  • SmmWaitForApArrival() : MpService.c
  • SmmWhoAmI() : CpuService.c , CpuService.h
  • SmmWriteSaveState() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • SmxInitialize() : FeatureControl.c , CpuCommonFeatures.h
  • SmxSupport() : CpuCommonFeatures.h , FeatureControl.c
  • SortApicId() : MpLib.c
  • SortMemoryMap() : SmmCpuMemoryManagement.c
  • SplitPage() : CpuPageTable.c , CpuPaging.c , SmmCpuMemoryManagement.c
  • StandardSignatureIsAuthenticAMD() : BaseXApicX2ApicLib.c , BaseXApicLib.c
  • StartSyncTimer() : SyncTimer.c , PiSmmCpuDxeSmm.h
  • StartupAllAPs() : CpuMp.c , CpuMp.h
  • StartupAllAPsWorker() : MpLib.h , MpLib.c
  • StartupAPsWorker() : PeiRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h , DxeRegisterCpuFeaturesLib.c
  • StartupThisAP() : CpuMp.h , CpuMp.c
  • StartupThisAPWorker() : MpLib.c , MpLib.h
  • STM_REGISTER_VIOLATION_TYPE : StmResourceDescriptor.h
  • STM_STATUS : StmStatusCode.h
  • StmCheckStmImage() : SmmStm.c
  • StmGen4GPageTable() : SmmStmSupport.c , SmmStm.h , SmmStmSupport.c
  • StmLoadStmImage() : SmmStm.c
  • StmSmmConfigurationTableInit() : SmmStm.h , SmmStm.c
  • SupportedMaskAnd() : CpuFeaturesInitialize.c
  • SupportedMaskCleanBit() : CpuFeaturesInitialize.c
  • SupportedMaskOr() : CpuFeaturesInitialize.c
  • SwitchBSP() : CpuMp.c , CpuMp.h
  • SwitchBspAfterFeaturesInitialize() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • SwitchBSPWorker() : MpLib.h , MpLib.c
  • SwitchNewBsp() : PeiRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h , DxeRegisterCpuFeaturesLib.c
  • SyncLocalApicTimerSetting() : MpLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- t -

  • TimedWaitForApFinish() : MpLib.c
  • TransferApToSafeState() : SmmFuncsArch.c , PiSmmCpuDxeSmm.h
  • TXT_SMM_PROTECTION_EXCEPTION_TYPE : StmApi.h
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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- u -

  • UpdateIdtTable() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
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AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- v -

  • ValidateResource() : SmmStm.c
  • VmxInitialize() : CpuCommonFeatures.h , FeatureControl.c
  • VmxSupport() : FeatureControl.c , CpuCommonFeatures.h
  • VOID() : MpLib.h , S3Resume.c
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AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- w -

  • WaitApWakeup() : MpLib.c
  • WaitForAllAPs() : MpService.c
  • WaitForSemaphore() : MpService.c
  • WakeUpAP() : MpLib.c , MpLib.h
  • WhoAmI() : CpuMp.c , CpuMp.h
  • WriteLocalApicReg() : BaseXApicX2ApicLib.c , DxeMpLib.c , BaseXApicLib.c
  • WriteSaveStateRegister() : SmramSaveState.c , PiSmmCpuDxeSmm.h
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AmdUefiCpuPkg: Globals

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Here is a list of all documented functions, variables, defines, enums, and typedefs with links to the documentation:

- x -

  • X2ApicGetConfigData() : CpuCommonFeatures.h , X2Apic.c
  • X2ApicInitialize() : X2Apic.c , CpuCommonFeatures.h
  • X2ApicSupport() : X2Apic.c , CpuCommonFeatures.h
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- _ -

  • _ModuleEntryPoint() : PlatformSecLibNull.c
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AmdUefiCpuPkg: Globals

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- a -

  • AcquirePage() : SmmProfileArch.c
  • ActivateBTS() : SmmProfile.c
  • ActivateLBR() : SmmProfile.c
  • ActivateSingleStepDB() : SmmProfile.c
  • ActivateSmmProfile() : SmmProfile.c , SmmProfile.h
  • AddLocalApicMemorySpace() : CpuDxe.c
  • AddMemoryMappedIoSpace() : CpuDxe.c
  • AddPiResource() : SmmStm.c , SmmStm.h
  • AddResource() : SmmStm.c
  • AddSingleResource() : SmmStm.c
  • AdjustEntry() : RegisterCpuFeaturesLib.c
  • AdjustFeaturesDependence() : RegisterCpuFeaturesLib.c
  • AesniGetConfigData() : CpuCommonFeatures.h , Aesni.c
  • AesniInitialize() : Aesni.c , CpuCommonFeatures.h
  • AesniSupport() : Aesni.c , CpuCommonFeatures.h
  • AllCpusInSmmWithExceptions() : MpService.c
  • AllocateAcpiNvsMemory() : CpuS3Data.c
  • AllocateAcpiNvsMemoryBelow4G() : PiSmmCommunicationSmm.c
  • AllocateAlignedCodePages() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • AllocateCodePages() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • AllocatePageTableMemory() : PiSmmCpuDxeSmm.h , CpuPageTable.c , CpuPageTable.h , CpuPaging.c , PiSmmCpuDxeSmm.c
  • AllocateResetVector() : MpLib.c
  • AllocateZeroPages() : CpuS3Data.c
  • AllocPage() : PageTbl.c
  • AmiCpuPeiPreMemEntry() : AmiCpuPeiPreMem.c
  • AnalysisProcessorFeatures() : CpuFeaturesInitialize.c
  • ApFuncEnableX2Apic() : MpLib.c
  • APHandler() : MpService.c
  • ApInitializeSync() : MpLib.c
  • ApWakeupFunction() : MpLib.c
  • ArchGetIdtHandler() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchRestoreExceptionContext() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchSaveExceptionContext() : ArchExceptionHandler.c , CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchSetupExcpetionStack() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • ArchUpdateIdtEntry() : CpuExceptionCommon.h , ArchExceptionHandler.c
  • AsmExchangeRole() : MpLib.h
  • AsmGetAddressMap() : CpuS3.c , MpLib.h
  • AsmGetTemplateAddressMap() : CpuExceptionCommon.h
  • AsmGetTssTemplateMap() : CpuExceptionCommon.h
  • AsmSetDataSelectors() : S3Resume.c
  • AsmVectorNumFixup() : CpuExceptionCommon.h
  • AssignMemoryPageAttributes() : CpuPageTable.c , CpuPageTable.h
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AmdUefiCpuPkg: Globals

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- b -

  • BackupAndPrepareWakeupBuffer() : MpLib.c
  • BiggestDep() : CpuFeaturesInitialize.c
  • BSPHandler() : MpService.c
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AmdUefiCpuPkg: Globals

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- c -

  • C1eInitialize() : C1e.c , CpuCommonFeatures.h
  • C1eSupport() : CpuCommonFeatures.h , C1e.c
  • CalculateMaximumSupportAddress() : PageTbl.c
  • CalculateTimeout() : MpLib.c
  • CheckAllAPs() : MpLib.h , MpLib.c
  • CheckAndUpdateApsStatus() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • CheckApsStatus() : DxeMpLib.c
  • CheckCpuFeaturesDependency() : RegisterCpuFeaturesLib.c
  • CheckFeatureSupported() : SmmProfile.c , SmmProfile.h
  • CheckOverlapWithAllocatedBuffer() : PeiMpLib.c
  • CheckThisAP() : MpLib.c , MpLib.h
  • CheckTimeout() : MpLib.c
  • ClearTopLevelSmiStatus() : SmmCpuPlatformHookLib.h , SmmCpuPlatformHookLibNull.c
  • ClearTrapFlag() : SmmProfileArch.c , SmmProfileInternal.h , SmmProfileArch.c
  • ClockModulationInitialize() : ClockModulation.c , CpuCommonFeatures.h
  • ClockModulationSupport() : ClockModulation.c , CpuCommonFeatures.h
  • CollectBistDataFromHob() : CpuMp.c
  • CollectBistDataFromPpi() : CpuBist.c , CpuMpPei.h
  • CollectProcessorCount() : MpLib.c
  • CollectProcessorData() : CpuFeaturesInitialize.c
  • CommonExceptionHandler() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • CommonExceptionHandlerWorker() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
  • Communicate() : PiSmmCommunicationPei.c
  • ConfigSmmCodeAccessCheck() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • ConfigSmmCodeAccessCheckOnCurrentProcessor() : PiSmmCpuDxeSmm.c
  • ConvertMemoryPageAttributes() : CpuPageTable.c , CpuPaging.c , SmmCpuMemoryManagement.c
  • ConvertPageEntryAttribute() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • CopyRegisterTable() : CpuS3.c
  • CpuCommonFeaturesLibConstructor() : CpuCommonFeaturesLib.c
  • CpuDisableInterrupt() : CpuDxe.c , CpuDxe.h
  • CpuEnableInterrupt() : CpuDxe.c , CpuDxe.h
  • CpuFeaturesDetect() : RegisterCpuFeaturesLib.h , CpuFeaturesInitialize.c
  • CpuFeaturesDxeInitialize() : CpuFeaturesDxe.c
  • CpuFeaturesInitialize() : RegisterCpuFeaturesLib.h , DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c
  • CpuFeaturesInitializeWorker() : CpuFeaturesDxe.c
  • CpuFeaturesPeimInitialize() : CpuFeaturesPei.c
  • CpuFlushCpuDataCache() : CpuDxe.h , CpuDxe.c
  • CpuGetInterruptState() : CpuDxe.c , CpuDxe.h
  • CpuGetTimerValue() : CpuDxe.c , CpuDxe.h
  • CpuInit() : CpuDxe.c , CpuDxe.h
  • CpuInitDataInitialize() : CpuFeaturesInitialize.c
  • CpuIo2Initialize() : CpuIo2Dxe.c
  • CpuIoCheckParameter() : CpuIo2Dxe.c , CpuIo2Smm.c , CpuIoPei.c
  • CpuIoInitialize() : CpuIoPei.c
  • CpuIoRead16() : CpuIoPei.c , CpuIoPei.h
  • CpuIoRead32() : CpuIoPei.c , CpuIoPei.h
  • CpuIoRead64() : CpuIoPei.c , CpuIoPei.h
  • CpuIoRead8() : CpuIoPei.c , CpuIoPei.h
  • CpuIoServiceRead() : CpuIo2Dxe.c , CpuIo2Dxe.h , CpuIo2Smm.h , CpuIoPei.c , CpuIoPei.h , CpuIo2Smm.c
  • CpuIoServiceWrite() : CpuIo2Dxe.h , CpuIo2Smm.c , CpuIo2Smm.h , CpuIoPei.h , CpuIoPei.c , CpuIo2Dxe.c
  • CpuIoWrite16() : CpuIoPei.c , CpuIoPei.h
  • CpuIoWrite32() : CpuIoPei.c , CpuIoPei.h
  • CpuIoWrite64() : CpuIoPei.h , CpuIoPei.c
  • CpuIoWrite8() : CpuIoPei.c , CpuIoPei.h
  • CpuMemoryServiceRead() : CpuIoPei.c , CpuIoPei.h , CpuIo2Dxe.c , CpuIo2Dxe.h , CpuIo2Smm.h , CpuIo2Smm.c
  • CpuMemoryServiceWrite() : CpuIoPei.c , CpuIo2Dxe.c , CpuIo2Smm.c , CpuIo2Smm.h , CpuIo2Dxe.h , CpuIoPei.h
  • CpuMemRead16() : CpuIoPei.c , CpuIoPei.h
  • CpuMemRead32() : CpuIoPei.h , CpuIoPei.c
  • CpuMemRead64() : CpuIoPei.h , CpuIoPei.c
  • CpuMemRead8() : CpuIoPei.h , CpuIoPei.c
  • CpuMemWrite16() : CpuIoPei.c , CpuIoPei.h
  • CpuMemWrite32() : CpuIoPei.h , CpuIoPei.c
  • CpuMemWrite64() : CpuIoPei.c , CpuIoPei.h
  • CpuMemWrite8() : CpuIoPei.c , CpuIoPei.h
  • CpuMpPeimInit() : CpuMpPei.c
  • CpuRegisterInterruptHandler() : CpuDxe.h , CpuDxe.c
  • CpuRegisterTableWrite() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • CpuRegisterTableWriteWorker() : RegisterCpuFeaturesLib.c
  • CpuS3DataInitialize() : CpuS3Data.c
  • CpuS3DataOnEndOfDxe() : CpuS3Data.c
  • CpuSetMemoryAttributes() : CpuDxe.c , CpuDxe.h
  • CpuSmmDebugEntry() : MpService.c
  • CpuSmmDebugExit() : MpService.c
  • CreatePageTable() : CpuPaging.c
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- d -

  • DebugExceptionHandler() : CpuDxe.h , CpuPageTable.c , SmmProfile.c
  • DeletePiResource() : SmmStm.c , SmmStm.h
  • DetectFeatureScope() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DetectNoneNeighborhoodFeatureScope() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DisableApicTimerInterrupt() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • DisableBTS() : SmmProfile.c
  • DisableLvtInterrupts() : BaseXApicX2ApicLib.c , LocalApicLib.h , BaseXApicLib.c
  • DisableReadOnlyPageWriteProtect() : CpuPageTable.c
  • DumpCpuContext() : ArchExceptionHandler.c
  • DumpCpuFeature() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DumpCpuFeatureMask() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c
  • DumpImageAndCpuContent() : ArchExceptionHandler.c , CpuExceptionCommon.h
  • DumpModuleImageInfo() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • DumpModuleInfoByIp() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • DumpRegisterTableOnProcessor() : CpuFeaturesInitialize.c
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- e -

  • EdkiiSmmClearMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • EdkiiSmmGetMemoryAttributes() : SmmCpuMemoryManagement.c , PiSmmCpuDxeSmm.h
  • EdkiiSmmSetMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • EFI_SM_MONITOR_STATE() : SmMonitorInit.h
  • EFI_STATUS() : SmmCpuService.h , SmMonitorInit.h
  • EistInitialize() : CpuCommonFeatures.h , Eist.c
  • EistSupport() : CpuCommonFeatures.h , Eist.c
  • EnableApicTimerInterrupt() : BaseXApicX2ApicLib.c , LocalApicLib.h , BaseXApicLib.c
  • EnableBTS() : SmmProfile.c
  • EnableDebugAgent() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • EnableDisableAP() : CpuMp.c , CpuMp.h
  • EnableDisableApWorker() : MpLib.c , MpLib.h
  • EnableMsegMsr() : SmmStm.c
  • EnablePaging() : CpuPaging.c
  • EnableReadOnlyPageWriteProtect() : CpuPageTable.c
  • EnlargeRegisterTable() : RegisterCpuFeaturesLib.c
  • ExecuteDisableInitialize() : ExecuteDisable.c , CpuCommonFeatures.h
  • ExecuteDisableSupport() : CpuCommonFeatures.h , ExecuteDisable.c
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- f -

  • FastStringsInitialize() : CpuCommonFeatures.h , FastStrings.c
  • FeatureControlGetConfigData() : FeatureControl.c , CpuCommonFeatures.h
  • FillExchangeInfoData() : MpLib.c
  • FillProcessorInfo() : CpuFeaturesInitialize.c
  • FindAndReportEntryPoints() : SecMain.h , FindPeiCore.c
  • FindImageBase() : FindPeiCore.c
  • FindMicrocode() : AmiCpuPeiPreMem.c
  • FindMicrocodeInFv() : AmiCpuPeiPreMem.c
  • FindSmramInfo() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • FindSpecifyFeature() : RegisterCpuFeaturesLib.c
  • FinishSmmCpuFeaturesInitializeProcessor() : SmmCpuFeaturesLibNoStm.c , SmmCpuFeaturesLib.c , SmmStm.c
  • FlushTlbForAll() : SmmCpuMemoryManagement.c
  • FlushTlbOnCurrentProcessor() : SmmCpuMemoryManagement.c
  • FreeResetVector() : MpLib.c
  • FutureBSPProc() : MpLib.c
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  • Gen4GPageTable() : MpService.c , PiSmmCpuDxeSmm.h
  • GetAccNum() : PageTbl.c
  • GetAcpiCpuData() : RegisterCpuFeatures.h , RegisterCpuFeaturesLib.c , CpuS3.c , PiSmmCpuDxeSmm.h
  • GetAcpiS3EnableFlag() : CpuS3.c , PiSmmCpuDxeSmm.h
  • GetAndUpdateAccNum() : PageTbl.c
  • GetApicId() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicMode() : BaseXApicX2ApicLib.c , LocalApicLib.h , BaseXApicLib.c
  • GetApicMsiAddress() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicMsiValue() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerCurrentCount() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerInitCount() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerInterruptState() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicTimerState() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApicVersion() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetApLoopMode() : MpLib.c
  • GetApState() : MpLib.c
  • GetAttributesFromPageEntry() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • GetBistFromHob() : SecBist.c
  • GetBistInfoFromPpi() : CpuBist.c , SecBist.c
  • GetCommunicationContext() : PiSmmCommunicationPei.c
  • GetConfigurationPcd() : CpuFeaturesInitialize.c
  • GetCpuFeaturesData() : DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h
  • GetCpuIndex() : SmmProfile.c , SmmProfile.h
  • GetCpuMpData() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • GetCpuMpDataFromGuidedHob() : MpLib.c , MpLib.h
  • GetCurrentMicrocodeSignature() : Microcode.c
  • GetCurrentPagingContext() : CpuPageTable.c
  • GetExceptionHandlerData() : PeiCpuException.c
  • GetExceptionNameStr() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • GetFirmwareVariableMtrrCount() : MtrrLib.h , MtrrLib.c
  • GetFirmwareVariableMtrrCountWorker() : MtrrLib.c
  • GetGcdMemoryMap() : SmmCpuMemoryManagement.c
  • GetGdtr() : CpuMp.c , CpuMpPei.c
  • GetInitialApicId() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetLocalApicBaseAddress() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetMaxMemoryPage() : CpuPaging.c
  • GetMemorySpaceAttributeFromMtrrType() : CpuDxe.c
  • GetModeTransitionBuffer() : DxeMpLib.c , MpLib.h , PeiMpLib.c
  • GetMonitorState() : SmmStm.c , SmmStm.h
  • GetMpPpi() : PeiRegisterCpuFeaturesLib.c
  • GetMpProtocol() : DxeRegisterCpuFeaturesLib.c
  • GetNextWaitingProcessorNumber() : MpLib.c
  • GetNumberOfProcessor() : DxeRegisterCpuFeaturesLib.c , PeiRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h
  • GetNumberOfProcessors() : CpuMp.h , CpuMp.c
  • GetPageTableBase() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • GetPageTableEntry() : CpuPaging.c , SmmCpuMemoryManagement.c , CpuPageTable.c
  • GetPageTableTopLevelType() : CpuPaging.c
  • GetPerformanceCounter() : X86TimerLib.c
  • GetPerformanceCounterProperties() : X86TimerLib.c
  • GetPhysicalAddressWidth() : CpuPaging.c
  • GetPiResource() : SmmStm.c , SmmStm.h
  • GetPlatformPageTableAttribute() : SmmCpuPlatformHookLibNull.c , SmmCpuPlatformHookLib.h
  • GetProcessorIndex() : DxeRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h , PeiRegisterCpuFeaturesLib.c
  • GetProcessorInfo() : CpuMp.c , CpuMp.h
  • GetProcessorInformation() : DxeRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h , PeiRegisterCpuFeaturesLib.c
  • GetProcessorLocationByApicId() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • GetProcessorNumber() : MpLib.c
  • GetProtectedModeCS() : DxeMpLib.c , SmmFuncsArch.c
  • GetRegisterIndex() : SmramSaveState.c
  • GetResourceSize() : SmmStm.c
  • GetSmiCommandPort() : SmmProfile.c
  • GetSmiHandlerSize() : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • GetSmramInfoByHob() : PiSmmCommunicationSmm.c
  • GetSmramInfoByProtocol() : PiSmmCommunicationSmm.c
  • GetSourceFromDestinationOnBts() : SmmProfile.c
  • GetStackBase() : CpuPaging.c
  • GetStmResource() : SmmStm.c , SmmStm.h
  • GetSubEntriesNum() : PageTbl.c
  • GetSupportPcd() : CpuFeaturesInitialize.c
  • GetTimeInNanoSecond() : X86TimerLib.c
  • GetUefiMemoryAttributesTable() : SmmCpuMemoryManagement.c
  • GetUefiMemoryMap() : SmmCpuMemoryManagement.c , PiSmmCpuDxeSmm.h
  • GetVariableMtrrCount() : MtrrLib.c , MtrrLib.h
  • GetVariableMtrrCountWorker() : MtrrLib.c
  • GetVmcsSize() : SmmStm.c
  • GetWakeupBuffer() : PeiMpLib.c , DxeMpLib.c , MpLib.h
  • GuardPagePFHandler() : SmmProfile.c , SmmProfile.h
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AmdUefiCpuPkg: Globals

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- h -

  • HandleSingleResource() : SmmStm.c
  • HookReturnFromSmm() : SmramSaveState.c , PiSmmCpuDxeSmm.h
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AmdUefiCpuPkg: Globals

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- i -

  • IdleLoopEventCallback() : CpuDxe.c
  • InitCommunicationContext() : PiSmmCommunicationPei.c
  • InitGdt() : PiSmmCpuDxeSmm.h , SmmFuncsArch.c
  • InitGlobalDescriptorTable() : CpuDxe.h , CpuGdt.c
  • InitializeAp() : CpuS3.c
  • InitializeApData() : MpLib.c
  • InitializeApicTimer() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • InitializeCpu() : CpuDxe.c
  • InitializeCpuAfterRebase() : CpuS3.c
  • InitializeCpuBeforeRebase() : CpuS3.c
  • InitializeCpuExceptionHandlers() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • InitializeCpuExceptionHandlersEx() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • InitializeCpuExceptionHandlersWorker() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
  • InitializeCpuInterruptHandlers() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • InitializeCpuMpWorker() : CpuMpPei.c , CpuMpPei.h
  • InitializeExceptionStackSwitchHandlers() : CpuMp.c , CpuMpPei.c
  • InitializeFloatingPointUnits() : UefiCpuLib.h
  • InitializeIDTSmmStackGuard() : SmmFuncsArch.c , PiSmmCpuDxeSmm.h , SmmFuncsArch.c
  • InitializeLocalApicSoftwareEnable() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • InitializeMpExceptionHandlers() : CpuMp.c
  • InitializeMpExceptionStackSwitchHandlers() : CpuMp.c , CpuMpPei.c
  • InitializeMpServiceData() : MpService.c , PiSmmCpuDxeSmm.h
  • InitializeMpSupport() : CpuMp.c , CpuMp.h
  • InitializeMpSyncData() : MpService.c , PiSmmCpuDxeSmm.h
  • InitializeMtrrMask() : CpuDxe.c
  • InitializePageTableLib() : CpuPageTable.h
  • InitializePageTablePool() : CpuPageTable.c
  • InitializeSmmCpuSemaphores() : MpService.c
  • InitializeSmmCpuServices() : CpuService.c , CpuService.h
  • InitializeSmmIdt() : PiSmmCpuDxeSmm.c
  • InitializeSmmTimer() : PiSmmCpuDxeSmm.h , SyncTimer.c
  • InitIdtr() : SmmProfile.c , SmmProfileInternal.h
  • InitInterruptDescriptorTable() : CpuDxe.c
  • InitMpGlobalData() : PeiMpLib.c , DxeMpLib.c , MpLib.h
  • InitMsrSpinLockByIndex() : PiSmmCpuDxeSmm.h
  • InitPagesForPFHandler() : SmmProfileArch.c , SmmProfileArch.h , SmmProfileArch.c , SmmProfileArch.h
  • InitPaging() : SmmProfile.c , SmmProfile.h
  • InitProtectedMemRange() : SmmProfile.c
  • InitSmmProfile() : SmmProfile.c , SmmProfile.h
  • InitSmmProfileCallBack() : SmmProfile.c
  • InitSmmProfileInternal() : SmmProfile.c
  • InitSmmS3Cr3() : SmmProfileArch.c , SmmProfileArch.h , SmmProfileArch.c
  • InitSmmS3ResumeState() : PiSmmCommunicationSmm.c , CpuS3.c , PiSmmCpuDxeSmm.h
  • InsertToAfterEntry() : RegisterCpuFeaturesLib.c
  • InsertToBeforeEntry() : RegisterCpuFeaturesLib.c
  • InstallSmiHandler() : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • InternalPrintMessage() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • InternalSmmStartupThisAp() : MpService.c
  • InternalSmstGetVendorTableByGuid() : PiSmmCommunicationPei.c
  • InternalX86Delay() : X86TimerLib.c
  • InternalX86GetTimerFrequency() : X86TimerLib.c
  • IntersectMemoryDescriptor() : CpuDxe.c
  • Is1GPageSupport() : PageTbl.c
  • IsAddressSplit() : SmmProfile.c , SmmProfileInternal.h
  • IsAddressValid() : SmmProfileInternal.h , SmmProfile.c
  • IsBitMaskMatch() : CpuFeaturesInitialize.c
  • IsBitMaskMatchCheck() : RegisterCpuFeaturesLib.c
  • IsBspExecuteDisableEnabled() : MpLib.c
  • IsCpuFeatureCapability() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • IsCpuFeatureInSetting() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • IsCpuFeatureMatch() : RegisterCpuFeaturesLib.c
  • IsCpuFeatureSetInCpuPcd() : RegisterCpuFeaturesLib.c
  • IsCpuFeatureSupported() : RegisterCpuFeaturesLib.c , RegisterCpuFeaturesLib.h
  • IsCpuFeatureUserConfiguration() : RegisterCpuFeaturesLib.h , RegisterCpuFeaturesLib.c
  • IsExecuteDisableEnabled() : CpuPageTable.c
  • IsIa32PaeSupported() : CpuPaging.c
  • IsInSmm() : CpuPageTable.c
  • IsInSmmRanges() : SmmProfile.c
  • IsLmceOsEnabled() : MpService.c
  • IsLmceSignaled() : MpService.c
  • IsLongModeWakingVector() : S3Resume.c
  • IsMtrrSupported() : MtrrLib.h , MtrrLib.c
  • IsMwaitSupport() : MpLib.h , MpLib.c
  • IsPagingAndPageAddressExtensionsEnabled() : CpuDxe.c
  • IsReadOnlyPageWriteProtected() : CpuPageTable.c
  • IsSmmCommBufferForbiddenAddress() : SmmCpuMemoryManagement.c , PiSmmCpuDxeSmm.h
  • IsSyncTimerTimeout() : PiSmmCpuDxeSmm.h , SyncTimer.c
  • IsUefiPageNotPresent() : SmmCpuMemoryManagement.c
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AmdUefiCpuPkg: Globals

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- l -

  • LibReleaseSemaphore() : CpuFeaturesInitialize.c
  • LibWaitForSemaphore() : CpuFeaturesInitialize.c
  • LimitCpuidMaxvalInitialize() : LimitCpuIdMaxval.c , CpuCommonFeatures.h
  • LimitCpuidMaxvalSupport() : CpuCommonFeatures.h , LimitCpuIdMaxval.c
  • LmceInitialize() : MachineCheck.c , CpuCommonFeatures.h
  • LmceSupport() : CpuCommonFeatures.h , MachineCheck.c
  • LoadMonitor() : SmmStm.c , SmmStm.h
  • LoadMtrrData() : CpuS3.c
  • LocalApicBaseAddressMsrSupported() : BaseXApicX2ApicLib.c , BaseXApicLib.c
  • LockdownSemaphore() : MpService.c
  • LockFeatureControlRegisterInitialize() : FeatureControl.c , CpuCommonFeatures.h
  • LockFeatureControlRegisterSupport() : FeatureControl.c , CpuCommonFeatures.h
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AmdUefiCpuPkg: Globals

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  • McaInitialize() : CpuCommonFeatures.h , MachineCheck.c
  • McaSupport() : MachineCheck.c , CpuCommonFeatures.h
  • MceInitialize() : CpuCommonFeatures.h , MachineCheck.c
  • MceSupport() : MachineCheck.c , CpuCommonFeatures.h
  • McgCtlInitialize() : CpuCommonFeatures.h , MachineCheck.c
  • McgCtlSupport() : CpuCommonFeatures.h , MachineCheck.c
  • MemoryDiscoveredPpiNotifyCallback() : CpuMpPei.h , CpuPaging.c
  • MergeMemoryMapForNotPresentEntry() : SmmCpuMemoryManagement.c
  • MicrocodeDetect() : Microcode.c , MpLib.h
  • MicroSecondDelay() : X86TimerLib.c
  • MonitorMwaitInitialize() : CpuCommonFeatures.h , MonitorMwait.c
  • MonitorMwaitSupport() : CpuCommonFeatures.h , MonitorMwait.c
  • MpInitChangeApLoopCallback() : DxeMpLib.c
  • MpInitLibEnableDisableAP() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibGetNumberOfProcessors() : MpInitLib.h , MpLib.c
  • MpInitLibGetProcessorInfo() : MpInitLib.h , MpLib.c
  • MpInitLibInitialize() : MpLib.c , MpInitLib.h
  • MpInitLibStartupAllAPs() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibStartupThisAP() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibSwitchBSP() : MpInitLib.h , DxeMpLib.c , PeiMpLib.c
  • MpInitLibWhoAmI() : MpInitLib.h , MpLib.c
  • MtrrDebugPrintAllMtrrs() : MtrrLib.h , MtrrLib.c
  • MtrrDebugPrintAllMtrrsWorker() : MtrrLib.c
  • MtrrGetAllMtrrs() : MtrrLib.h , MtrrLib.c
  • MtrrGetDefaultMemoryType() : MtrrLib.h , MtrrLib.c
  • MtrrGetDefaultMemoryTypeWorker() : MtrrLib.c
  • MtrrGetFixedMtrr() : MtrrLib.h , MtrrLib.c
  • MtrrGetFixedMtrrWorker() : MtrrLib.c
  • MtrrGetMemoryAttribute() : MtrrLib.h , MtrrLib.c
  • MtrrGetMemoryAttributeByAddressWorker() : MtrrLib.c
  • MtrrGetMemoryAttributeInVariableMtrr() : MtrrLib.c , MtrrLib.h
  • MtrrGetMemoryAttributeInVariableMtrrWorker() : MtrrLib.c
  • MtrrGetVariableMtrr() : MtrrLib.h , MtrrLib.c
  • MtrrGetVariableMtrrWorker() : MtrrLib.c
  • MtrrLibAppendVariableMtrr() : MtrrLib.c
  • MtrrLibApplyFixedMtrrs() : MtrrLib.c
  • MtrrLibApplyVariableMtrrs() : MtrrLib.c
  • MtrrLibBiggestAlignment() : MtrrLib.c
  • MtrrLibCalculateLeastMtrrs() : MtrrLib.c
  • MtrrLibCalculateMtrrs() : MtrrLib.c
  • MtrrLibCalculateSubtractivePath() : MtrrLib.c
  • MtrrLibGetCompatibleTypes() : MtrrLib.c
  • MtrrLibGetNumberOfTypes() : MtrrLib.c
  • MtrrLibGetRawVariableRanges() : MtrrLib.c
  • MtrrLibInitializeMtrrMask() : MtrrLib.c
  • MtrrLibIsPowerOfTwo() : MtrrLib.c
  • MtrrLibLowestType() : MtrrLib.c
  • MtrrLibMergeVariableMtrr() : MtrrLib.c
  • MtrrLibPostMtrrChange() : MtrrLib.c
  • MtrrLibPostMtrrChangeEnableCache() : MtrrLib.c
  • MtrrLibPrecedence() : MtrrLib.c
  • MtrrLibPreMtrrChange() : MtrrLib.c
  • MtrrLibProgramFixedMtrr() : MtrrLib.c
  • MtrrLibSetBelow1MBMemoryAttribute() : MtrrLib.c
  • MtrrLibSetMemoryRanges() : MtrrLib.c
  • MtrrLibSetMemoryType() : MtrrLib.c
  • MtrrLibTypeLeftPrecedeRight() : MtrrLib.c
  • MtrrSetAllMtrrs() : MtrrLib.c , MtrrLib.h
  • MtrrSetFixedMtrr() : MtrrLib.c , MtrrLib.h
  • MtrrSetFixedMtrrWorker() : MtrrLib.c
  • MtrrSetMemoryAttribute() : MtrrLib.h , MtrrLib.c
  • MtrrSetMemoryAttributeInMtrrSettings() : MtrrLib.h , MtrrLib.c
  • MtrrSetMemoryAttributesInMtrrSettings() : MtrrLib.h , MtrrLib.c
  • MtrrSetVariableMtrr() : MtrrLib.c , MtrrLib.h
  • MtrrSetVariableMtrrWorker() : MtrrLib.c
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AmdUefiCpuPkg: Globals

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  • NanoSecondDelay() : X86TimerLib.c
  • NeedSplitPage() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • NotifyOnS3SmmInitDonePpi() : PeiMpLib.c
  • NotifyStmResourceChange() : SmmStm.c , SmmStm.h
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  • PageAttributeToLength() : CpuPageTable.c , SmmCpuMemoryManagement.c
  • PageAttributeToMask() : SmmCpuMemoryManagement.c , CpuPageTable.c
  • PageFaultExceptionHandler() : CpuDxe.h , CpuPageTable.c
  • PageFaultIdtHandlerSmmProfile() : SmmProfile.h
  • PatchGdtIdtMap() : SmmCpuMemoryManagement.c
  • PatchSmmSaveStateMap() : SmmCpuMemoryManagement.c
  • PeiEnableDisableAP() : CpuMpPei.c , CpuMpPei.h
  • PeiGetNumberOfProcessors() : CpuMpPei.c , CpuMpPei.h
  • PeiGetProcessorInfo() : CpuMpPei.c , CpuMpPei.h
  • PeimS3ResumeEntryPoint() : S3Resume.c
  • PeiStartupAllAPs() : CpuMpPei.c , CpuMpPei.h
  • PeiStartupThisAP() : CpuMpPei.c , CpuMpPei.h
  • PeiSwitchBSP() : CpuMpPei.c , CpuMpPei.h
  • PeiWhoAmI() : CpuMpPei.c , CpuMpPei.h
  • PendingBreakInitialize() : CpuCommonFeatures.h , PendingBreak.c
  • PendingBreakSupport() : CpuCommonFeatures.h , PendingBreak.c
  • PerformPreTasks() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • PerformRemainingTasks() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • PiCpuSmmEntry() : PiSmmCpuDxeSmm.c
  • PiSmmCommunicationHandler() : PiSmmCommunicationSmm.c
  • PiSmmCommunicationPeiEntryPoint() : PiSmmCommunicationPei.c
  • PiSmmCommunicationSmmEntryPoint() : PiSmmCommunicationSmm.c
  • PiSmmCpuSmiEntryFixupAddress() : PiSmmCpuDxeSmm.h
  • PiSmmCpuSmmInitFixupAddress() : PiSmmCpuDxeSmm.h
  • PlatformSmmBspElection() : SmmCpuPlatformHookLibNull.c , SmmCpuPlatformHookLib.h
  • PlatformValidSmi() : SmmCpuPlatformHookLib.h , SmmCpuPlatformHookLibNull.c
  • PpinInitialize() : Ppin.c , CpuCommonFeatures.h
  • PpinSupport() : CpuCommonFeatures.h , Ppin.c
  • PrepareApStartupVector() : CpuS3.c
  • PreSmmCpuRegisterTableWrite() : RegisterCpuFeaturesLib.h , RegisterCpuFeaturesLib.c
  • ProcessLibraryConstructorList() : SecMain.h
  • ProcTraceGetConfigData() : ProcTrace.c , CpuCommonFeatures.h
  • ProcTraceInitialize() : ProcTrace.c , CpuCommonFeatures.h
  • ProcTraceSupport() : CpuCommonFeatures.h , ProcTrace.c
  • ProgramProcessorRegister() : CpuS3.c , CpuFeaturesInitialize.c
  • ProgramVirtualWireMode() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
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AmdUefiCpuPkg: Globals

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- r -

  • ReadAndVerifyVectorInfo() : CpuExceptionCommon.c , CpuExceptionCommon.h
  • ReadLocalApicReg() : BaseXApicX2ApicLib.c , DxeMpLib.c , BaseXApicLib.c
  • ReadSaveStateRegister() : PiSmmCpuDxeSmm.h , SmramSaveState.c
  • ReadSaveStateRegisterByIndex() : SmramSaveState.c
  • ReclaimPages() : PageTbl.c
  • RefreshGcdMemoryAttributes() : CpuDxe.c
  • RefreshGcdMemoryAttributesFromPaging() : CpuDxe.h , CpuPageTable.c
  • RefreshMemoryAttributesFromMtrr() : CpuDxe.c
  • RegisterCpuFeature() : RegisterCpuFeaturesLib.h , RegisterCpuFeaturesLib.c
  • RegisterCpuFeatureWorker() : RegisterCpuFeaturesLib.c
  • RegisterCpuInterruptHandler() : DxeException.c , PeiCpuException.c , SecPeiCpuException.c , SmmException.c
  • RegisterCpuInterruptHandlerWorker() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
  • RegisterSmmEntry() : MpService.c , PiSmmCpuDxeSmm.h
  • ReleaseAllAPs() : MpService.c
  • ReleaseSemaphore() : MpService.c
  • RelocateApLoop() : DxeMpLib.c
  • ReplaceOSMtrrs() : MpService.c
  • RepublishSecPlatformInformationPpi() : SecMain.h , SecBist.c
  • ResetProcessorToIdleState() : MpLib.c
  • RestorePageTableAbove4G() : SmmProfileArch.c , SmmProfileArch.h
  • RestorePageTableBelow4G() : SmmProfile.c
  • RestoreS3PageTables() : S3Resume.c
  • RestoreSmmConfigurationInS3() : CpuS3.c , PiSmmCpuDxeSmm.h
  • RestoreVolatileRegisters() : MpLib.c
  • RestoreWakeupBuffer() : MpLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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- s -

  • S3ReleaseSemaphore() : CpuS3.c
  • S3RestoreConfig2() : S3Resume.c
  • S3ResumeBootOs() : S3Resume.c
  • S3ResumeExecuteBootScript() : S3Resume.c
  • S3WaitForSemaphore() : CpuS3.c
  • SaveCpuMpData() : PeiMpLib.c , DxeMpLib.c , MpLib.h
  • SaveLocalApicTimerSetting() : MpLib.c
  • SaveVolatileRegisters() : MpLib.c
  • SearchGcdMemorySpaces() : CpuDxe.c
  • SecPerformancePpiCallBack() : SecMain.c , SecMain.h
  • SecPlatformDisableTemporaryMemory() : PlatformSecLib.h , PlatformSecLibNull.c
  • SecPlatformInformation() : PlatformSecLib.h , PlatformSecLibNull.c
  • SecPlatformInformation2() : CpuBist.c , CpuMpPei.h
  • SecPlatformInformation2Bist() : SecBist.c , SecMain.h
  • SecPlatformInformationBist() : SecBist.c , SecMain.h
  • SecPlatformMain() : PlatformSecLib.h , PlatformSecLibNull.c
  • SecStartup() : SecMain.c , SecMain.h
  • SecStartupPhase2() : SecMain.c
  • SecTemporaryRamDone() : SecMain.c , SecMain.h
  • SemaphoreHook() : PiSmmCpuDxeSmm.h , Semaphore.c
  • SendApicEoi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendFixedIpi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendFixedIpiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitIpi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitIpiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitSipiSipi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendInitSipiSipiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendIpi() : BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendSmiIpi() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SendSmiIpiAllExcludingSelf() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SetAccNum() : PageTbl.c
  • SetApicMode() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SetApState() : MpLib.c
  • SetCapabilityPcd() : CpuFeaturesInitialize.c
  • SetCodeSelector() : CpuDxe.h
  • SetCommunicationContext() : PiSmmCommunicationPei.c , PiSmmCommunicationSmm.c
  • SetCpuFeaturesBitMask() : RegisterCpuFeaturesLib.c
  • SetDataSelectors() : CpuDxe.h
  • SetExceptionHandlerData() : PeiCpuException.c
  • SetGcdMemorySpaceAttributes() : CpuDxe.c
  • SetLocalApicBaseAddress() : LocalApicLib.h , BaseXApicLib.c , BaseXApicX2ApicLib.c
  • SetMemMapAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SetMtrrsFromBuffer() : CpuDxe.c
  • SetPageTableAttributes() : PageTbl.c , PiSmmCpuDxeSmm.h , PageTbl.c
  • SetProcessorRegister() : CpuFeaturesInitialize.c , RegisterCpuFeatures.h
  • SetRegister() : CpuS3.c
  • SetSettingPcd() : CpuFeaturesInitialize.c
  • SetStaticPageTable() : PageTbl.c
  • SetSubEntriesNum() : PageTbl.c
  • SetUefiMemMapAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SetupStackGuardPage() : CpuPaging.c
  • SignalToSmmByCommunication() : S3Resume.c
  • SmiDefaultPFHandler() : PageTbl.c , SmmProfileInternal.h , PageTbl.c
  • SmiPFHandler() : PageTbl.c , PiSmmCpuDxeSmm.h , PageTbl.c
  • SmiRendezvous() : MpService.c
  • SmmAddProcessor() : CpuService.c , CpuService.h
  • SmmBlockingStartupThisAp() : MpService.c , PiSmmCpuDxeSmm.h
  • SmmClearMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmClearMemoryAttributesEx() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmConfigurationEventNotify() : CpuFeaturesDxe.c
  • SmmCpuFeaturesAllocatePageTableMemory() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesCompleteSmmReadyToLock() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesDisableSmrr() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesGetSmiHandlerSize() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLibNoStm.c , SmmStm.c
  • SmmCpuFeaturesGetSmmRegister() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesHookReturnFromSmm() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesInitializeProcessor() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesInstallSmiHandler() : SmmStm.c , SmmCpuFeaturesLibNoStm.c , SmmCpuFeaturesLib.h
  • SmmCpuFeaturesIsSmmRegisterSupported() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesLibConstructor() : SmmCpuFeaturesLib.c , SmmStm.c
  • SmmCpuFeaturesLibStmConstructor() : SmmStm.c
  • SmmCpuFeaturesLibStmSmiEntryFixupAddress() : SmmStm.h
  • SmmCpuFeaturesNeedConfigureMtrrs() : SmmCpuFeaturesLib.c , SmmCpuFeaturesLib.h
  • SmmCpuFeaturesReadSaveStateRegister() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesReenableSmrr() : SmmCpuFeaturesLib.c , SmmCpuFeaturesLib.h
  • SmmCpuFeaturesRendezvousEntry() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesRendezvousExit() : SmmCpuFeaturesLib.c , SmmCpuFeaturesLib.h
  • SmmCpuFeaturesSetSmmRegister() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesSmmRelocationComplete() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuFeaturesWriteSaveStateRegister() : SmmCpuFeaturesLib.h , SmmCpuFeaturesLib.c
  • SmmCpuIo2Initialize() : CpuIo2Smm.c
  • SmmCpuUpdate() : CpuService.c , CpuService.h
  • SmmEndOfDxeEventNotify() : SmmStm.c
  • SmmGetProcessorInfo() : CpuService.h , CpuService.c
  • SmmGetSystemConfigurationTable() : SmmCpuMemoryManagement.c
  • SmmInitHandler() : PiSmmCpuDxeSmm.c
  • SmmInitPageTable() : PiSmmCpuDxeSmm.h , PageTbl.c
  • SmmProfilePFHandler() : SmmProfile.h , SmmProfile.c
  • SmmProfileRecordSmiNum() : SmmProfile.h , SmmProfile.c
  • SmmProfileStart() : SmmProfile.h , SmmProfile.c
  • SmmReadSaveState() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • SmmReadyToLockEventNotify() : PiSmmCpuDxeSmm.c
  • SmmRegisterExceptionHandler() : CpuService.c , CpuService.h
  • SmmRelocateBases() : PiSmmCpuDxeSmm.h , PiSmmCpuDxeSmm.c
  • SmmRelocationSemaphoreComplete() : PiSmmCpuDxeSmm.h
  • SmmRelocationSemaphoreComplete32() : Semaphore.c
  • SmmRemoveProcessor() : CpuService.h , CpuService.c
  • SmmRestoreCpu() : CpuS3.c
  • SmmSetMemoryAttributes() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmSetMemoryAttributesEx() : PiSmmCpuDxeSmm.h , SmmCpuMemoryManagement.c
  • SmmStartupThisAp() : MpService.c , PiSmmCpuDxeSmm.h
  • SmmStmExceptionHandler() : SmmStmSupport.c , SmmStm.h
  • SmmStmSetup() : SmmStm.c
  • SmmStmTeardown() : SmmStm.c
  • SmmSwitchBsp() : CpuService.h , CpuService.c
  • SmmWaitForApArrival() : MpService.c
  • SmmWhoAmI() : CpuService.c , CpuService.h
  • SmmWriteSaveState() : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • SmxInitialize() : CpuCommonFeatures.h , FeatureControl.c
  • SmxSupport() : CpuCommonFeatures.h , FeatureControl.c
  • SortApicId() : MpLib.c
  • SortMemoryMap() : SmmCpuMemoryManagement.c
  • SplitPage() : SmmCpuMemoryManagement.c , CpuPaging.c , CpuPageTable.c
  • StandardSignatureIsAuthenticAMD() : BaseXApicLib.c , BaseXApicX2ApicLib.c
  • StartSyncTimer() : PiSmmCpuDxeSmm.h , SyncTimer.c
  • StartupAllAPs() : CpuMp.h , CpuMp.c
  • StartupAllAPsWorker() : MpLib.c , MpLib.h
  • StartupAPsWorker() : PeiRegisterCpuFeaturesLib.c , DxeRegisterCpuFeaturesLib.c , RegisterCpuFeatures.h
  • StartupThisAP() : CpuMp.c , CpuMp.h
  • StartupThisAPWorker() : MpLib.c , MpLib.h
  • StmCheckStmImage() : SmmStm.c
  • StmGen4GPageTable() : SmmStmSupport.c , SmmStm.h
  • StmLoadStmImage() : SmmStm.c
  • StmSmmConfigurationTableInit() : SmmStm.c , SmmStm.h
  • SupportedMaskAnd() : CpuFeaturesInitialize.c
  • SupportedMaskCleanBit() : CpuFeaturesInitialize.c
  • SupportedMaskOr() : CpuFeaturesInitialize.c
  • SwitchBSP() : CpuMp.h , CpuMp.c
  • SwitchBspAfterFeaturesInitialize() : RegisterCpuFeaturesLib.h , RegisterCpuFeaturesLib.c
  • SwitchBSPWorker() : MpLib.h , MpLib.c
  • SwitchNewBsp() : RegisterCpuFeatures.h , PeiRegisterCpuFeaturesLib.c , DxeRegisterCpuFeaturesLib.c
  • SyncLocalApicTimerSetting() : MpLib.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • _
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  • TimedWaitForApFinish() : MpLib.c
  • TransferApToSafeState() : SmmFuncsArch.c , PiSmmCpuDxeSmm.h , SmmFuncsArch.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
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  • _
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- u -

  • UpdateIdtTable() : CpuExceptionCommon.h , PeiDxeSmmCpuException.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
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  • Typedefs
  • Enumerations
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  • _
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- v -

  • ValidateResource() : SmmStm.c
  • VmxInitialize() : CpuCommonFeatures.h , FeatureControl.c
  • VmxSupport() : FeatureControl.c , CpuCommonFeatures.h
  • VOID() : MpLib.h , S3Resume.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
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- w -

  • WaitApWakeup() : MpLib.c
  • WaitForAllAPs() : MpService.c
  • WaitForSemaphore() : MpService.c
  • WakeUpAP() : MpLib.c , MpLib.h
  • WhoAmI() : CpuMp.c , CpuMp.h
  • WriteLocalApicReg() : BaseXApicX2ApicLib.c , DxeMpLib.c , BaseXApicLib.c
  • WriteSaveStateRegister() : SmramSaveState.c , PiSmmCpuDxeSmm.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
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- x -

  • X2ApicGetConfigData() : CpuCommonFeatures.h , X2Apic.c
  • X2ApicInitialize() : X2Apic.c , CpuCommonFeatures.h
  • X2ApicSupport() : X2Apic.c , CpuCommonFeatures.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • gPatchSmbase : SmramSaveState.c
  • mSmmCpu : PiSmmCpuDxeSmm.c , PiSmmCpuDxeSmm.h
  • mSmmCpuHandle : PiSmmCpuDxeSmm.c
  • mSmmCpuIoType : SmramSaveState.c
  • mSmmCpuIoWidth : SmramSaveState.c
  • mSmmCpuRegisterRanges : SmramSaveState.c
  • mSmmCpuWidthOffset : SmramSaveState.c
  • mSmmMemoryAttribute : PiSmmCpuDxeSmm.c
  • mSmmSaveStateRegisterLma : PiSmmCpuDxeSmm.h , SmramSaveState.c
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
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  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • CPU_FEATURE_GET_CONFIG_DATA : RegisterCpuFeaturesLib.h
  • CPU_FEATURE_INITIALIZE : RegisterCpuFeaturesLib.h
  • CPU_FEATURE_SUPPORT : RegisterCpuFeaturesLib.h
  • PAGE_TABLE_LIB_ALLOCATE_PAGES : CpuPageTable.h
  • STM_STATUS : StmStatusCode.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • EVENT_TYPE : StmApi.h
  • RTIT_OUTPUT_SCHEME : ProcTrace.c
  • RTIT_TOPA_MEMORY_SIZE : ArchitecturalMsr.h
  • SMM_PAGE_SIZE_TYPE : SmmCpuPlatformHookLib.h
  • SMM_REG_NAME : SmmCpuFeaturesLib.h
  • STM_REGISTER_VIOLATION_TYPE : StmResourceDescriptor.h
  • TXT_SMM_PROTECTION_EXCEPTION_TYPE : StmApi.h
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AmdUefiCpuPkg: Globals

  • File List
  • Globals
  • All
  • Functions
  • Variables
  • Typedefs
  • Enumerations
  • Enumerator
  • EvtBiosAccessToUnclaimedResource : StmApi.h
  • EvtInvalid : StmApi.h
  • EvtMleMax : StmApi.h
  • SmmRegFeatureControl : SmmCpuFeaturesLib.h
  • SmmRegSmmBlocked : SmmCpuFeaturesLib.h
  • SmmRegSmmDelayed : SmmCpuFeaturesLib.h
  • SmmRegSmmEnable : SmmCpuFeaturesLib.h
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


Copyright

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AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/X64 Directory Reference

  • UefiCpuPkg
  • CpuDxe
  • X64
X64 Directory Reference

Files

file CpuAsm.nasm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/X64 Directory Reference

  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • X64
X64 Directory Reference

Files

file PageTables.asm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: F:/DoxyStartFiles Directory Reference

  • DoxyStartFiles
DoxyStartFiles Directory Reference

Files

file DoxyDefault.Dox
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Ia16 Directory Reference

  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Ia16
Ia16 Directory Reference

Files

file | Init16.asm
file | Real16ToFlat32.asm
file | ResetVectorVtf0.asm
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AmdUefiCpuPkg: UefiCpuPkg/Library/BaseUefiCpuLib/Ia32 Directory Reference

  • UefiCpuPkg
  • Library
  • BaseUefiCpuLib
  • Ia32
Ia32 Directory Reference

Files

file | InitializeFpu.nasm
file | InitializeFpu.S
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/UefiCpuSetup Directory Reference

  • UefiCpuPkg
  • UefiCpuSetup
UefiCpuSetup Directory Reference

Files

file | UefiCpuSetup.sd
file | UefiCpuSetup.sdl
file | UefiCpuSetup.uni
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32 Directory Reference

  • UefiCpuPkg
  • Universal
  • Acpi
  • S3Resume2Pei
  • Ia32
Ia32 Directory Reference

Files

file AsmFuncs.nasm
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AmdUefiCpuPkg: UefiCpuPkg/SecCore/Ia32 Directory Reference

  • UefiCpuPkg
  • SecCore
  • Ia32
Ia32 Directory Reference

Files

file ResetVec.nasmb
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AmdUefiCpuPkg: UefiCpuPkg/Library/BaseUefiCpuLib/X64 Directory Reference

  • UefiCpuPkg
  • Library
  • BaseUefiCpuLib
  • X64
X64 Directory Reference

Files

file | InitializeFpu.nasm
file | InitializeFpu.S
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/Ia32 Directory Reference

  • UefiCpuPkg
  • Library
  • MpInitLib
  • Ia32
Ia32 Directory Reference

Files

file | MpEqu.inc
file | MpFuncs.nasm
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AmdUefiCpuPkg: UefiCpuPkg/ResetVector/Vtf0/Ia32 Directory Reference

  • UefiCpuPkg
  • ResetVector
  • Vtf0
  • Ia32
Ia32 Directory Reference

Files

file | Flat32ToFlat64.asm
file | PageTables64.asm
file | SearchForBfvBase.asm
file | SearchForSecEntry.asm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64 Directory Reference

  • UefiCpuPkg
  • Universal
  • Acpi
  • S3Resume2Pei
  • X64
X64 Directory Reference

Files

file AsmFuncs.nasm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/CpuDxe/Ia32 Directory Reference

  • UefiCpuPkg
  • CpuDxe
  • Ia32
Ia32 Directory Reference

Files

file CpuAsm.nasm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: UefiCpuPkg/Library/MpInitLib/X64 Directory Reference

  • UefiCpuPkg
  • Library
  • MpInitLib
  • X64
X64 Directory Reference

Files

file | MpEqu.inc
file | MpFuncs.nasm
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


AmdUefiCpuPkg: Main Page

AmdUefiCpuPkg Documentation
Main Page

Release Notes

Copyright
Generated on Tue Sep 1 2020 14:37:10 for AmdUefiCpuPkg by doxygen 1.8.6


Release Notes - NDA Required

Component Information:
Component Title: AmdUefiCpuPkg
Component Reference Name: AmdUefiCpuPkg
Component Type: eModule
Release Date: 2020-09-01
Source Control Label: AmdUefiCpuPkg_04
Source Control Location: SS: AptioV;$/AptioV/Source/Hardware/Chipset/AMD/AmdUefiCpuPkg;
Dependencies
Component Dependencies
N0NE

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Incompatible with IA32FamilyCpuPkg
Origin: TianoCore.org, Tag edk2-stable201811, commit 85588389222a3636baf0f9ed8227f2434af4c3f9
UefiCpuPkg is upgraded to align with TianoCore.org revision 8558838922 created 2018-11-14
NOTE: This version UefiCpuPkg is incompatible with IA32FamilyCpuPkg
New features :
None.
AMI Build Tools:
Tools Label: BuildTools_35, Dated: 2019-07-04
Visual eBios: RSS:7.22.0720 , Dated: 2019-07-04
Compiler Tool(s): EnterpriseWDK_rs2_release_15063_20170317-1834
New features added in this label:
[TAG] EIP 534380
[Category] IMPROVEMENT
[Description] SMM isolation implementation.
[Files] SmmCpuFeaturesLib.c, SmiException.nasm, SmiRendezvous.nasm, MpService.c, PiSmmCpuDxeSmm.c, PiSmmCpuDxeSmm.h, PiSmmCpuDxeSmm.inf, SmramSaveState.c, UefiCpuSetup.cif, UefiCpuSetup.sd, UefiCpuSetup.sdl, UefiCpuSetup.uni, AmdUefiCpuPkg.cif, UefiCpuPkg.dec, UefiCpuPkg,sdl.
General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
None
Files Changed for General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
EIP 534380: SmmCpuFeaturesLib.c, SmiException.nasm, SmiRendezvous.nasm, MpService.c, PiSmmCpuDxeSmm.c, PiSmmCpuDxeSmm.h, PiSmmCpuDxeSmm.inf, SmramSaveState.c, UefiCpuSetup.cif, UefiCpuSetup.sd, UefiCpuSetup.sdl, UefiCpuSetup.uni, AmdUefiCpuPkg.cif, UefiCpuPkg.dec, UefiCpuPkg,sdl.
EIP 542508: BaseXApicX2ApicLib.c and DxeMpLib.c.
EIP 502692: BaseXApicX2ApicLib.c.
EIP 501722: DxeMpLib.c.
Known Limitations and Erratas in this label:
None
Remaining Issues:
NONE
Unit Testing:
Module tested on CRBs: Myrtle.
Release History:
AmdUefiCpuPkg_03
AmdUefiCpuPkg_02
AmdUefiCpuPkg_01

© American Megatrends International LLC.


Release Notes - NDA Required

Component Information:
Component Title: AmdUefiCpuPkg
Component Reference Name: AmdUefiCpuPkg
Component Type: eModule
Release Date: 2019-08-07
Source Control Label: AmdUefiCpuPkg_01
Source Control Location: SS: AptioV;$/AptioV/Source/Hardware/Chipset/AMD/AmdUefiCpuPkg;
Dependencies
Component Dependencies
N0NE

File Dependencies
N0NE

Protocol Dependencies
ONE
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Incompatible with IA32FamilyCpuPkg
Origin: TianoCore.org, Tag edk2-stable201811, commit 85588389222a3636baf0f9ed8227f2434af4c3f9
UefiCpuPkg is upgraded to align with TianoCore.org revision 8558838922 created 2018-11-14
NOTE: This version UefiCpuPkg is incompatible with IA32FamilyCpuPkg
New features :
None.
AMI Build Tools:
Tools Label: BuildTools_35, Dated: 2019-07-04
Visual eBios: RSS:7.22.0720 , Dated: 2019-07-04
Compiler Tool(s): EnterpriseWDK_rs2_release_15063_20170317-1834
New features added in this label:
[TAG] EIP 472275
[Category] IMPROVEMENT
[Description] Replace AmiCpuPkg with UefiCpuPkg.
[Files] UefiCpuPkg files.
General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
None
Files Changed for General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
None.
Known Limitations and Erratas in this label:
None
Remaining Issues:
NONE
Unit Testing:
Module tested on CRBs: Myrtle.
Release History:

© American Megatrends International LLC.


Release Notes - NDA Required

Component Information:
Component Title: AmdUefiCpuPkg
Component Reference Name: AmdUefiCpuPkg
Component Type: eModule
Release Date: 2019-10-23
Source Control Label: AmdUefiCpuPkg_02
Source Control Location: SS: AptioV;$/AptioV/Source/Hardware/Chipset/AMD/AmdUefiCpuPkg;
Dependencies
Component Dependencies
N0NE

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Incompatible with IA32FamilyCpuPkg
Origin: TianoCore.org, Tag edk2-stable201811, commit 85588389222a3636baf0f9ed8227f2434af4c3f9
UefiCpuPkg is upgraded to align with TianoCore.org revision 8558838922 created 2018-11-14
NOTE: This version UefiCpuPkg is incompatible with IA32FamilyCpuPkg
New features :
None.
AMI Build Tools:
Tools Label: BuildTools_35, Dated: 2019-07-04
Visual eBios: RSS:7.22.0720 , Dated: 2019-07-04
Compiler Tool(s): EnterpriseWDK_rs2_release_15063_20170317-1834
New features added in this label:
[TAG] EIP 502692
[Category] IMPROVEMENT
[Description] The ApicSwEn bit should be cleared in AMD system.
[Files] BaseXApicX2ApicLib.c.
General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
[TAG] EIP 501722
[Category] BUG FIX
[Severity] Normal
[Symptom] Some AP functions may allocate the pool that was used for AP reset vector.
[RootCause] The memory pool that used for AP reset vector may get destroyed.
[Solution] The AP reset vector should be reserved for waking AP up.
[Files] DxeMpLib.c.
Files Changed for General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
EIP 502692: BaseXApicX2ApicLib.c.
EIP 501722: DxeMpLib.c.
Known Limitations and Erratas in this label:
None
Remaining Issues:
NONE
Unit Testing:
Module tested on CRBs: Myrtle.
Release History:
AmdUefiCpuPkg_01

© American Megatrends International LLC.


Release Notes - NDA Required

Component Information:
Component Title: AmdUefiCpuPkg
Component Reference Name: AmdUefiCpuPkg
Component Type: eModule
Release Date: 2020-06-05
Source Control Label: AmdUefiCpuPkg_03
Source Control Location: SS: AptioV;$/AptioV/Source/Hardware/Chipset/AMD/AmdUefiCpuPkg;
Dependencies
Component Dependencies
N0NE

File Dependencies
N0NE

Protocol Dependencies
N0NE
Non-Compiled BIN and LIB File(s) within this Component:
N0NE
Component Description:
Incompatible with IA32FamilyCpuPkg
Origin: TianoCore.org, Tag edk2-stable201811, commit 85588389222a3636baf0f9ed8227f2434af4c3f9
UefiCpuPkg is upgraded to align with TianoCore.org revision 8558838922 created 2018-11-14
NOTE: This version UefiCpuPkg is incompatible with IA32FamilyCpuPkg
New features :
None.
AMI Build Tools:
Tools Label: BuildTools_35, Dated: 2019-07-04
Visual eBios: RSS:7.22.0720 , Dated: 2019-07-04
Compiler Tool(s): EnterpriseWDK_rs2_release_15063_20170317-1834
New features added in this label:
None
General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
[TAG] EIP 542508
[Category] BUG FIX
[Severity] Normal
[Symptom] APs can't enter into CC6 mode.
[RootCause] The root cause is that the APICSWEN bit will set every time when AP is woken up, so the best time to clear this bit for good is when AP is being halted in the exit boot services event.
[Solution] Cleared the APICSWEN bit in the exit boot services event.
[Files] BaseXApicX2ApicLib.c and DxeMpLib.c.
Files Changed for General Bug Fixes and EIP Addressed in this Label:

EIP Addressed
EIP 542508: BaseXApicX2ApicLib.c and DxeMpLib.c.
EIP 502692: BaseXApicX2ApicLib.c.
EIP 501722: DxeMpLib.c.
Known Limitations and Erratas in this label:
None
Remaining Issues:
NONE
Unit Testing:
Module tested on CRBs: Myrtle.
Release History:
AmdUefiCpuPkg_02
AmdUefiCpuPkg_01

© American Megatrends International LLC.