142 lines
5.2 KiB
C
142 lines
5.2 KiB
C
//*****************************************************************//
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//*****************************************************************//
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//*****************************************************************//
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//** **//
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//** (C)Copyright 2014, American Megatrends, Inc. **//
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//** **//
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//** All Rights Reserved. **//
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//** **//
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//** 5555 Oakbrook Pkwy, Building 200,Norcross, Georgia 30093 **//
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//** **//
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//** Phone (770)-246-8600 **//
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//** **//
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//*****************************************************************//
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//*****************************************************************//
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//*****************************************************************//
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// $Header: /AptioV/SRC/AMIDebugRxPkg/Include/Library/ser_regs.h 2 2/20/14 5:01p Sudhirv $
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//
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// $Revision: 2 $
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//
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// $Date: 2/20/14 5:01p $
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//*****************************************************************
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//*****************************************************************
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//
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// ser_regs.h
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//
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//
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// Revision History
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// ----------------
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// $Log: /AptioV/SRC/AMIDebugRxPkg/Include/Library/ser_regs.h $
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//
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// 2 2/20/14 5:01p Sudhirv
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// Updated for AMI Debug for UEFI 3.01.0008 INT Label
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//
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// 1 11/02/12 10:07a Sudhirv
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// AMIDebugRxPkg modulepart for AMI Debug for UEFI 3.0
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//
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// 2 8/03/12 6:32p Sudhirv
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// Updated before making binaries.
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//
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// 1 7/15/12 8:12p Sudhirv
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// AMIDebugRx Module for Aptio 5
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//
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//*****************************************************************
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#define RX_BUF_REG 0x00
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#define TX_BUF_REG 0x00
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#define INT_ENB_REG 0x01
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#define INT_ID_REG 0x02
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#define FIFO_CTRL_REG 0x02
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#define LINE_CTRL_REG 0x03
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#define MDM_CTRL_REG 0x04
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#define LINE_STATUS_REG 0x05
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#define MDM_STATUS_REG 0x06
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#define SCRATCH_REG 0x07
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#define DL_LSB_REG 0x00
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#define DL_MSB_REG 0x01
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// Interrupt enable register
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#define INT_ENB_RXRD 0x01
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#define INT_ENB_TBE 0x02
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#define INT_ENB_ERBK 0x04
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#define INT_ENB_SINP 0x08
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// Interrupt identification register
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#define INT_ID_MASK 0x06
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#define INT_ID_SINP 0x00
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#define INT_ID_TBE 0x02
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#define INT_ID_RXRD 0x04
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#define INT_ID_ERBK 0x06
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#define INT_ID_NO_INT_PND 0x01
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// Data format register
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#define DATA_BITS_5 0x00
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#define DATA_BITS_6 0x01
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#define DATA_BITS_7 0x02
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#define DATA_BITS_8 0x03
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#define STOP_BITS_1 0x00
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#define STOP_BITS_2 0x04
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#define NO_PARITY 0x00
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#define ODD_PARITY 0x08
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#define EVEN_PARITY 0x18
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#define MARK_PARITY 0x28
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#define SPACE_PARITY 0x38
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#define BRK_OFF 0x00
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#define BRK_ON 0x40
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#define DLAB_ENB 0x80
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// Divisor latch register
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#define DL_LSB(BaudRate) ((UINT8)(115200L/BaudRate) & 0xff)
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#define DL_MSB(BaudRate) ((UINT8)((115200L/BaudRate) >> 0x08) & 0xff)
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// Modem control register
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#define DTR_ENB 0x01
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#define RTS_ENB 0x02
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#define OUT1_ENB 0x04
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#define OUT2_ENB 0x08
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#define LOOP_ENB 0x10
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// Line status register
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#define LINE_STATUS_RxRD 0x01
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#define LINE_STATUS_OVRE 0x02
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#define LINE_STATUS_PARE 0x04
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#define LINE_STATUS_FRME 0x08
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#define LINE_STATUS_BREK 0x10
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#define LINE_STATUS_TBE 0x20
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#define LINE_STATUS_TXE 0x40
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// Modem status register
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#define MDM_STATUS_DCTS 0x01
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#define MDM_STATUS_DDSR 0x02
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#define MDM_STATUS_DRI 0x04
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#define MDM_STATUS_DDCD 0x08
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#define MDM_STATUS_CTS 0x10
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#define MDM_STATUS_DSR 0x20
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#define MDM_STATUS_RI 0x40
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#define MDM_STATUS_DCD 0x80
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// BASE PORT Address
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#define PIC_MASK_PORT 0x21
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#define PIC_CTRL_PORT 0x20
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#define EOI 0x20
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//*****************************************************************//
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//*****************************************************************//
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//*****************************************************************//
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//** **//
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//** (C)Copyright 2014, American Megatrends, Inc. **//
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//** **//
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//** All Rights Reserved. **//
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//** **//
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//** 5555 Oakbrook Pkwy, Building 200,Norcross, Georgia 30093 **//
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//** **//
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//** Phone (770)-246-8600 **//
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//** **//
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//*****************************************************************//
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//*****************************************************************//
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//*****************************************************************//
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